The zynqmp gem driver support max MTU size 1536, so remove tftp
block size 4096 from defconfig and use default tftp block size.
Fixes: a33b4b96b3cf ("xilinx: Enable MBEDTLS/LWIP/WGET and WGET_HTTPS")
Signed-off-by: Padmarao Begari <padmarao.begari@amd.com>
Link: https://lore.kernel.org/r/20250304043030.2344536-1-padmarao.begari@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Added support for Infineon Octal flash components on the
Versal and Versal Net platforms.
Signed-off-by: Tejas Bhumkar <tejas.arvind.bhumkar@amd.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20250116051857.346921-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Activate the xSPI Software Reset support, which will be
utilized to transition from octal DTR mode to legacy
mode during shutdown and boot (if enabled).
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20241114042641.22642-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
The Micron MT35 series octal flashes can be activated
through the configuration option CONFIG_SPI_FLASH_MT35XU.
To ensure their detection, enable this option in the
default defconfig for octal flashes.
Signed-off-by: Tejas Bhumkar <tejas.arvind.bhumkar@amd.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20241114051047.13700-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> says:
This series adds support for Xilinx qspi parallel and
stacked memeories.
In parallel mode, the current implementation assumes that a maximum
of two flashes are connected. The QSPI controller splits the data
evenly between both the flashes so, both the flashes that are connected
in parallel mode should be identical.
During each operation SPI-NOR sets 0th bit for CS0 & 1st bit for CS1 in
nor->flags.
In stacked mode the current implementation assumes that a maximum of two
flashes are connected and both the flashes are of same make but can differ
in sizes. So, except the sizes all other flash parameters of both the flashes
are identical.
Spi-nor will pass on the appropriate flash select flag to low level driver,
and it will select pass all the data to that particular flash.
Write operation in parallel mode are performed in page size * 2 chunks as
each write operation results in writing both the flashes. For doubling the
address space each operation is performed at addr/2 flash offset, where addr
is the address specified by the user.
Similarly for read and erase operations it will read from both flashes, so
size and offset are divided by 2 and send to flash.
Enable the SPI_ADVANCE config option for all xilinx platforms, as
this is required for parallel-memories.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Enable setting speed mode using mmc dev commands.
The speed mode is provided as the last argument in these commands
(ex: mmc dev 0 0 10) and is indicated using the index from enum
bus_mode in include/mmc.h. A speed mode can be set if it is enabled
from device tree or from capabilities register
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20240708091755.5021-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
It is good to be aware what information is shared via smbios interface
that's why enable it by default.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Boards which have for example MAC address in eeprom but not in Xilinx
format (legacy or FRU) could reference it via nvmem cells.
For example:
&gem0 {
nvmem-cells = <&mac>;
nvmem-cell-names = "mac-address";
};
&eeprom {
#address-cells = <1>;
#size-cells = <1>;
mac: mac-address@f0 {
reg = <0xf0 6>;
};
};
For getting it work above DT changes are required but also CONFIG_NVMEM
should be enabled. That's why enable it by default in generic defconfigs
to be able to use it directly by changing DT only.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/9c8ee7a4c7a16367438a92a4c9581bac9d968f84.1712815454.git.michal.simek@amd.com
Switch PHY_ANEG_TIMEOUT to CONFIG_PHY_ANEG_TIMEOUT Kconfig symbol.
This removes one more configuration headers option finalizes its
Kconfig symbol conversion. No functional change expected.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Enabled the default utilization of the NFS command across all Xilinx
platforms to facilitate the booting of images through the network
using the NFS protocol.
Fixes: 10de12570799 ("disable NFS support by default")
Signed-off-by: Tejas Bhumkar <tejas.arvind.bhumkar@amd.com>
Link: https://lore.kernel.org/r/20240104045217.2966454-1-tejas.arvind.bhumkar@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Kernel Address Space Layout Randomization (KASLR) is a hardening
feature that aims to make it more difficult to take advantage
of known exploits in the kernel, by placing kernel data structures
at a random address at each boot.The bootloader supports randomizing
the virtual address at which the kernel image is loaded.
The bootloader must provide entropy by passing a random u64 value
in the /chosen/kaslr-seed device tree node.
When we run "kaslrseed" command from U-Boot, the bootloader will
genarate the kaslr-seed and update the /chosen/kaslr-seed DT property.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20230831032612.2729-4-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
HBM stands for high bandwidth memory and is a type of memory interface used
in 3D-stacked DRAM (dynamic random access memory) in some AMD GPUs (aka
graphics cards), as well as the server, high-performance computing (HPC)
and networking and client space. High Bandwidth Memory(HBM) has total 16
channels, one channel is divided into two pseudo channels which makes its
32 banks each with some amount of memory.
And then we have DDR_LOW PS low, DDR_HIGH0 PS high, DDR_HIGH1 PS very high
and pretty much there should be also place for PL DDR. So maximum number of
memory banks will be 36, updating the CONFIG_NR_DRAM_BANKS to 36.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/ed9eaf5c20501ee691d7d28a173511cd9a87f161.1690958095.git.michal.simek@amd.com
The current name is inconsistent with SPL which uses CONFIG_SPL_TEXT_BASE
and this makes it imposible to use CONFIG_VAL().
Rename it to resolve this problem.
Signed-off-by: Simon Glass <sjg@chromium.org>
ENV_OFFSET_REDUND config is by default set to 0 for flashes. Saving the env
variables is overwriting data at 0 offset, which is wrong. So add default
redund env offset for Zynq, ZynqMP, Versal and microblaze platforms.
Configured ENV_OFFSET_REDUND offsets by ENV_OFFSET + (2 * ENV_SIZE).
In case of versal, we configured ENV_OFFSET_REDUND at 0x7F00000 instead
of 0x7F80000. As BOOT_SCRIPT_OFFSET is already configured at 0x7F80000.
Added ENV_OFFSET_REDUND in Kconfig for microblaze due to dependency of
ENV_IS_IN_SPI_FLASH config.
Below table specifies platform specific env and env redund offsets.
PLAT ENV_OFFSET ENV_OFFSET_REDUND
---- ---------- -----------------
ZYNQ 0xE0000 0xE40000
ZYNQMP 0x1E00000 0x1E80000
VERSAL 0x7F40000 0x7F00000
MICROBLAZE 0x1080000 0x10C0000
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/92656dc08f0f5a749d62b71ca6e77fe1be72e9e0.1661340204.git.michal.simek@amd.com
With commit 55b3ba4c2ba4 ("spi: cadence_qspi: Migrate CONFIG_CQSPI_REF_CLK
to Kconfig") CONFIG_CQSPI_REF_CLK is moved to Kconfig.
The static value via Kconfig is a fallback option in case of clock
framework is not enabled or fails for some reason.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/fe7c38a19e878c307d5b75311bbfd8cf6c1f601e.1659691195.git.michal.simek@amd.com
Enable power domain driver to configure pmufw config object and request
node for all the IP's that are enabled in DT.
This driver depends on mailbox and IPI driver, hence enable them as well.
Add ARCH_VERSAL in the depends on of mailbox Kconfig to compile for
Versal platforms.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20220722084658.30995-6-ashok.reddy.soma@xilinx.com
