109 Commits

Author SHA1 Message Date
Weijie Gao
ece4e5804f clk: mediatek: add clock driver support for MediaTek MT7987 SoC
This patch adds clock driver support for MediaTek MT7987 SoC

Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2025-01-30 14:35:14 -06:00
Weijie Gao
b033dfb21d clk: mediatek: fix uninitialized fields issue in INFRA_MUX struct
This patch adds missing initialization of fields in INFRA_MUX struct
which caused uart broken after any other infra mux being enabled by
'clk_prepare_enable'

Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2025-01-23 12:11:49 -06:00
Sam Shih
5449167139 clk: mediatek: mt7629: fix gate offset of peri clock tree
The clock definitions in mt7629-clk.h indicate that CLK_PERIBUS_SEL is the
first element in the pericfg clock tree and also serves as a clock mux,
unlike other clocks belonging to the clock gate in pericfg.

This make the clock consumer get a wrong clock gate during request a clock
from <&pericfg>.

Since CLK_PERIBUS_SEL clock is not required in U-Boot, add a clock gate
offset for the pericfg clock tree to resolve this problem.

Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2025-01-21 09:28:43 -06:00
Weijie Gao
6e45549f4d clk: mediatek: mt7629: fix parent clock of some top clock muxes
According to the mt7629 programming guide, the CLK_TOP_F10M_REF_SEL
shares the same parent selection with CLK_TOP_IRRX_SEL, while the
present parent selection for CLK_TOP_F10M_REF_SEL is actually used
for CLK_TOP_SGMII_REF_1_SEL.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2024-12-31 10:58:52 -06:00
Tom Rini
aa2efb0873 Merge patch series "clk: mediatek: mt7622: clk migration for OF_UPSTREAM"
Christian Marangi <ansuelsmth@gmail.com> says:

These are all the required patches to migrate clk and correctly support
OF_UPSTREAM. This will align the clk index to upstream to support the same
clk implementation with downstream and upstream DTS.
2024-08-19 16:15:51 -06:00
Christian Marangi
105c78844a clk: mediatek: mt7622: add missing clock PERIBUS_SEL clock
Add missing PERIBUS_SEL clock to match upstream linux clk ID order. Also
convert pericfg to mux + gate implementation as now we have also mux on
top of gates.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:15:26 -06:00
Christian Marangi
a776493f4b clk: mediatek: mt7622: add missing clock PERI_UART4_PD
Add missing clock PERI_UART4_PD for peri clock gates. This is needed to
match upstream linux clk ID in preparation for OF_UPSTREAM.
Also convert infracfg to mux + gate implementation as now we have mux on
top of gates.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:15:26 -06:00
Christian Marangi
a942c0c3f5 clk: mediatek: mt7622: add missing clock MUX1_SEL
Add missing infra clock MUX1_SEL needed for CPU clock. This is needed to
match the upstream clk ID order in preparation for OF_UPSTREAM.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:15:26 -06:00
Christian Marangi
6dfa991204 clk: mediatek: mt7622: add missing clock define for MAIN_CORE_EN
Add missing clock for MAIN_CORE_EN. This is a special clock as it's a
gate for the APMIXED clocks required as a parent for CPU clocks.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:15:26 -06:00
Christian Marangi
7246138958 clk: mediatek: mt7622: move INFRA_TRNG to the bottom
Move INFRA_TRNG clock to the bottom of the clk ID to match upstream
linux order. This is in preparation of OF_UPSTREAM.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:15:26 -06:00
Christian Marangi
c7978fd395 clk: mediatek: mt7622: fix broken peri_cgs clk with XTAL parents
Fix broken peri_cgs clock with XTAL parents as they have wrong
definition of the parent type.

Correctly fix them and use CLK_PARENT_XTAL for them.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:15:26 -06:00
Tom Rini
f9e45be1a1 Merge patch series "clk: mediatek: mt7986: clk migration for OF_UPSTREAM"
Christian Marangi <ansuelsmth@gmail.com> says:

These are all the required patches to migrate clk and correctly support
OF_UPSTREAM. This will align the clk index to upstream to support the same
clk implementation with downstream and upstream DTS.
2024-08-19 16:15:13 -06:00
Christian Marangi
54f8ba658f clk: mediatek: mt7986: rename CK to CLK
Rename each entry from CK to CLK to match the include in upstream kernel
linux.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Tested-by: Frank Wunderlich <frank-w@public-files.de>
2024-08-19 16:14:44 -06:00
Christian Marangi
ba7969c5fb clk: mediatek: mt7986: convert to unified infracfg gates + muxes
Convert to infracfg gates + muxes implementation now that it's
supported.

Drop infracfg-ao nodes and rename all infracfg-ao clocks to infracfg.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:14:44 -06:00
Christian Marangi
efc82b035f clk: mediatek: mt7986: replace infracfg ID with upstream linux
Replace infracfg clk ID with upstream linux version.

The same format is used here with the factor first, then mux and then
gates.

To correctly reference the gates in clk_gate function, define the
gates_offs value in clk_tree now that they are at an offset from mux and
factor.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:14:44 -06:00
Christian Marangi
6636017ad3 clk: mediatek: mt7986: move INFRA_TRNG_CK to the bottom of the list
Move INFRA_TRNG_CK to the bottom of the list to have a 1:1 match with
upstream linux clock ID.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:14:44 -06:00
Christian Marangi
e4bdf9b004 clk: mediatek: mt7986: comment out CK_TOP_A_TUNER as not used
Comment out CK_TOP_A_TUNER as not used and not defined in upstream
kernel linux. This is to permit support of OF_UPSTREAM and have a 1:1
match with upstream linux clock ID.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:14:44 -06:00
Christian Marangi
7124b9928a clk: mediatek: mt7986: drop 1/1 spurious factor for topckgen
Now that we can have advanced parent handling for mux, we can drop
spurious topckgen 1/1 factor. This is in preparation to make the clk
ID match the ID in upstream include for mt7986.

Drop the factor entry from mt7986-clk.h and reference to them in
mt7981.dtsi. Muxes and gates are updated to reference the apmixed clk
following how it's done in upstream kernel linux. Add relevant clk type
flag in clk_tree for apmixed.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:14:43 -06:00
Christian Marangi
8cf99baf99 clk: mediatek: mt7986: reorder TOPCKGEN factor ID
Reorder TOPCKGEN factor ID to put TOP_FACTOR first and then PLL. This is
to match how it's done in upstream kernel linux and in preparation for
OF_UPSTREAM support.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:14:43 -06:00
Christian Marangi
1062187a4b clk: mediatek: mt7986: rename TOPCKGEN factor clock to upstream naming
Rename TOPCKGEN factor clock to upstream neaming.
Upstream kernel linux reference the factor clock for apmixedpll with the
"pll" suffix. Align the naming to the upstream naming format in
preparation for OF_UPSTREAM support.

Also rename rtc clock to drop the CB_ as upstream doesn't have that.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:14:43 -06:00
Christian Marangi
b87f40fb7e clk: mediatek: mt7986: fix typo for infra_i2c0_ck
Fix a typo for infra_i2c0_ck where 0 was misspelled as O.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:14:43 -06:00
Christian Marangi
a6c0761f65 clk: mediatek: mt7986: add missing entry for IPCIE_PIPE_CK infra gate
Add missing entry for IPCIE_PIPE_CK infra gate clock. Renumber the clock
order to match the expected offset in the gate array.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:14:43 -06:00
Christian Marangi
6df8029c9e clk: mediatek: mt7986: drop 1/1 infracfg spurious factor
Now that we can have advanced parent handling for mux, we can drop
spurious infracfg 1/1 factor. This is in preparation to make the clk
ID match the ID in upstream include for mt7986.

Drop the factor entry from mt7986-clk.h and reference to them in
mt7981.dtsi. Muxes and gates are updated to reference the topckgen clk
following how it's done in upstream kernel linux. Add relevant clk type
flag in clk_tree for infracfg and topckgen.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:14:43 -06:00
Christian Marangi
6267725ccc clk: mediatek: mt7986: fix wrong parent for INFRA_ADC_26M_CK
Fix wrong parent for INFRA_ADC_26M_CK as should be INFRA_ADC_FRC_CK
instead of INFRA_CK_F26M. This is to match implementation on upstream
kernel linux.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:14:43 -06:00
Christian Marangi
5e4ee4b354 clk: mediatek: mt7986: rename 66M_MCK to SYSAXI_D2
Upstream kernel linux clock include use SYSAXI_D2 instead of 66M_MCK.
Rename this clock to the upstream kernel in preparation for support of
OF_UPSTREAM.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:14:43 -06:00
Christian Marangi
e69a1fed16 clk: mediatek: mt7986: rename CB_CKSQ_40M to TOP_XTAL
Upstream kernel linux clock include use TOP_XTAL instead of CB_CKSQ_40M.
Rename this clock to the upstream kernel in preparation for support of
OF_UPSTREAM.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:14:43 -06:00
Christian Marangi
5dd509788d clk: mediatek: mt7986: fix wrong shift for PCIe clocks
Fix wrong shift for PCIe clocks. This cause the PCIe port to malfunction
as the gate clocks weren't correctly enabled.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:14:43 -06:00
Tom Rini
2f71d6ef32 Merge patch series "clk: mediatek: mt7988: clk migration for OF_UPSTREAM"
Christian Marangi <ansuelsmth@gmail.com> says:

These are all the required patches to migrate clk and correctly support
OF_UPSTREAM. This will align the clk index to upstream to support the same
clk implementation with downstream and upstream DTS.
2024-08-19 16:14:29 -06:00
Christian Marangi
99c5fa184b clk: mediatek: mt7988: rename CK to CLK
Rename each entry from CK to CLK to match the include in upstream kernel
linux.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Tested-by: Frank Wunderlich <frank-w@public-files.de>
2024-08-19 16:14:09 -06:00
Christian Marangi
ef4a648587 clk: mediatek: mt7988: convert to unified infracfg gates + muxes
Convert to infracfg gates + muxes implementation now that it's
supported.

Drop infracfg-ao nodes and rename all infracfg-ao clocks to infracfg.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:14:09 -06:00
Christian Marangi
4f100a0c70 clk: mediatek: mt7988: replace clock ID with upstream linux
Replace infracfg clk ID with upstream linux version.

The same format is used here with the factor first, then mux and then
gates.

To correctly reference the gates in clk_gate function, define the
gates_offs value in clk_tree now that they are at an offset from mux and
factor.

Drop any comment that reference the clock ID as we now have a 1:1 match
with upstream kernel linux.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:14:09 -06:00
Christian Marangi
6e54f037df clk: mediatek: mt7988: comment out infracfg clk not defined
Comment out infracfg clk not defined in upstream kernel linux clock ID
include. These clock are not used and can be safely commented. Keep them
just to have a reference of their existence.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:14:09 -06:00
Christian Marangi
d061f73a92 clk: mediatek: mt7988: drop 1/1 spurious factor for topckgen
Now that we can have advanced parent handling for mux, we can drop
spurious topckgen 1/1 factor. This is in preparation to make the clk
ID match the ID in upstream include for mt7988.

Drop the factor entry from mt7988-clk.h and reference to them in
mt7988.dtsi. Muxes and gates are updated to reference the apmixed clk
following how it's done in upstream kernel linux. Add relevant clk type
flag in clk_tree for apmixed and topckgen.

Also move TOP_XTAL to the fixed clock table following how it's done in
upstream linux kernel.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:14:09 -06:00
Christian Marangi
1bafda9851 clk: mediatek: mt7988: reorder TOPCKGEN factor ID
Reorder TOPCKGEN factor ID to put TOP_FACTOR first and then PLL. This is
to match how it's done in upstream kernel linux and in preparation for
OF_UPSTREAM support.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:14:09 -06:00
Christian Marangi
8b75c2c479 clk: mediatek: mt7988: rename TOPCKGEN factor clock to upstream naming
Rename TOPCKGEN factor clock to upstream neaming.
Upstream kernel linux reference the factor clock for apmixedpll with the
"pll" suffix. Align the naming to the upstream naming format in
preparation for OF_UPSTREAM support.

Also rename rtc clock to drop the CB_ as upstream doesn't have that.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:14:09 -06:00
Christian Marangi
78507c3a9f clk: mediatek: mt7988: drop 1/1 infracfg spurious factor
Now that we can have advanced parent handling for mux, we can drop
spurious infracfg 1/1 factor. This is in preparation to make the clk
ID match the ID in upstream include for mt7988.

Drop the factor entry from mt7988-clk.h and reference to them in
mt7988.dtsi. Muxes and gates are updated to reference the topckgen clk
following how it's done in upstream kernel linux.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:14:09 -06:00
Christian Marangi
caa5f27382 clk: mediatek: mt7988: fix wrong parent for INFRA_PCIE_PERI_26M_CK_P2
Fix wrong parent for INFRA_PCIE_PERI_26M_CK_P2 as should be
INFRA_PCIE_PERI_26M_CK_P3 instead of INFRA_F26M_O0. This is to match
implementation on upstream kernel linux.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:14:09 -06:00
Christian Marangi
49d11169f7 clk: mediatek: mt7988: move INFRA_PCIE_PERI_26M_CK_Px clock at top
Move INFRA_PCIE_PERI_26M_CK_Px clock at top of the infracfg gates
in preparation for support of OF_UPSTREAM to have a 1:1 match with
upstream clock ID.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:14:09 -06:00
Christian Marangi
603585892f clk: mediatek: mt7988: rename TOP_CK_NPU_SEL_CM_TOPS_SEL to TOP_NPU_SEL
Upstream kernel linux clock include use TOP_NPU_SEL instead of
TOP_CK_NPU_SEL_CM_TOPS_SEL.
Rename this clock to the upstream kernel in preparation for support of
OF_UPSTREAM.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:14:09 -06:00
Christian Marangi
e7ecdd5a46 clk: mediatek: mt7988: rename TOP_DA_SELM_XTAL_SEL to TOP_DA_SEL
Upstream kernel linux clock include use TOP_DA_SEL instead of
TOP_DA_SELM_XTAL_SEL.
Rename this clock to the upstream kernel in preparation for support of
OF_UPSTREAM.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:14:09 -06:00
Christian Marangi
b76b75bfc6 clk: mediatek: mt7988: rename CB_CKSQ_40M to TOP_XTAL
Upstream kernel linux clock include use TOP_XTAL instead of CB_CKSQ_40M.
Rename this clock to the upstream kernel in preparation for support of
OF_UPSTREAM.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:14:09 -06:00
Tom Rini
98cccbd680 Merge patch series "clk: mediatek: mt7981: clk migration for OF_UPSTREAM"
Christian Marangi <ansuelsmth@gmail.com> says:

These are all the required patches to migrate clk and correctly support
OF_UPSTREAM. This will align the clk index to upstream to support the same
clk implementation with downstream and upstream DTS.
2024-08-19 16:13:57 -06:00
Christian Marangi
02de3b9f04 clk: mediatek: mt7981: rename CK to CLK
Rename each entry from CK to CLK to match the include in upstream kernel
linux.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:13:13 -06:00
Christian Marangi
99da5bbd80 clk: mediatek: mt7981: convert to unified infracfg gates + muxes
Convert to infracfg gates + muxes implementation now that it's
supported.

Drop infracfg-ao nodes and rename all infracfg-ao clocks to infracfg.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:13:13 -06:00
Christian Marangi
2d20cc4064 clk: mediatek: mt7981: fix support for pwm3 clock
Add and fix support for pwm3 clock. In the pwm DTSI node we were
actually using PWM2 clock for PWM3. Now that we have correct ID also add
the missing entry of gate and mux to support PWM3 clock.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:13:13 -06:00
Christian Marangi
2967f21182 clk: mediatek: mt7981: replace infracfg ID with upstream linux
Replace infracfg clk ID with upstream linux version.

Add some missing clk for PWM3 and for PCIe. The same format is used here
with the factor first, then mux and then gates.

To correctly reference the gates in clk_gate function, define the
gates_offs value in clk_tree now that they are at an offset from mux and
factor.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:13:13 -06:00
Christian Marangi
78487cd093 clk: mediatek: mt7981: drop 1/1 spurious factor
Now that we can have advanced parent handling for mux, we can drop
spurious infracfg 1/1 factor. This is in preparation to make the clk
ID match the ID in upstream include for mt7981.

Drop the factor entry from mt7981-clk.h and reference to them in
mt7981.dtsi. Muxes and gates are updated to reference the topckgen clk
following how it's done in upstream kernel linux. Add relevant clk type
flag in clk_tree for infracfg and topckgen.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:13:13 -06:00
Christian Marangi
807624c1e1 clk: mediatek: mt7981: implement sgmii0/1 clock
Implement missing sgmii0/1 clock and update the compatible the DTS to
match upstream kernel linux and in preparation for OF_UPSTREAM support
since the ethernet node define these additional clocks.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:13:13 -06:00
Christian Marangi
e568997faa clk: mediatek: mt7981: fix wrong parent list for INFRA_PWM1_SEL mux
Fix wrong parent list for INFRA_PWM1_SEL mux. The list is incorrect and
the parents are just 2. This also match the upstream linux
implementation.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:13:13 -06:00
Christian Marangi
02af9cad70 clk: mediatek: mt7981: fix wrong parent for TOP_FAUD clock
Fix wrong parent for TOP_FAUD clock. Upstream linux sets the parent for
TOP_FAUD to TOP_AUD_SEL instead of CB_CKSQ_40M.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:13:13 -06:00