dram_para1 is different in the D1s DDR2 configuration, but investigation
shows its default value is not actually used, as a hardcoded value is
used in auto_scan_dram_rank_width(), and auto_scan_dram_size()
completely overwrites the existing value.
Clarify the logic here by splitting dram_para1 into its six different
fields, as done in dram_sunxi_dw.c.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Some of these unused parameters have different values on the D1s SoC,
which includes in-package DDR2. Make that explicit, instead of including
the values from the stock DDR3 configuration. We still keep the unused
parameters around for now, for comparison with the BSP DRAM parameters.
Signed-off-by: Samuel Holland <samuel@sholland.org>
On D1/D1s, the boot ROM enables the data cache, and it is left enabled
throughout SPL. Some DRAM controller settings affect the mapping of the
CPU address space, so the data cache must be flushed when changing them.
Signed-off-by: Samuel Holland <samuel@sholland.org>
The check is expected to pass on D1s, where the DRAM die has only one
bank, as signified by bit 12 being unset in the stock dram_para1 value.
Changing the offset matches the algorithm from dram_sunxi_dw.c (which
uses 2 bank bits + 9 page bits), and works on D1, D1s, and T113-S3.
Link: https://github.com/smaeul/sun20i_d1_spl/issues/14
Link: https://github.com/YuzukiHD/TinyKasKit/commit/1bc76937dcf3
Reported-by: YuzukiTsuru <gloomyghost@gloomyghost.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
As part of bringing the master branch back in to next, we need to allow
for all of these changes to exist here.
Reported-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Tom Rini <trini@konsulko.com>
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay
Ethernet"' I failed to notice that b4 noticed it was based on next and
so took that as the base commit and merged that part of next to master.
This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing
changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35.
Reported-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Tom Rini <trini@konsulko.com>
The Allwinner R528/T113-s/D1/D1s SoCs all share the same die, so use the
same DRAM initialisation code.
Make use of prior art here and lift some code from awboot[1], which
carried init code based on earlier decompilation efforts, but with a
GPL2 license tag.
This code has been heavily reworked and cleaned up, to match previous
DRAM routines for other SoCs, and also to be closer to U-Boot's coding
style and support routines.
The actual DRAM chip timing parameters are included in the main file,
since they cover all DRAM types, and are protected by a new Kconfig
CONFIG_SUNXI_DRAM_TYPE symbol, which allows the compiler to pick only
the relevant settings, at build time.
The relevant DRAM chips/board specific configuration parameters are
delivered via Kconfig, so this code here should work for all supported
SoCs and DRAM chips combinations.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Sam Edwards <CFSworks@gmail.com>
At the moment all Allwinner DRAM initialisation routines are stored in
arch/arm/mach-sunxi, even though those "drivers" are just a giant
collection of writel's, without any architectural dependency.
The R528/T113-s SoC (with ARM cores) and the D1/D1s Soc (with RISC-V
cores) share the same die, so should share the same DRAM init routines as
well.
To prepare for this, add a new sunxi directory inside drivers/ram, and
add some stub entries to prepare for the addition of the share DRAM code
for those SoCs.
The RISC-V D1(s) SoCs will probably use SPL_DM, so for that SoC this
would be the right directory anyway.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
