Replace infracfg clk ID with upstream linux version.
The same format is used here with the factor first, then mux and then
gates.
To correctly reference the gates in clk_gate function, define the
gates_offs value in clk_tree now that they are at an offset from mux and
factor.
Drop any comment that reference the clock ID as we now have a 1:1 match
with upstream kernel linux.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Comment out infracfg clk not defined in upstream kernel linux clock ID
include. These clock are not used and can be safely commented. Keep them
just to have a reference of their existence.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Now that we can have advanced parent handling for mux, we can drop
spurious topckgen 1/1 factor. This is in preparation to make the clk
ID match the ID in upstream include for mt7988.
Drop the factor entry from mt7988-clk.h and reference to them in
mt7988.dtsi. Muxes and gates are updated to reference the apmixed clk
following how it's done in upstream kernel linux. Add relevant clk type
flag in clk_tree for apmixed and topckgen.
Also move TOP_XTAL to the fixed clock table following how it's done in
upstream linux kernel.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reorder TOPCKGEN factor ID to put TOP_FACTOR first and then PLL. This is
to match how it's done in upstream kernel linux and in preparation for
OF_UPSTREAM support.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Rename TOPCKGEN factor clock to upstream neaming.
Upstream kernel linux reference the factor clock for apmixedpll with the
"pll" suffix. Align the naming to the upstream naming format in
preparation for OF_UPSTREAM support.
Also rename rtc clock to drop the CB_ as upstream doesn't have that.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Now that we can have advanced parent handling for mux, we can drop
spurious infracfg 1/1 factor. This is in preparation to make the clk
ID match the ID in upstream include for mt7988.
Drop the factor entry from mt7988-clk.h and reference to them in
mt7988.dtsi. Muxes and gates are updated to reference the topckgen clk
following how it's done in upstream kernel linux.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Fix wrong parent for INFRA_PCIE_PERI_26M_CK_P2 as should be
INFRA_PCIE_PERI_26M_CK_P3 instead of INFRA_F26M_O0. This is to match
implementation on upstream kernel linux.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Move INFRA_PCIE_PERI_26M_CK_Px clock at top of the infracfg gates
in preparation for support of OF_UPSTREAM to have a 1:1 match with
upstream clock ID.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Upstream kernel linux clock include use TOP_NPU_SEL instead of
TOP_CK_NPU_SEL_CM_TOPS_SEL.
Rename this clock to the upstream kernel in preparation for support of
OF_UPSTREAM.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Upstream kernel linux clock include use TOP_DA_SEL instead of
TOP_DA_SELM_XTAL_SEL.
Rename this clock to the upstream kernel in preparation for support of
OF_UPSTREAM.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Upstream kernel linux clock include use TOP_XTAL instead of CB_CKSQ_40M.
Rename this clock to the upstream kernel in preparation for support of
OF_UPSTREAM.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Christian Marangi <ansuelsmth@gmail.com> says:
These are all the required patches to migrate clk and correctly support
OF_UPSTREAM. This will align the clk index to upstream to support the same
clk implementation with downstream and upstream DTS.
Convert to infracfg gates + muxes implementation now that it's
supported.
Drop infracfg-ao nodes and rename all infracfg-ao clocks to infracfg.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Add and fix support for pwm3 clock. In the pwm DTSI node we were
actually using PWM2 clock for PWM3. Now that we have correct ID also add
the missing entry of gate and mux to support PWM3 clock.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Replace infracfg clk ID with upstream linux version.
Add some missing clk for PWM3 and for PCIe. The same format is used here
with the factor first, then mux and then gates.
To correctly reference the gates in clk_gate function, define the
gates_offs value in clk_tree now that they are at an offset from mux and
factor.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Now that we can have advanced parent handling for mux, we can drop
spurious infracfg 1/1 factor. This is in preparation to make the clk
ID match the ID in upstream include for mt7981.
Drop the factor entry from mt7981-clk.h and reference to them in
mt7981.dtsi. Muxes and gates are updated to reference the topckgen clk
following how it's done in upstream kernel linux. Add relevant clk type
flag in clk_tree for infracfg and topckgen.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Implement missing sgmii0/1 clock and update the compatible the DTS to
match upstream kernel linux and in preparation for OF_UPSTREAM support
since the ethernet node define these additional clocks.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Fix wrong parent list for INFRA_PWM1_SEL mux. The list is incorrect and
the parents are just 2. This also match the upstream linux
implementation.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Fix wrong parent for TOP_FAUD clock. Upstream linux sets the parent for
TOP_FAUD to TOP_AUD_SEL instead of CB_CKSQ_40M.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Swap wrong clock-names for spi nodes as they were wrong and the spi-clk
was referencing the sel-clk and the sel-clk was referencing the spi-clk.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Fix wrong mux width for pwm2 and pwm1. Upstream have width 1 but U-Boot
have width set to 2. Change the value to follow upstream implementation.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Add missing clock for infra_ipcie_pipe to make PCIe correctly work. This
clock is a parent of the fixed clock from topckgen cb_cksq_40m.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Christian Marangi <ansuelsmth@gmail.com> says:
These are all the required patches to migrate clk and correctly support
OF_UPSTREAM. This will align the clk index to upstream to support the same
clk implementation with downstream and upstream DTS.
Upstream kernel linux makes use of peri clock MUX to setup UART.
Add definition for these and add remap table as in the upstream clock ID
order gates are before MUX but we require MUX first and then clocks in
our downstream driver.
Convert the peri clk tree to MUX + GATE implementation.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Tested-by: Frank Wunderlich <frank-w@public-files.de>
Define remap table also for apmixedsys clock ID. The clock ID starts
from 1 instead of 0 in upstream kernel linux.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Define id_offs_map and use clk ID form upstream linux kernel to have a
1:1 match for the TOPCKGEN clock and permit usage of OF_UPSTREAM with
upstream dtsi.
For all the gate clock, the clk ID starts from 1 instead of zero. Define
an additional clock tree for them and set the .gates_offs to 1 to
account for this.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Fix broken peri_cgs and infra_cgs clock with XTAL parents as they have
wrong definition of the parent type.
Correctly fix them and use CLK_PARENT_XTAL for them.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
eMMC is enabled on E850-96 board now. Mention that in the board
documentation.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Enable MMC subsystem and DW MMC driver support to make eMMC functional.
Also enable a couple of related commands so the user can make use of
eMMC from U-Boot shell.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Upstream properties were added to device trees to follow current Linux
kernel. DW MMC driver was updated accordingly. Safely remove outdated
MMC properties. Details on removed properties are as follows:
* samsung,removable: replaced by non-removable
* samsung,bus-width: replaced by bus-width
* samsung,timing:
- replaced by samsung,dw-mshc-ciu-div and samsung,dw-mshc-sdr-timing
in dw_mmc nodes
- removed from sdhci nodes (it's neither described in bindings, nor
it's used in s5p_sdhci.c driver)
* fifoth_val: replaced by fifo-depth
* bus_hz: replaced by clock-frequency
* div: the fixed CIU clock divider value was moved to the chip data in
exynos_dw_mmc.c driver
No functional change.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Fix most of checkpatch warnings and other obvious style issues.
No functional change.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Reduce U-Boot footprint by reusing dev->name as a driver's displayed
name. This changes boot device name (and "mmc info" output) from "EXYNOS
DWMMC" to something like "mmc@12100000".
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
add_dwmci() is already calling dwmci_setup_cfg() internally, there is no
needed to call dwmci_setup_cfg() again in case when add_dwmci() is used
(for non-DM cases). Fix it by calling dwmci_setup_cfg() only in DM
cases, when add_dwmci() wasn't called. Also, this assignment:
host->mmc = &plat->mmc;
is wrong in non-DM case when add_dwmci() was called, as it's creating
mmc object internally. Fix that by pulling that assignment into DM case,
when add_dwmci() isn't called.
While at it, add also this missing assignment:
host->mmc->dev = dev;
Fixes: 3537ee879e04 ("mmc: exynos_dw_mmc: support the Driver mode for Exynos")
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
There is no logical sense to split the initialization code between
multiple functions. Pull both do_dwmci_init() and
exynos_dwmci_core_init() into exynos_dwmmc_probe() to make the code more
simple and obvious.
No functional change.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Add the compatible entry and corresponding chip data for Exynos7
compatible chips, which covers modern ARM64 based Exynos chips. They
have some differences w.r.t. old ARM32 Exynos chips:
- CLKSEL register offset is different
- 64-bit IDMAC descriptor and 64-bit IDMAC registers are used
(implemented in dw_mmc core driver)
In terms of the driver implementation, the CIU clock is obtained via CCF
framework (as opposed to ad-hoc clock driver implementation for ARM32
chips).
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
By now exynos_dw_mmc driver was relying on the correct CIU clock
frequency being set on driver init. But dw_mmc core is actually trying
to change CIU clock rate dynamically, on init and in set_ios() callback,
which it's requesting via host->get_mmc_clk() callback (the name is
misleading: although it's called "get_mmc_clk()", it can actually
request both get and set operations). Implement setting the requested
rate for CIU clock in Exynos driver to achieve the correct dw_mmc core
driver operation at all times. DDR mode requires the clock to be twice
as fast (when 8 bit bus is used), so handle this too, to make DDR
function properly.
This change makes the eMMC throughput on E850-96 board twice as fast.
That's because "clock-frequency" is set to 800 MHz in E850-96 device
tree, but for DDR52 mode it should be 416 MHz (and TRM states it should
be 400 MHz for DDR50/8bit mode). The dw_mmc core is requesting 52 MHz
bus_hz for DDR52 mode, and DDR+8bit mode means it should be x2 fast, so:
f_ciu = 2 * ciu_div * f_bus = 2 * 4 * 52e6 = 416 MHz,
where f_ciu - freq of clock fed to DW MMC block from CMU (SDCLKIN), Hz
f_bus - freq of clock fed to the card (CCLKIN), Hz
ciu_div - value of internal divider (in DW MMC block).
Another way to work that around would be overriding the
"clock-frequency" property in corresponding dts. But setting the clock
frequency dynamically as it's done here looks much neater.
This implementation follows what's done in Linux kernel dw_mmc-exynos
driver in .set_ios() callback for MMC_TIMING_MMC_DDR52 case.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
DDR timing values should be defined in "samsung,dw-mshc-ddr-timing" dts
property, and used when DDR MMC mode is selected. Read that value from
dts and use it. If it's not available, use SDR timing values instead.
This change is following upstream Linux kernel implementation.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
host->quirks field is only used internally in exynos_dw_mmc.c driver.
To avoid cluttering the scope of struct dwmci_host, move quirks field
into Exynos driver's chip data, where it can be statically defined.
No functional change.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Instead of using non-standard "bus_hz" dts property, read common
"clock-frequency" property used in upstream Linux kernel. It's safe to
do so, as "clock-frequency" property was already added to corresponding
nodes in all affected Exynos device tree files.
No functional change.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Instead of using non-standard "samsung,bus-width" dts property, read
common "bus-width" property used in upstream Linux kernel. It's safe to
do so, as "bus-width" property was already added to corresponding nodes
in all affected Exynos device tree files.
No functional change.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Some chips like Exynos4412 have fixed internal CIU clock divider.
Instead of reading it from non-standard "div" dts property, store its
value in the driver internally, in static chip data associated with
corresponding compatible. This makes it possible to avoid using
host->div for storing it, so the latter can be removed safely. Also
create a helper function called exynos_dwmmc_get_ciu_div() for getting
the current div value: in case the fixed div is provided in the chip
data it will be used, otherwise the current div value is being read from
CLKSEL register.
The insights for this change were taken from dw_mmc-exynos.c driver in
Linux kernel.
No functional change.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
CLKSEL register offset may vary between different Exynos chips, e.g. on
ARM64 vs ARM32 chips. Provide a way to specify its offset value for each
compatible instead of hard-coding its value in read/write calls.
No functional change.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
The obsolete "samsung,timing" dts property is now split into
"samsung,dw-mshc-ciu-div" (for holding the internal DW MMC divider
value) and "samsung,dw-mshc-sdr-timing" (for actual timing values) in
upstream Linux kernel. Rework the driver to make use of new properties
instead of the old one. All affected dts files were already updated
accordingly.
No functional change.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Update the driver to use livetree API instead of FDT one.
No functional change.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
exynos_dwmci_get_config() is called from the probe function and used to
read data from device tree. Make use of .of_to_plat driver callback
instead, and convert exynos_dwmci_get_config() to match its signature.
No functional change.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
