Add configurations for the Videostrong KII Pro set-top box.
This defconfig is cloned from the WeTek Play2's.
Signed-off-by: Ferass El Hafidi <vitali64pmemail@protonmail.com>
Link: https://lore.kernel.org/r/20230507124109.31778-3-vitali64pmemail@protonmail.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
The AD401 board is the Amlogic A1 SoC reference board
Signed-off-by: Igor Prusov <ivprusov@sberdevices.ru>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230505125639.3605-6-ivprusov@sberdevices.ru
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Two conflicting bootcmds were included in the environment.
Streamline to defining the bootcmd only in the env file.
Signed-off-by: Eduard Strehlau <eduard@lionizers.com>
Signed-off-by: Fabio Estevam <festevam@denx.de>
This command is useful to power off the system from within U-Boot.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom <twarren@nvidia.com>
This command is useful to power off the system from within U-Boot.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom <twarren@nvidia.com>
DM_FLAG_PRE_RELOC flag is added into some drivers
by recent commits such as
1bd790bc4b ("firmware: psci: enable DM_FLAG_PRE_RELOC").
Current SYS_MALLOC_F_LEN of SynQuacer Developerbox platform
is too small, Developerbox will not boot due to lack of
heap memory.
This commit increases the size of heap memory.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Acked-by: Jassi Brar <jaswinder.singh@linaro.org>
Enable the newest features: nvmxip, fwu-metadata and
gpt. Commands to print the partition info, gpt info
and fwu metadata will be available.
Adjust also env boot script the address of the
bootbank with the new gpt layout, and also remove
the not needed kernel address bank0 and bank1
and retrieve function that would test the bank flag
before and now we are getting the info from the fwu
metadata.
Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
We need to distinguish between boot banks and from which
partition to load the kernel+initramfs to memory.
For that, fetch the boot index, fetch the correspondent
partition, calculate the correct kernel address and
then set the env variable kernel_addr with that value.
Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
Reduces the CONFIG_DDR_CACHEABLE_SIZE, the size of DDR mapped cacheable
before relocation, to support DDR with only 256MB because the OP-TEE
reserved memory is located at end of the DDR.
By default the new size of 128MB cacheable memory is enough
in dram_bank_mmu_setup() for early_enable_caches() in arch_cpu_init()
and is correct for DDR size = 256MB.
After relocation the real size of DDR, excluding the no-map reserved
memory, is used after the U-Boot device tree parsing.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
The ITS file used to build the images here lists three dtb files as
being used. Today, these are built by the logic that will over-build dtb
files based on SOC/etc symbols being set. To future proof this platform
and be generally correct, we list all 3 of the device trees used here in
OF_LIST.
Cc: Marek Vasut <marex@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Remove the support of the fastboot "oem format" command for STM32MP15x
boards and removed the associated env variable "partitions".
This command is not required; with fastboot tool, the GPT partition can
be handle with "flash" command in "gpt" target (=CONFIG_FASTBOOT_GPT_NAME),
for example: fastboot flash gpt gpt.bin
This patch avoids to define the GPT partitioning in U-Boot environment,
which is incompatible with planned modifications, for example to
support TF-A firmware update.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
The CONFIG_FASTBOOT_USB_DEV is used to select USB OTG controller other
than 0 but it is not the case for STM32MP15 boards; it can be removed
to simplify the STM32MP15 defconfig files.
On STM32MP15x boards, we have only one USB device with instance 0,
so the device is hardcoded arch/arm/mach-stm32mp/cpu.c with
the command "fastboot 0" and this define is not used in config files
(include/configs/stm32mp15_st_common.h).
Fixes: 4633fd51c5d7 ("stm32mp1: activate FASTBOOT on eMMC")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Disable CMD_MTDPARTS as it's no more needed and it is strongly
encouraged to avoid using this command anymore.
(see comments in ./cmd/Kconfig:2422).
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Copy the fixed partition nodes from U-Boot device tree to Linux kernel
device tree to dynamically configure the MTD partitions.
fdt_copy_fixed_partitions is only based on device tree
and replace the function fdt_fixup_mtdparts based on mtdparts variable;
the variable mtdid and mtdparts are not more required.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Add partitions subnode in flash0 and nand nodes for all stm32mp157xx-ev1
boards. Update only the file stm32mp157c-ev1-*u-boot.dtsi, included by
other files stm32mp15*-ev1-*-u-boot.dtsi.
For SCMI variant of device tree used with stm32mp15_defconfig
add partitions needed by TF-A firmware update:
- metadata to save the TF-A information: 2 copy
- fip-a / fip-b: two FIP slots, used for system A/B (seamless) update
- the previous "fsbl" partition with 2 copy of TFA is replaced
by 2 partitions (only one copy in each MTD partition) to simplify
the update: no need to managed this copy on update, need to update the
two partition (skip bad block for NAND)
The offset for ENV partition are also updated in stm32mp15_defconfig
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
With DM_ETH configured by default, complete the Ethernet enablement for
LS1046AFRWY by activating DM_MDIO.
Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Add the RAM_ROCKCHIP_LPDDR4 to fix the Pinephone Pro booting.
When the configs were updated in 26f92be07e2 it somehow broke
the PPP boot process so let's fix it.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
CC: Jagan Teki <jagan@edgeble.ai>
CC: Kever Yang <kever.yang@rock-chips.com>
The board comes with SMSC LAN8710A PHY, enable matching driver.
Enable DM_ETH_PHY in the process to start using DM drivers more.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
---
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Michal Simek <michal.simek@amd.com>
Cc: Nishanth Menon <nm@ti.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Add code to support FWU_MULTI_BANK_UPDATE.
The platform does not have gpt-partition storage for
Banks and MetaData, rather it used SPI-NOR backed
mtd regions for the purpose.
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
Towards enabling FWU and supporting new firmware layout in NOR flash,
make u-boot PIC and adjust uboot env offset in flash.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
Add board code for the R8A77980 V3HSK board.
Add CPLD sysreset driver to the R-Car V3H SK board.
Extracted from a larger patch by Valentine Barshak.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Sync configs and board code with V3H Condor, squash CPLD driver in]
Add board code for the R8A77970 V3MSK board.
Add CPLD sysreset driver to the R-Car V3M SK board.
Extracted from a larger patch by Valentine Barshak.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Sync configs and board code with V3M Eagle, squash CPLD driver in]
The Lctech Pi F1C200s (also previously known under the Cherry Pi brand)
is a small development board with the Allwinner F1C200s SoC. This is the
same as the F1C100s, but with 64MB instead of 32MB co-packaged DRAM.
Add a defconfig for this board, enabling the most basic features. This
uses the new 64MB memory map, which avoids the very tight memory map we
use for the 32MB F1C100s board(s).
The devicetree file is already in the tree, courtesy of the previous
Linux repo sync.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This is required for UART boot flow where u-boot.img needs to be
downloaded via YMODEM.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
This platform is currently unmaintained and untested, so remove it.
Further, as it is the only TI816X SoC example, remove related files as
well.
Signed-off-by: Tom Rini <trini@konsulko.com>
In non-combined boot flow for K3, all the firewalls are locked by default
until sysfw comes up. Rom configures some of the firewall for its usage
along with the SRAM for R5 but the PSRAM region is still locked.
The K3 MCU Scratchpad for j721e was set to a PSRAM region triggering the
firewall exception before sysfw came up. The exception started happening
after adding multi dtb support that accesses the scratchpad for reading
EEPROM contents.
The commit changes R5 MCU scratchpad for j721e to an SRAM region.
Old Map:
┌─────────────────────────────────────┐ 0x41c00000
│ SPL │
├─────────────────────────────────────┤ 0x41c40000 (approx)
│ STACK │
├─────────────────────────────────────┤ 0x41c85b20
│ Global data │
│ sizeof(struct global_data) = 0xd8 │
├─────────────────────────────────────┤ gd->malloc_base = 0x41c85bfc
│ HEAP │
│ CONFIG_SYS_MALLOC_F_LEN = 0x70000 │
├─────────────────────────────────────┤ CONFIG_SPL_BSS_START_ADDR
│ SPL BSS │ (0x41cf5bfc)
│ CONFIG_SPL_BSS_MAX_SIZE = 0xA000 │
└─────────────────────────────────────┘ CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX
(0x41cffbfc)
New Map:
┌─────────────────────────────────────┐ 0x41c00000
│ SPL │
├─────────────────────────────────────┤ 0x41c40000 (approx)
│ EMPTY │
├─────────────────────────────────────┤ 0x41c81920
│ STACK │
│ SPL_SIZE_LIMIT_PROVIDE_STACK=0x4000 │
├─────────────────────────────────────┤ 0x41c85920
│ Global data │
│ sizeof(struct global_data) = 0xd8 │
├─────────────────────────────────────┤ gd->malloc_base = 0x41c859f0
│ HEAP │
│ CONFIG_SYS_MALLOC_F_LEN = 0x70000 │
├─────────────────────────────────────┤ CONFIG_SPL_BSS_START_ADDR
│ SPL BSS │ (0x41cf59f0)
│ CONFIG_SPL_BSS_MAX_SIZE = 0xA000 │
├─────────────────────────────────────┤ 0x41cff9fc
│ NEW MCU SCRATCHPAD │
│ SYS_K3_MCU_SCRATCHPAD_SIZE = 0x200 │
└─────────────────────────────────────┘ CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX
(0x41cffbfc)
Fixes: ab977c8b91b4 ("configs: j721s2_evm_r5: Enable support for building multiple dtbs into FIT")
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
[n-francis@ti.com: SRAM allocation addressing diagram]
Signed-off-by: Neha Francis <n-francis@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com>
K3 devices have runtime type board detection. Make the default defconfig
include the secure configuration. Then remove the HS specific config.
Non-HS devices will continue to boot due to runtime device type detection.
If TI_SECURE_DEV_PKG is not set the build will emit warnings, for non-HS
devices these can be ignored.
Reviewed-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Acked-by: Andrew Davis <afd@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
As the ddr timing info will be saved at the last 16KB of
the OCRAM, spl stack & bss base should be updated to avoid
conflict.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Add a static u-boot config for i.MX93 low drive mode support. When
low drive mode is enabled, VDD_SOC is set to 0.75V. Bus clocks,
A55 core clock (900Mhz), DDR clock (1866MTS), and some peripherals
clocks (USDHC/FLEXSPI/PDM/DISP_PIX/CAM_PIX) must decrease to meet
max frequencies in low drive mode.
Also set standby voltage for buck1
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Add sfc and flash node to device tree and config options to enable
support for booting from SPI NOR flash on Radxa ROCK 5 Model B.
Similar to RK3568 the BootRom in RK3588 can read all data and look for
idbloader at 0x8000, same as on SD and eMMC.
Use the rksd format and modify the mkimage offset to generate a bootable
u-boot-rockchip-spi.bin that can be written to 0x0 of SPI NOR flash. The
FIT image is loaded from 0x60000.
=> sf probe
SF: Detected mx25u12835f with page size 256 Bytes, erase size 4 KiB, total 16 MiB
=> load mmc 1:1 10000000 u-boot-rockchip-spi.bin
1492992 bytes read in 129 ms (11 MiB/s)
=> sf update $fileaddr 0 $filesize
device 0 offset 0x0, size 0x16c800
1300480 bytes written, 192512 bytes skipped in 11.103s, speed 137694 B/s
The BROM_BOOTSOURCE_ID value read back when booting from SPI flash does
not match the expected value of 3 (SPINOR) used by other SoCs. Instead a
value of 6 is read back, add a new enum value to handle this new
bootsource id.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Eugen Hristev <eugen.hristev@collabora.com>
The phycore-rk3288 SPL binary is reaching the limits of 32KB very often.
Enable CONFIG_LTO to reduce the size of the SPL and make the board more
future proof for changes increasing the SPL size.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
If u-boot is installed on the internal emmc, then this will
allow to boot without failure.
Signed-off-by: Wolfgang Zarre <lxdev12@zirdeon.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Update defconfig for rk3588-rock-5b with new defaults.
Remove the SPL_ROCKCHIP_BACK_TO_BROM=y option, SPL is expected to load
next stage from a FIT image and then jump to next stage not back to
BootRom.
Extend SPL_MAX_SIZE to 0x40000, SPL is loaded to 0x0 and TF-A is loaded
to 0x40000, use the space in between as SPL_MAX_SIZE.
Add config option to include useful gpio cmd.
Remove the CONFIG_NET_RANDOM_ETHADDR=y option, ethaddr and eth1addr is
set based on cpuid read from OTP.
Add CONFIG_SYS_NS16550_MEM32=y to use 32bit access of serial register.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Update defconfig for rk3588-evb with new defaults.
Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash
of FIT images. This help indicate if there is an issue loading any of
the images to DRAM or SRAM.
Extend SPL_MAX_SIZE to 0x40000, SPL is loaded to 0x0 and TF-A is loaded
to 0x40000, use the space in between as SPL_MAX_SIZE.
Add config options to include useful gpio and regulator cmd.
Remove the CONFIG_NET_RANDOM_ETHADDR=y option, ethaddr and eth1addr is
set based on cpuid read from OTP.
Remove CONFIG_DEBUG_UART_ANNOUNCE=y to remove debug messages.
Add CONFIG_SYS_NS16550_MEM32=y to use 32bit access of serial register.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Like other Rockchip SoCs, DM_RESET and DM_REGULATOR_FIXED is useful
across RK3588 platform. Select them from arch Kconfig.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
