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5 Commits

Author SHA1 Message Date
Michal Simek
c5cd2d2aba arm: dts: xilinx: Remove undocumented is-dual property 
Xilinx was using in past is-dual property for QSPIs to reflect their
configurations. But handling for them never reached upstream code that's
why better to remove them.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/15980560b98672959a889ff9970cbe9540b4ed69.1695808563.git.michal.simek@amd.com
 2023-10-09 12:13:04 +02:00
Michal Simek
174d728471 arm64: zynqmp: Switch to amd.com emails 
Update my and DPs email address to match current setup.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/aba5b19b9c5a95608829e86ad5cc4671c940f1bb.1688992543.git.michal.simek@amd.com
 2023-07-21 09:00:38 +02:00
Michal Simek
0da6d5a9e2 ARM: zynq: Switch from earlyprintk to earlycon 
Switch to earlycon which is preffered over earlyprintk.
It is also sync with Linux kernel (zynq-microzed).

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/d280fa18068f80412cf12c235c5245651e7062e2.1679987839.git.michal.simek@amd.com
 2023-05-15 09:33:57 +02:00
Simon Glass
8c103c33fb dm: dts: Convert driver model tags to use new schema 
Now that Linux has accepted these tags, move the device tree files in
U-Boot over to use them.

Signed-off-by: Simon Glass <sjg@chromium.org>
 2023-02-14 09:43:26 -07:00
Michal Simek
6bfe3fffac arm: zynq: Add support for DLC20 board 
Xilinx DLC20 has I2C0 with EEPROM(1KB), UART1, GPIO, SD0 (EMMC 4GB),
USB0 device, ENET0, QSPI (16MB) and DDR(two of 256MB each).

Boards have mix of Winbond/ST QSPIs.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
 2018-10-16 14:58:45 +02:00