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3 Commits

Author SHA1 Message Date
Chris Packham
f52e2d884c arm: mvebu: ac5: Define mvebu_get_nand_clock() 
The NF_CLK for the AC5 SoC runs at 400MHz. There's no strapping
or gating require so just add a mvebu_get_nand_clock() that
returns this value.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
 2023-07-13 10:26:27 +02:00
Tom Rini
f47c765dbe mvebe: Drop ARCH_MISC_INIT from alleycat 5 
In this platform, arch_misc_init doesn't perform any real function. The
call to get_soc_type_rev has no lasting side effects.

Cc: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
 2023-03-02 15:32:25 -05:00
Chris Packham
7d7bb99e22 arm: mvebu: Support for 98DX25xx/98DX35xx SoC 
Add support for the Allecat5/Alleycat5X SoC. These are L3 switches with
an integrated CPU (referred to as the CnM block in Marvell's
documentation). These have dual ARMv8.2 CPUs (Cortex-A55). This support
has been ported from Marvell's SDK which is based on a much older
version of U-Boot.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
 2022-11-07 07:46:28 +01:00