5 Commits

Author SHA1 Message Date
Samuel Holland
e4fd49ae30 power: regulator: Add a driver for the AXP PMIC drivevbus
The first AXP regulator converted to use the regulator uclass is the
drivevbus switch, since it is used by the USB PHY driver.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-11-19 14:03:50 -06:00
Samuel Holland
3e5446194a power: pmic: axp: Bind regulators from the DT
Now that a regulator driver exists for this PMIC, hook it up to the
device tree "regulators" subnodes.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-11-19 13:55:46 -06:00
Samuel Holland
f68a53ec77 power: pmic: axp: Provide a variant ID in the driver data
Subordinate regulator drivers can use this enumerated ID instead of
matching the compatible string again.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-11-19 13:40:31 -06:00
Samuel Holland
95d9ffd7b6 power: pmic: axp: Implement poweroff via sysreset
The AXP PMICs have the ability to power off the system. The existing
code for this is duplicated for each PMIC variant, and uses the legacy
non-DM "pmic_bus" interface. When SYSRESET is enabled, this can all be
replaced with a sysreset device using the DM_PMIC interface.

Since the trigger bit is the same on all PMIC variants, use the register
definitions from the oldest supported PMIC.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-25 14:51:03 +01:00
Samuel Holland
526c4f2e43 power: pmic: Add a driver for X-Powers AXP PMICs
These PMICs provide some combination of battery charger, fuel gauge,
GPIOs, regulators, and VBUS routing. These functions are represented
as child nodes in the device tree. Add the minimal driver needed to
probe these child devices and provide the DM_PMIC ops.

Enable the driver by default for SoCs that normally pair with a PMIC.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-12 09:41:57 +01:00