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3 Commits

Author SHA1 Message Date
Michal Simek
df09969070 arm: zynq: Fix indentation for zynq-cse targets 
Trivial DT style fixes.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
 2018-08-06 08:44:35 +02:00
Michal Simek
7996fcca9d arm: zynq: Remove fclk-enable property for cse-nor target 
Mini cse NOR configuration is running without PL that's why there is no
reason to enable clock to PL.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
 2018-08-06 08:44:35 +02:00
Siva Durga Prasad Paladugu
1c310aec67 arm: zynq: Add parallel NOR flash mini u-boot configuration for zynq 
Add configuration files/dtses for mini u-boot configuration
which runs on smaller footprint OCM memory. This configuration
only has required parallel nor flash support.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
 2018-07-19 10:49:56 +02:00