The FIT name in RISC-V Falcon mode should be different from that in
normal boot mode; it is called linux.itb. If the setting is missing
in common/spl, the normal boot file name will be used.
Signed-off-by: Randolph <randolph@andestech.com>
Add document for Banana Pi F3 board which based on SpacemiT's K1 SoC.
Signed-off-by: Kongyang Liu <seashell11234455@gmail.com>
Signed-off-by: Huan Zhou <pericycle.cc@gmail.com>
Tested-by: Marcel Ziswiler <marcel@ziswiler.com>
Reviewed-by: Yixun Lan <dlan@gentoo.org>
Add basic support for SpacemiT's Banana Pi F3 board.
Update the k1.dtsi align with mainline.
Note that the device tree files follow the mainline Linux source[1].
Links: https://patches.linaro.org/project/linux-serial/patch/20240730-k1-01-basic-dt-v5-8-98263aae83be@gentoo.org/ [1]
Signed-off-by: Kongyang Liu <seashell11234455@gmail.com>
Signed-off-by: Huan Zhou <pericycle.cc@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Yixun Lan <dlan@gentoo.org>
Tested-by: Marcel Ziswiler <marcel@ziswiler.com>
Enable driver for DesignWare MSHC. TH1520 supports all
speed modes up to HS400ES and UHS SDR105.
Also enable ADMA and mmc command.
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com>
Add SDHCI and EMMC controlles nodes on TH-1520 SoC. And enable them for
Lichee module 4A.
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com>
Add support for DesignWare SDHCI host controller on Alibaba TH1520 SoC
Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com>
Tested-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
The imply statements should be sorted in the sequence
of appearance in .config.
Tested-by: Anand Moon <linux.amoon@gmail.com>
Tested-by: E Shattow <lucent@gmail.com>
Suggested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Get product ID and the other information from EEPROM, use them to select
the correct DTB.
Tested-by: Anand Moon <linux.amoon@gmail.com>
Tested-by: E Shattow <lucent@gmail.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
The prefix "SPL_" is not needed when using CONFIG_IS_ENABLED().
Tested-by: Anand Moon <linux.amoon@gmail.com>
Tested-by: E Shattow <lucent@gmail.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Fixes: 5ecf9b0b8a75 ("board: starfive: add StarFive VisionFive v2 board support")
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Support multiple DTBs for JH7110 based boards, so they can
select the correct DT at runtime.
Tested-by: Anand Moon <linux.amoon@gmail.com>
Tested-by: E Shattow <lucent@gmail.com>
Reviewed-by: E Shattow <lucent@gmail.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
So JH7110 based boards can select their own DT at runtime.
Tested-by: Anand Moon <linux.amoon@gmail.com>
Tested-by: E Shattow <lucent@gmail.com>
Reviewed-by: E Shattow <lucent@gmail.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
As OF_UPSTREAM is implemented, these code are redundant.
Tested-by: Anand Moon <linux.amoon@gmail.com>
Tested-by: E Shattow <lucent@gmail.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
To support the other JH7110 based boards, add u-boot
device tree for them.
Tested-by: Anand Moon <linux.amoon@gmail.com>
Tested-by: E Shattow <lucent@gmail.com>
Reviewed-by: E Shattow <lucent@gmail.com>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Cc: H Bell <dmoo_dv@protonmail.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
To support JH7110 based boards besides v1.3B,
add a common dtsi and add common code to it.
Tested-by: Anand Moon <linux.amoon@gmail.com>
Tested-by: E Shattow <lucent@gmail.com>
Reviewed-by: E Shattow <lucent@gmail.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
There are difference between upstream DT and the old DT
in terms of reg base, reset gpio and syscon. Make the driver
compatible with upstream DT.
Tested-by: Anand Moon <linux.amoon@gmail.com>
Tested-by: E Shattow <lucent@gmail.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Make the U-Boot JH7110 MMC driver compatible with upstream DT.
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Add u-boot features to the U-Boot device tree.
Tested-by: Anand Moon <linux.amoon@gmail.com>
Tested-by: E Shattow <lucent@gmail.com>
Reviewed-by: E Shattow <lucent@gmail.com>
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Enable OF_UPSTREAM to use upstream DT and add starfive/ prefix to
the DEFAULT_DEVICE_TREE. Rename jh7110-starfive-visionfive-2-u-boot.dtsi
to jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi and set the v1.3b
device tree as the default device tree.
Drop redundant DT files from arch/riscv/dts/ and redundant clock and
reset definitions from include/dt-bindings/.
Since the old clock definitions is a little different from those in
upstream Linux, update the clock definitions in clock drivers
accordingly.
Tested-by: Anand Moon <linux.amoon@gmail.com>
Tested-by: E Shattow <lucent@gmail.com>
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Import a slightly modified version of the LicheeRV Nano and SG2002
device trees from the Linux Kernel. The current supported IPs are UART,
MMC, Timer, PLIC and CLINT.
Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
Provide a page describing the usage of U-Boot on the LicheeRV Nano and a
description of the board.
Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
This is a debug command to monitor the retention state of the data on
the array. The command needs a duplication of the mtd_read_oob()
function to actually return the maximum number of bitflips encountered
while reading the page. We could write a specific implementation for the
Sunxi driver but this is probably enough.
nand watch <off> <size> - check an area for bitflips
nand watch.part <part> - check a partition for bitflips
nand watch.chip - check the whole device for bitflips
The output may be a bit verbose and could look like:
=> nand watch.chip
device 0 whole chip
size adjusted to 0xff60000 (5 bad blocks)
NAND watch for bitflips in area 0x0-0xff60000:
Page 0 (0x00000000) -> error -74
Page 1 (0x00000800) -> error -74
Page 2 (0x00001000) -> error -74
Page 3 (0x00001800) -> error -74
Page 4 (0x00002000) -> error -74
Page 5 (0x00002800) -> error -74
Page 6 (0x00003000) -> error -74
Page 7 (0x00003800) -> error -74
Page 8 (0x00004000) -> error -74
Page 9 (0x00004800) -> error -74
Page 10 (0x00005000) -> error -74
Page 11 (0x00005800) -> error -74
Page 12 (0x00006000) -> error -74
Page 13 (0x00006800) -> error -74
Page 14 (0x00007000) -> error -74
Page 15 (0x00007800) -> error -74
Page 16 (0x00008000) -> error -74
Page 17 (0x00008800) -> error -74
Page 18 (0x00009000) -> error -74
Page 19 (0x00009800) -> error -74
Page 20 (0x0000a000) -> error -74
Page 21 (0x0000a800) -> error -74
Page 22 (0x0000b000) -> error -74
Page 23 (0x0000b800) -> error -74
Page 1110 (0x0022b000) -> up to 1 bf/chunk
Page 1122 (0x00231000) -> up to 1 bf/chunk
Page 1132 (0x00236000) -> up to 1 bf/chunk
Page 1362 (0x002a9000) -> up to 1 bf/chunk
Page 4990 (0x009bf000) -> up to 1 bf/chunk
Page 5728 (0x00b30000) -> up to 1 bf/chunk
Page 7116 (0x00de6000) -> up to 1 bf/chunk
Page 7160 (0x00dfc000) -> up to 1 bf/chunk
Page 7494 (0x00ea3000) -> up to 1 bf/chunk
Page 10842 (0x0152d000) -> up to 1 bf/chunk
Page 11614 (0x016af000) -> up to 1 bf/chunk
Page 11970 (0x01761000) -> up to 1 bf/chunk
Page 12536 (0x0187c000) -> up to 1 bf/chunk
Page 12687 (0x018c7800) -> up to 1 bf/chunk
Page 14298 (0x01bed000) -> up to 1 bf/chunk
Page 18268 (0x023ae000) -> up to 1 bf/chunk
Page 18760 (0x024a4000) -> up to 1 bf/chunk
Page 21440 (0x029e0000) -> up to 1 bf/chunk
Page 22336 (0x02ba0000) -> up to 1 bf/chunk
Page 22592 (0x02c20000) -> up to 1 bf/chunk
Page 23872 (0x02ea0000) -> up to 1 bf/chunk
Page 27584 (0x035e0000) -> up to 1 bf/chunk
Page 35008 (0x04460000) -> up to 1 bf/chunk
Page 37184 (0x048a0000) -> up to 1 bf/chunk
Page 41728 (0x05180000) -> up to 1 bf/chunk
Page 42176 (0x05260000) -> up to 1 bf/chunk
Page 43200 (0x05460000) -> up to 1 bf/chunk
Page 43328 (0x054a0000) -> up to 1 bf/chunk
Page 45376 (0x058a0000) -> up to 1 bf/chunk
Page 47040 (0x05be0000) -> up to 1 bf/chunk
Page 47552 (0x05ce0000) -> up to 1 bf/chunk
Page 49344 (0x06060000) -> up to 1 bf/chunk
Page 49856 (0x06160000) -> up to 1 bf/chunk
Page 62784 (0x07aa0000) -> up to 1 bf/chunk
Page 65153 (0x07f40800) -> up to 1 bf/chunk
Page 65228 (0x07f66000) -> up to 1 bf/chunk
Page 65382 (0x07fb3000) -> up to 1 bf/chunk
Page 98624 (0x0c0a0000) -> up to 1 bf/chunk
Page 101952 (0x0c720000) -> up to 1 bf/chunk
Page 107584 (0x0d220000) -> up to 1 bf/chunk
Page 118208 (0x0e6e0000) -> up to 1 bf/chunk
Page 126656 (0x0f760000) -> up to 1 bf/chunk
Page 127680 (0x0f960000) -> up to 1 bf/chunk
Page 129920 (0x0fdc0000) -> up to 1 bf/chunk
Maximum number of bitflips: 1
Pages with bitflips: 44/130752
It is also possible to reduce the output with the .quiet suffix in order
to just show the summary.
=> nand watch.chip
device 0 whole chip
size adjusted to 0xff60000 (5 bad blocks)
NAND watch for bitflips in area 0x0-0xff60000:
Maximum number of bitflips: 1
Pages with bitflips: 44/130752
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
The condition 'ret' is always true as it is never set to other than
-EIO.
Remove 'ret' and the condition for copy.
Signed-off-by: Marcus Folkesson <marcus.folkesson@gmail.com>
Reviewed-by: Michael Trimarchi <micheal@amarulasolutions.com>
Previously, all LMB marked with LMB_NOMAP (above and below ram_top)
are considered as invalid entry in TLB.
Since commit 1a48b0be93d4 ("lmb: prohibit allocations above ram_top
even from same bank") all LMB located above ram_top are now marked
LMB_NOOVERWRITE and no more LMB_MAP.
This area above ram_top is reserved for OPTEE and must not be cacheable,
otherwise this leads to a Panic on some boards (Issue on STM32MP135F-DK).
Restore previous behavior by marking invalid entry all TLB above ram_top.
Fixes: 1a48b0be93d4 ("lmb: prohibit allocations above ram_top even from same bank")
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
cc: Sughosh Ganu <sughosh.ganu@linaro.org>
Acked-by: Sughosh Ganu <sughosh.ganu@linaro.org>
I have an original rpi installed now, loaded with OS Lite (32-bit)
Add an entry for it so that it can be used for testing.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
This patch was written before the XPL change-over. Update the Makefile
condition to the new way.
Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: ae3b5928d61 ("x86: coreboot: Allow building an expo for...")
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
The logic in get_details() retrieves the default source directory from
the Labgrid settings. This is convenient for interactive use, since it
allows pytests to be run from any directory and still find the source
tree.
However, it is not actually correct.
Gitlab sets the current directory to the source tree and expects that to
be used. At present it is ignored. The result is that Gitlab builds
whatever happens to be in the default source directory, ignoring the
tree it is supposed to be building.
Fix this by using the directory of the source tree, always. This is
obtained by looking at the grandparent of the conftest.py file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Tom Rini <trini@konsulko.com>
Fixes: bf89a8f1fc2 ("test: Introduce the concept of a role")
Tested-by: Tom Rini <trini@konsulko.com>
In case DM drivers probe earlier than board clock setup is done
init of basic clocks should be done in CAR driver probe as well.
Add it to avoid possible clock related problems.
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Return PLL id into struct clk if PLL is parsed from device
tree instead of throwing an error. Allow requesting PLL
clock rate via get_rate op.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
The srktool option -c does not allow spaces between certificate
filenames. Only commas (',') should separate the filenames. If spaces
are incorrectly included, srktool will not display an error or warning
message but will only process the first certificate in the list.
So adapt documentation accordingly.
Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com>
On 64bit systems the timer value might be truncated to a 32bit value
causing malfunctions. For example on ARM the timer might start from 0
again only after a cold reset. The 32bit overflow occurs after a bit
more than 49 days (1000 Hz counter) so booting after that time may lead
to a surprise because the board might become stuck requiring a cold
reset.
Signed-off-by: Ronald Wahl <ronald.wahl@legrand.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
include display_options.h to address build warning:
lib/smbios.c: In function ‘smbios_update_version’:
lib/smbios.c:305:9: warning: implicit declaration of function ‘print_buffer’
[-Wimplicit-function-declaration]
print_buffer((ulong)ptr, ptr, 1, old_len + 1, 0);
^~~~~~~~~~~~
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Fix spelling mistake in the board init files of j721e and j721s2.
s/WKUP_DEVSTAT_MCU_OMLY_MASK/WKUP_DEVSTAT_MCU_ONLY_MASK
Signed-off-by: Prasanth Babu Mantena <p-mantena@ti.com>
In the x86emuOp_jump_call_near_IMM() function the target address is
printed incorrectly when jumping backwards. For example instead of
"jmp 0xe8bc" the string "jmp ffffe8bc" is printed. That's because
of the following macro:
DECODE_PRINTF2("%04x\n", ip);
while it should be
DECODE_PRINTF2("%04x\n", (u16)ip);
Signed-off-by: Yuri Zaporozhets <yuriz@qrv-systems.net>
In the x86emuOp_call_near_IMM() function the address of CALL is
printed incorrectly when jumping backwards. For example, the correct
disassemble of the bytes below would be:
0000E8DE E8DBFF call 0xe8bc
(verified by ndisasm). But instead the address is printed as "ffffe8bc".
That's because of the following macro:
DECODE_PRINTF2("%04x\n", ip);
while it should be
DECODE_PRINTF2("%04x\n", (u16)ip);
Signed-off-by: Yuri Zaporozhets <yuriz@qrv-systems.net>
When DEBUG_DECODE_F is enabled in bios_emulator, the printing of
SET{O,NO,B,NB,Z,NZ,BE,NBE,S,NS,P,TP,L,NL,LE,NLE} instructions
is not followed by newline and is, therefore, immediately followed
by the printed address of a new instruction. This garbles the output
and makes it very difficult to read.
This patch adds missing DECODE_PRINTF("\n") calls to print newlines.
Signed-off-by: Yuri Zaporozhets <yuriz@qrv-systems.net>
When DEBUG_DECODE_F is enabled in bios_emulator, the printing of BSF
instructions is garbled because the '\n' symbol is used instead of
the correct '\t'. Fix that.
Signed-off-by: Yuri Zaporozhets <yuriz@qrv-systems.net>
Currently if a gigabit-capable PHY is connected to FEC via RMII or MII, it
will advertise 1000FULL and 1000HALF to a link partner.
Different problems may arise here:
- usually with (R)MII between MAC and PHY the PHY's connection to magnetics
would have only 2 pairs routed as well, otherwise a PHY can negotiate 1000
speed and there will be no traffic possible;
- but even if there is no way to negotiate 1000 speed in HW (only 2 signal
pairs routed), it may take a lot of time for PHY to figure this out; in
case of AD1300 it takes 17-20 seconds, which is waay longer than default
4s PHY_ANEG_TIMEOUT.
Use phy_set_supported() in such cases to disable gigabit advertised
options.
Signed-off-by: Alexander Sverdlin <alexander.sverdlin@siemens.com>
Set correct CPU and GPU frequencies for the industrial i.MX8 SoC
variant.
Ensure that the CPU and GPU frequencies are properly configured for the
industrial variant of the SoC. According to the "i.MX 8QuadMax
Industrial Applications Processors" datasheet, the frequency limits for
this variant are as follows:
- Cortex-A72: 1.296 GHz
- Cortex-A53: 1.104 GHz
- GPU core: 625 MHz
- GPU shader: 625 MHz
The CPU clock is enforced by the System Controller Firmware (SCFW), but
the cpufreq driver is unaware of this enforcement. By removing
unsupported frequencies from the operating points, we ensure that the
cpufreq driver aligns correctly with the SCFW's settings.
The GPU frequency, on the other hand, is not enforced by the SCFW. As a
result, the GPU could potentially be overclocked. To prevent this, we
set the correct clock frequency and update the operating points
accordingly, ensuring compliance with the datasheet specifications.
Signed-off-by: Stefan Eichenberger <stefan.eichenberger@toradex.com>
Simplify module version handling by removing the special case for the
Apalis iMX8QM.
The Apalis iMX8QM has been treated as a special case in module version
handling, but was always the default. By removing this special handling,
the code is simplified and easier to maintain.
We will not print the message "Unknown Apalis iMX8 module" anymore.
However, we still handle this because if the config block is missing we
show "MISSING TORADEX CONFIG BLOCK" and if the serial number is unknown
we show "Model: Toradex 0000 UNKNOWN MODULE V1.1A". Therefore, it is
still possible to detect such issues.
Signed-off-by: Stefan Eichenberger <stefan.eichenberger@toradex.com>
Add new PIDs for the Apalis iMX8 modules featuring the industrial
variant of the SoC, which supports a maximum CPU frequency of 1300 MHz.
Signed-off-by: Stefan Eichenberger <stefan.eichenberger@toradex.com>
This preparation step ensures that the first column has sufficient space
to handle longer defines. This is necessary for the new Apalis iMX8
defines.
Signed-off-by: Stefan Eichenberger <stefan.eichenberger@toradex.com>
Apalis iMX8DXP 1GB is currently set to enable when compiling for Apalis
iMX8. This is a mistake the Apalis iMX8DXP 1GB was never released and is
not compatible to the Apalis iMX8 series.
Signed-off-by: Stefan Eichenberger <stefan.eichenberger@toradex.com>
