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3 Commits

Author SHA1 Message Date
Tom Rini
b8d59ba049 board: freescale: Remove <common.h> and add needed includes 
Remove <common.h> from this board vendor directory and when needed
add missing include files directly.

Acked-by: Jason Liu <jason.hui.liu@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
 2024-05-07 08:00:24 -06:00
Bai Ping
7b14cc991b imx8mq: Update the ddrc QoS setting for B1 chip 
Update the ddrc Qos setting for B1 to align with B0's setting.
Correct the initial clock for dram_pll. This setting will be
overwrite before ddr phy training. Although there is no impact
on the dram init, we still need to correct it to eliminate
confusion.

Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Tested-by: Robby Cai <robby.cai@nxp.com>
 2019-10-08 16:36:37 +02:00
Peng Fan
86ac7a9a5d imx: add i.MX8MQ EVK support 
Add i.MX8MQ EVK support. SPL will initialize ddr and load ddr phy
firmware. Then loading FIT image, ATF to OCRAM, U-Boot and DTB to
DRAM.

The boot log with Arm trusted firmware console enabled:
"
U-Boot SPL 2018.11-00142-g9ae14e7274 (Nov 20 2018 - 18:13:16 +0800)
PMIC:  PFUZE100 ID=0x10
Normal Boot
Trying to boot from MMC2
NOTICE:  Configureing TZASC380
NOTICE:  BL31: v1.5(release):p9.0.0_1.0.0-beta-20180928-8-ge09c4b62-dirty
NOTICE:  BL31: Built : 09:28:54, Nov  8 2018
lpddr4 swffc start
NOTICE:  sip svc init

U-Boot 2018.11-00142-g9ae14e7274 (Nov 20 2018 - 18:13:16 +0800)

CPU:   Freescale i.MX8MQ rev2.0 at 1000 MHz
Reset cause: POR
Model: Freescale i.MX8MQ EVK
DRAM:  3 GiB
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
In:    serial
Out:   serial
Err:   serial
Net:
Warning: ethernet@30be0000 using MAC address from ROM
eth0: ethernet@30be0000
Hit any key to stop autoboot:  0
"

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
 2019-01-01 14:12:18 +01:00