Move to using OF_UPSTREAM config and thus using the devicetree
subtree and remove unused device tree files.
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
Acked-by: Sumit Garg <sumit.garg@linaro.org>
The Texas Instruments Foundational Security (TIFS) firmware must match
the security level configured on the SoC. To boot Security Enforced (SE)
variants of the AM62Px, add another tiboot3 build which packages the
Security Enforced (SE) firmware variant for AM62Px SoCs.
Signed-off-by: Bryan Brattlof <bb@ti.com>
OSPI Boot requires overrides specific to R5 and also
to use DMA in R5 SPL stage the DM_TIFS needs to be used.
Add the corresponding overrides for R5 SPL stage.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Prasanth Babu Mantena <p-mantena@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Andrew Goodbody <andrew.goodbody@linaro.org> says:
Picking up a series from Dan Carpenter and applying requested
changes for v2.
I had previously set CONFIG_64BIT for arm64. This patchset does the
same thing for sandbox and x86_64. (Mips and riscv were already
doing it). This CONFIG option is used in the Makefile to determine
if it's a 32 or 64 bit system for the CHECKER.
Makefile
1052 # the checker needs the correct machine size
1053 CHECKFLAGS += $(if $(CONFIG_64BIT),-m64,-m32)
Link: https://lore.kernel.org/r/20241216180736.1933807-1-andrew.goodbody@linaro.org
Select CONFIG_64BIT so that we pass the -m64 option (instead of -m32) to
static analysis tools.
Introduce CONFIG_SPL_64BIT and select it for architectures other than
x86 with 64 bit builds. Do not select it for x86 builds as x86 uses
a 32 bit SPL.
Ensure that when limits are set they use CONFIG_64BIT for U-Boot
proper and CONFIG_SPL_64BIT for SPL. This is to allow for the 32 bit
SPL build used by x86.
Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Describe APMU controller as a remoteproc device capable of starting
the Cortex-R52 cores in Renesas R8A779G0 V4H SoC DT. The APMU IP is
in fact a power management unit capable of additional operations, but
those are not used by U-Boot so far.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Add R-Car Gen4 APMU controller remoteproc driver capable of starting
the Cortex-R52 cores in Renesas R8A779G0 V4H/V4M SoC. The APMU IP is
in fact a power management unit capable of additional operations, but
those are not used by U-Boot so far.
This requires slight adjustment to the SPL entry point code, as that
is being executed on the Cortex-R52 #0 and the Cortex-R52 #0 enters an
endless loop once it starts the rest of the SPL on Cortex-A76 core.
The endless loop now checks for content of APMU CRBARP registers and
tests whether valid VLD_BARP and BAREN_VALID bits are set, if so, the
Cortex-R52 core exits the endless loop and jumps to address started
in CRBARP[31:18] register in ARM mode, which is a trampoline code to
jump to the final entry point.
The trampoline code is in place to avoid limitation of CRBARP[31:18]
address field, which limits the core start address to memory addresses
aligned to 0x40000 or 256 kiB . The trampoline is placed at 0x40000
aligned address and jumps to the final entry point, which can be at
an address with arbitrary alignment at instruction granularity.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This DTC_FLAGS assignment is no longer necessary as all R-Car Gen2/Gen3/Gen4
platforms have been converted to OF_UPSTREAM and matching DTC_FLAGS assignment
is present in dts/upstream/src/arm64/Makefile . Drop the remnant.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Align R-Car Gen2/Gen3/Gen4 configuration header file to look
basically the same way across these three SoC generations.
There are subtle difference between the remaining bits in
those files across SoC generations, but the common bits are
now aligned. There is not much left in those headers either,
most of the configuration is now converted to Kconfig.
Specifically for R-Car Gen3, GIC registers have been moved
to architecture specific header file rcar-gen3-base.h , the
rest of the changes here are comment changes and indentation
changes.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Add support for building U-Boot SPL for Renesas R-Car Gen4 R8A779G0 V4H SoC.
The SPL initializes the DBSC5 DRAM controller, RT-VRAM and loads and starts
U-Boot proper on the Cortex-A76 core.
The SoC BootROM can not boot the CA76 core directly, instead the SPL starts
on the CR52 core which immediately brings up the CA76 core, which in turn
starts executing the actual SPL. This is achieved by placing a tiny bit of
precompiled Aarch32 code at the very beginning of the SPL. The code consists
of some 32 instructions, uses APMU to configure CA76 start address to offset
0x80 Bytes from start of the SPL, and uses APMU to start the CA76 core. The
code parts the CR52 core in an endless loop once the CA76 core got started.
The 32 instructions are completely arbitrary number, so is the offset 0x80
Bytes from start of SPL, because 0x80 = 128 decimal and 128 / 4 bytes per
instruction is 32 instructions. The 32 instructions turned out to be enough
to started the CA76 and 0x80 is nicely aligned.
Once the SPL completes hardware initialization, the SPL loads U-Boot proper.
The u-boot.itb proper fitImage contains 64bit build on u-boot-nodtb.bin and
a DT for R8A779G0 V4H White Hawk board and is generated by binman. The
u-boot.itb is loaded from SPI NOR offset 0x80000.
In order to install this setup on an existing R8A779G0 V4H White Hawk board,
build using r8a779g0_whitehawk_defconfig, generate SPI NOR image flash.bin
and write flash.bin to SPI NOR offset 0x0 . Finally, configure board MD pin
switches according to the R8A779G0 V4H White Hawk board documentation for
40 MHz SPI NOR boot using DMA and restart the board.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Make the R-Car V3U stub PSCI implementation available on 64bit R-Car SoCs.
This implementation is useful during early board bring up, where it can
supplant missing fully-featured PSCI implementation. Note that this PSCI
implementation is very basic and offers only SoC reset functionality. It
is unable to enable or disable secondary CPU cores nor does it offer any
suspend/resume functionality.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Describe DBSC5 DRAM controller and RT-VRAM configuration interface
as two new DT nodes in R-Car Gen4 R8A779G0 U-Boot DT extras file.
This node is used by the U-Boot SPL for R8A779G0 SoC, where the
DBSC5 and RT-VRAM drivers bind to these nodes and bring up the
DRAM controller and RT-VRAM settings respectively, so U-Boot
proper can be loaded into DRAM and started on Cortex A76 core.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
The GW7905 was renamed to GW7500 before release. Change the various
names in the dt files and references.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Drop global ddrphy_trained_csr which maybe different with per board
ddrphy_trained_csr. DDR TOOL generates ddrphy_trained_csr for each
board, using the global ddrphy_trained_csr has risk that values may
be not up to date.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
commit e27bddff4b97 ("imx8m: Restrict usable memory to space below 4G boundary")
tried to adjust the usable memory limits on a 4GB boundary.
ram_top is described as 'top address of RAM used by U-Boot' and we want
to preserve that. This is defined as a phys_addr_t and unfortunately
its size differs across architectures. This has lead us to a weird
state where 32bit boards define it 'SZ_4GB - 1' and 64bit boards as
'SZ_4GB' unless it was otherwise defined.
With some recent LMB changes and specifically
commit 1a48b0be93d4 ("lmb: prohibit allocations above ram_top even from same bank")
the board fails to boot properly although the commit above is correct
since it's making sure that no memory above ram_top is usable -- but
added to our memory map so EFI can hand it over to the booted OS.
The reason for that is that during the LMB init we add all usable memory
in lmb_add_memory(). In that function any memory above ram_top gets added
as 'reserved' for LMB. With the current values tha's set to 0xFFFF_FFFF
for this board. Later LMB is trying to protect the memory area U-Boot lives
in with lmb_reserve_common(). The latter fails though since it tries to
add U-Boot top (which is 0xFFFF_FFFF as well) to U-Boot 'bottom'. This call
will fail since 1 byte of that memory range is already marked as 'reserved'.
Since we are close to the release, LMB seems to assume that the address
is rounded up and is the 'next address' and so does parsing and adding
memory ranges from DT files, bump the ram_top of the board by 1byte.
In the long run we should change all of the above and have 32b and 64b
platforms define ram_top identically.
Add a Fixes tag although the commit is correct, so people can figure out
the broken scenarios in the future.
Suggested-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Fixes: commit 1a48b0be93d4 ("lmb: prohibit allocations above ram_top even from same bank")
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reported-by: João Paulo Gonçalves <jpaulo.silvagoncalves@gmail.com>
Closes: https://lore.kernel.org/all/20241216114231.qpfwug3zfqkxn3d5@joaog-nb.corp.toradex.com/
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Fixes: 74f88b72219e ("ARM: imx: imx8m: Fix board_get_usable_ram_top()")
This returns a devicetree and updates a parameter with an error code.
Swap it, since this fits better with the way U-Boot normally works. It
also (more easily) allows leaving the existing pointer unchanged.
No yaks were harmed in this change, but there is a very small code-size
reduction.
For sifive, the OF_BOARD option must be set for the function to be
called, so there is no point in checking it again. Also OF_SEPARATE is
defined always.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
[trini: Update total_compute]
Signed-off-by: Tom Rini <trini@konsulko.com>
The root oscillators reference used to be in rcc node since
3d15245502c4 ("ARM: dts: stm32mp1: explicit clock reference needed by RCC clock driver")
however this is not part of upstream stm32mp151.dtsi . The
RCC driver does need this reference, reinstate it locally.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
The root oscillators reference used to be in rcc node since
3d15245502c4 ("ARM: dts: stm32mp1: explicit clock reference needed by RCC clock driver")
however this is not part of upstream stm32mp151.dtsi . The
RCC driver does need this reference, reinstate it globally.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Tested-by: Patrice Chotard <patrice.chotard@foss.st.com>
Previously, all LMB marked with LMB_NOMAP (above and below ram_top)
are considered as invalid entry in TLB.
Since commit 1a48b0be93d4 ("lmb: prohibit allocations above ram_top
even from same bank") all LMB located above ram_top are now marked
LMB_NOOVERWRITE and no more LMB_MAP.
This area above ram_top is reserved for OPTEE and must not be cacheable,
otherwise this leads to a Panic on some boards (Issue on STM32MP135F-DK).
Restore previous behavior by marking invalid entry all TLB above ram_top.
Fixes: 1a48b0be93d4 ("lmb: prohibit allocations above ram_top even from same bank")
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
cc: Sughosh Ganu <sughosh.ganu@linaro.org>
Acked-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Fix spelling mistake in the board init files of j721e and j721s2.
s/WKUP_DEVSTAT_MCU_OMLY_MASK/WKUP_DEVSTAT_MCU_ONLY_MASK
Signed-off-by: Prasanth Babu Mantena <p-mantena@ti.com>
Set correct CPU and GPU frequencies for the industrial i.MX8 SoC
variant.
Ensure that the CPU and GPU frequencies are properly configured for the
industrial variant of the SoC. According to the "i.MX 8QuadMax
Industrial Applications Processors" datasheet, the frequency limits for
this variant are as follows:
- Cortex-A72: 1.296 GHz
- Cortex-A53: 1.104 GHz
- GPU core: 625 MHz
- GPU shader: 625 MHz
The CPU clock is enforced by the System Controller Firmware (SCFW), but
the cpufreq driver is unaware of this enforcement. By removing
unsupported frequencies from the operating points, we ensure that the
cpufreq driver aligns correctly with the SCFW's settings.
The GPU frequency, on the other hand, is not enforced by the SCFW. As a
result, the GPU could potentially be overclocked. To prevent this, we
set the correct clock frequency and update the operating points
accordingly, ensuring compliance with the datasheet specifications.
Signed-off-by: Stefan Eichenberger <stefan.eichenberger@toradex.com>
Since commit 61ff13283c3b ("board: sl28: move to OF_UPSTREAM") USB0 is
broken because the former u-boot soc dtsi was setting dr_mode to "host"
but the linux device tree isn't. That is because linux fully supports
OTG but u-boot doesn't. Therefore, u-boot only ever enabled host mode
and never OTG mode. Add it to our board "-u-boot.dtsi" to fix it.
Fixes: 61ff13283c3b ("board: sl28: move to OF_UPSTREAM")
Reported-by: Heiko Thiery <heiko.thiery@gmail.com>
Signed-off-by: Michael Walle <mwalle@kernel.org>
Tested-by: Heiko Thiery <heiko.thiery@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Anurag Dutta <a-dutta@ti.com> says:
Hi All,
In u-boot, hbmc is broken and has been removed from j7200
configs. This series re-enables the hbmc driver and introduces a series
of hyperflash boot fixes. At present, in u-boot, the parent device (fss)
gets registered as a syscon device. This is done because the MMIO
mux driver in u-boot did not support the mux functionality when the
parent device is not a syscon. In this series, we make relevant changes
in the hbmc driver as well as dts' so that we can use the reg-mux driver for
selecting the appropriate state of the mux.
Test logs:
1) j721e-idk-gw hyperflash boot test: https://gist.github.com/anuragdutta731/50aae6fec707a3ffad6d985de6757fe4
2) j7200-evm hyperflash boot test: https://gist.github.com/anuragdutta731/c3a4d60f8bfd9c425d6c44b36eb7322b
Link: https://lore.kernel.org/r/20241129113136.383277-1-a-dutta@ti.com
Add 32-bit address overrides for Hyper Bus Memory Controller
for Hyperflash to be functional in R5 SPL.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Anurag Dutta <a-dutta@ti.com>
Add 32-bit address overrides for Hyper Bus Memory Controller
for Hyperflash to be functional in R5 SPL.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Anurag Dutta <a-dutta@ti.com>
Garrett Giordano <ggiordano@phytec.com> says:
This patch set adds the phyCORE AM62Ax board support and documenation to
u-boot.
The phyCORE-AM62Ax is a SoM (System on Module) featuring TI's AM62Ax SoC. It can
be used in combination with different carrier boards. This module can come
with different sizes and models for DDR, eMMC, SPI NOR Flash and various SoCs
from the AM62x family.
A development Kit, called phyBOARD-Lyra is used as a carrier board reference
design around the AM62x SoM.
This series depends on the following two patches:
- [PATCH v2] arm: mach-k3: am62a7: Provide a way to obtain boot device for non SPL
https://lists.denx.de/pipermail/u-boot/2024-October/570156.html
- [PATCH] board: phytec: common: Introduce CONFIG_PHYTEC_K3_DDR_PATCH
https://lists.denx.de/pipermail/u-boot/2024-November/571543.html
Link: https://lore.kernel.org/r/20241118231606.3161665-1-ggiordano@phytec.com
[trini: Fix warning in board/phytec/common/k3/board.c when
CONFIG_EFI_HAVE_CAPSULE_SUPPORT is not enabled]
Signed-off-by: Tom Rini <trini@konsulko.com>
Introduce get_boot_device() to obtain the booting device. Make it also
available for non SPL builds so u-boot can also know the device it
is booting from.
Signed-off-by: Garrett Giordano <ggiordano@phytec.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>
Wadim Egorov <w.egorov@phytec.de> says:
This implements capsule updates for all our K3 SoMs for
eMMC, OSPI NOR and uSD cards.
We can use capsule updates to update the bootloader on all our
supported flash devices.
Link: https://lore.kernel.org/r/20241127121736.1525948-1-w.egorov@phytec.de
Enable Quality of Service (QoS) blocks for Display SubSystem (DSS), by
servicing the DSS - DDR traffic from the Real-Time (RT) queue. This is
done by setting the DSS DMA orderID to greater than 7.
DDR intensive software applications can overwhelm the DSS's access to
the DDR because of their higher frequency DDR accesses. This can cause
flickering in display with certain applications running parallely if
the DSS traffic is being serviced through non-RT queue.
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
Enable Quality of Service (QoS) blocks for Display SubSystem (DSS), by
servicing the DSS - DDR traffic from the Real-Time (RT) queue. This is
done by setting the DSS DMA orderID to greater than 7.
The C7x and VPAC can overwhelm the DSS's access to the DDR because of
their higher frequency DDR accesses. This can cause flickering in
display with certain edgeAI models running parallely if the DSS traffic
is being serviced through non-RT queue.
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
The correct spelling is R-Car, including the dash, update the usage.
Kconfig strings and comment changes only, no functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
The correct spelling is R-Car, including the dash, update the usage.
Comment change only, no functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
The U-Boot is currently not capable of handling ethernet-phy-ieee802.3-c45
PHYs correctly, and also does not handle MDIO bus wide reset-gpios property.
Until proper C45 PHY support lands in U-Boot, disable AVB1/AVB2 interfaces.
This only disables the two MACs with 88Q2110/88Q2112 100/1000BASE-T1 PHYs
on ethenet sub-board, the main board AVB0 ethernet is unaffected.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
The new i.MX8M Plus DHCOM rev.200 is populated with M24C32-D EEPROM
that contains an additional write-lockable page called ID page. Add
aliases eeprom0wl and eeprom1wl for the access to the EEPROM ID
page node.
Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Reviewed-by: Marek Vasut <marex@denx.de>
