random-mirrors/smaeul-u-boot
1
0
Fork 0
mirror of https://github.com/smaeul/u-boot.git synced 2025-10-17 14:18:14 +01:00
Code Issues Packages Projects Releases Wiki Activity
53,712 Commits 30 Branches 324 Tags
Commit Graph

2 Commits

Author SHA1 Message Date
Bin Meng
b5369c5813 riscv: Make start.S available for all targets 
Currently start.S is inside arch/riscv/cpu/ax25/, but it can be
common for all RISC-V targets.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
 2018-10-03 17:48:14 +08:00
Bin Meng
2fab2e9c88 riscv: Add a helper routine to print CPU information 
This adds a helper routine to print CPU information. Currently
it prints all the instruction set extensions that the processor
core supports.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
 2018-10-03 17:47:55 +08:00