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3 Commits

Author SHA1 Message Date
Simon Glass
7ea01d1808 x86: Add FDT SPI node for link 
Add a memory-mapped 8GB SPI chip.

Signed-off-by: Simon Glass <sjg@chromium.org>
 2013-03-19 08:45:37 -07:00
Simon Glass
26f7621d99 x86: Adjust link device tree include file 
This is currently set to coreboot.dtsi, but we cannot support this on
old device tree compilers (dtc <= 1.3), so adjust to use ARCH_CPU_DTS
to let the Makefile preprocessor sort this out.

Signed-off-by: Simon Glass <sjg@chromium.org>
 2013-03-04 15:57:51 -08:00
Simon Glass
2712f08898 x86: fdt: Create basic .dtsi file for coreboot 
This contains just the minimum information for a coreboot-based board.

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
 2012-12-06 14:30:42 -08:00