53 Commits

Author	SHA1	Message	Date
Simon Glass	6e5b12b614	x86: ivybridge: Enable PCI in early init ... Enable PCI so we can access devices that need to be set up before relocation. Signed-off-by: Simon Glass <sjg@chromium.org>	2014-11-21 07:34:12 +01:00
Simon Glass	70a09c6c3d	x86: chromebook_link: Implement CAR support (cache as RAM) ... Add support for CAR so that we have memory to use prior to DRAM init. On link there is a total of 128KB of CAR available, although some is used for the memory reference code. Signed-off-by: Simon Glass <sjg@chromium.org>	2014-11-21 07:34:11 +01:00
Simon Glass	8ef07571a0	x86: Add chromebook_link board ... This board is a 'bare' version of the existing 'link 'board. It does not require coreboot to run, but is intended to start directly from the reset vector. This initial commit has place holders for a wide range of features. These will be added in follow-on patches and series. So far it cannot be booted as there is no ROM image produced, but it does build without errors. Signed-off-by: Simon Glass <sjg@chromium.org>	2014-11-21 07:34:11 +01:00