As done for infracfg, also add support for parent mux from different
source for topckgen. This is needed as upstream linux doesn't use 1/1
factor and use directly the APMIXED clocks.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
There is a current limitation where parents for a mux can be all declared
as they are from a common source. This is not true as there are some MUX
that can have parent from both infracfg or from topckgen.
To handle this, implement a new flag for the mux, CLK_PARENT_MIXED, and
a new entry for the mux parent_flags.
To use this, CLK_PARENT_MIXED must be used and parent_flags will be used
instead of the parent variable.
Entry in parent_flags are just a struct of ID and flags where it will be
defined where that parent comes from with the usage of
CLK_PARENT_INFRASYS or CLK_PARENT_TOPCKGEN.
This permits to have MUX with parents from infracfg or topckgen.
Notice that with CLK_PARENT_MIXED applied the CLK_BYPASS_XTAL is
ignored.
With CLK_PARENT_MIXED declare CLK_PARENT_XTAL for the relevant parent
instead.
Also alias for the CLK_PARENT macro are provided to better clear their
usage. CLK_PARENT_MIXED require these alias that describe the clk type
to be defined in the clk_tree flags to prevent clk ID clash from
different subsystem that may have equal clk ID.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Add support to clk_gate ops to reference the clk ID at an offset by
using the just introduced gates_offs value from the unified muxes +
gates implementation.
Gate clock that doesn't have gates_offs set won't be affected as the
offset will simply be 0 and won't be offset of any value.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Add support for gates in clk_tree for infrasys ops.
Infracfg clks can have a sum of gates and muxes, and current solution
handle this by duplicating the driver and split clks for mux and clks
for gates. Upstream linux kernel handle this differently and doesn't
have this distinction.
To be closer to the upstream kernel clock definition, implement
additional logic to have gates defined in the clk_tree and implement
variant for the infrasys ops to handle gates defined in the tree.
Similar to how it's done with factor and mux, we introduce gates_offs.
Upstream kernel follow the similar logic with all the ID defined as
FDIVS, MUXES and finally GATES.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
We currently return 0 if XTAL rate is requested in get_mux_rate. This
deviates from what is done in get_factor_rate and is totally wrong as it
can cause unwanted results (division by 0 crash)
For infrasys that makes use of CLK_XTAL, assume xtal_rate to be defined
in clk_tree and return the rate when BYPASS_XTAL is not enabled with
clk ID 0 index parents.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
There is currently a massive bug that makes any gate clk that have
CLK_XTAL as parent to return the wrong clock.
Following the code, with CLK_XTAL defined as TOPCKGEN parent, the
topckgen get_rate is called. The clk ID (0) is parsed and only in some
corner case (scenario where fixed clock are not defined) the correct
XTAL rate will be returned as get_factor or get_mux is called (that have
correct handling for CLK_XTAL). With fixed clock defined, the rate that
will be returned will always be the FIRST ELEMENT of the fixed clock
table instead of the hardcoded XTAL rate.
To handle this, add additional logic and if the flag is set to
PARENT_XTAL for the gate, return the XTAL rate directly.
We assume the clk_tree to have xtal_rate defined with clk gates that
have XTAL as parents.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Bevor this commit, only clause 22 access was possible. After this commit,
clause 45 direct access will available as well.
Note that there is a slight change of behavior: Before this commit, the
C45E bit was set to whatever value was left in the register from the
previous access. After this commit, we adopt the common practice of
discerning C45 from C22 using the devad argument.
Signed-off-by: Philip Oberfichtner <pro@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
- fix dropping characters when pasting commands over the UART
- enable background syncing by default for boards using VIDEO
- make sandbox video more responsive
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Merge tag 'video-20240731' of https://source.denx.de/u-boot/custodians/u-boot-video
- improve video sync performance with background syncing (cyclic)
- fix dropping characters when pasting commands over the UART
- enable background syncing by default for boards using VIDEO
- make sandbox video more responsive
Jiaxun Yang <jiaxun.yang@flygoat.com> says:
This is a subset of my previous arm64_be work.
I wish this could be merged first so it would be easier to work
against xtensa and arm64 be support.
So CONFIG_SYS_BIG_ENDIAN is our cross architecture option for
selecting machine endian, while the old CONFIG_CPU_BIG_ENDIAN
is defined by Arc only.
Use it whenever possible to ensure big endian code path is enabled
for all possible big endian machines.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
With sandbox, when U-Boot is waiting for input it syncs the video
display, since presumably the user has finished typing.
Now that cyclic is used for video syncing, we can drop this. Cyclic
will automatically call the video_idle() function when idle.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present U-Boot flushes the cache after every character written to
the display. This makes the command-line slower, to the point that
pasting in long strings can fail.
Add a cyclic function to sync the display every 10ms. Enable this by
default.
Allow much longer times for sandbox, since the SDL display is quite
slow.
Avoid size growth if the feature is disabled by making the new init and
destroy functions dependent on CYCLIC being enabled.
Signed-off-by: Simon Glass <sjg@chromium.org>
Rather than using a static variable, use the video device's private
data to remember when the last video sync was completed. This allows
each display to have its own sync and avoids using static data in SPL.
Signed-off-by: Simon Glass <sjg@chromium.org>
The cyclic subsystem is currently enabled either in all build phases
or none. For tools this should not be enabled, but since lib/shc256.c
and other files include watchdog.h in the host build, we must make
sure that it is not enabled there.
Add an SPL symbol so that there is more control of this.
Add an include into cyclic.h so that tools can include this file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
Reviewed-by: Stefan Roese <sr@denx.de>
The linux kernel has the list_count_nodes() API functions which is
used for counting nodes of a list. This has now been imported in
U-Boot as part of an earlier commit. Use this function and drop the
list_count_items().
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> says:
v2 changes:
* Drop sw_blink_state structure, move its necessary fields to
led_uc_plat structure.
* Add cyclic_info pointer to led_uc_plat structure. This
simplify code a lot.
* Remove cyclic function search logic. Not needed anymore.
* Fix blinking period. It was twice large.
* Other cleanups.
v3 changes:
* Adapt code to recent cyclic function changes
* Move software blinking functions to separate file
* Other small changes
v4 changes:
* Refactoring of led_set_period() function
v5 changes
* Fix compilation if CONFIG_LED_BLINK is not defined
v6 changes:
* Enable LEDST_BLINK state unconditionally.
* Function led_set_period() becomes available when CONFIG_LED_BLINK
is disabled. This makes led code simpler.
* Software blinking requires about 100 bytes of data for a led. It's
not a good idea to allocate so much memory for each supported led.
Change the code to allocate blinking data only for required leds.
The standard property
linux,default-trigger = "pattern";
used to get an effect. No blinking parameters can be set yet.
Signed-off-by: Michael Polyntsov <michael.polyntsov@iopsys.eu>
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Reviewed-by: Simon Glass <sjg@chromium.org>
If hardware (or driver) doesn't support leds blinking, it's
now possible to use software implementation of blinking instead.
This relies on cyclic functions.
Signed-off-by: Michael Polyntsov <michael.polyntsov@iopsys.eu>
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Reviewed-by: Simon Glass <sjg@chromium.org>
Changes:
* enable LEDST_BLINK state unconditionally
* function led_set_period() becomes available when CONFIG_LED_BLINK
is disabled. This makes led code simpler.
* fix cmd/led.c to work properly when LEDST_BLINK present, but
CONFIG_LED_BLINK is disabled
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Reviewed-by: Simon Glass <sjg@chromium.org>
* Qualcomm platforms >~2016 gain support for the RPMh (Resource Power Manager)
peripheral which is used to control most regulators. The RB5 is now able to
power up its USB VBUS regulator via the rpmh regulator driver. Git history
from the original Linux driver is preserved for ease of maintenance.
* IPQ40xx SoCs gain ethernet networking support via the new ESS EDMA driver.
This adds the driver for the ESS EDMA ethernet adapter
found inside of Qualcomm IPQ40xx SoC series.
This driver also integrates the built in modified QCA8337N
switch support as they are tightly integrated.
Co-Developed-by: Gabor Juhos <j4g8y7@gmail.com>
Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
IPQ4019 has more networking related resets that will be required for future
wired networking support, so lets add them.
This syncs the driver with Linux.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
ESS clock is the Ethernet Subsystem clock, so lets add it as its
already configured by SBL1.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Add Kconfig and Makefile entries for this driver now that it can build
for U-Boot.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Refactor initialization to use U-Boot's driver model and API.
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Port over the regulator ops to U-Boot's regulator API. Add back the
pmic5 mode map using U-Boot dm_regulator_mode API and adjust the
pmic5_pldo and pmic5_pldo_lv definitions. No functional changes.
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Initially just include the few regulators needed for the RB5 board.
Others can be added back as-needed.
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
A lot of the features in here are only relevant when running
multi-threaded with interrupts. Drop everything except what we need to
run single-threaded with a single TCS (which is all the rpmh-rsc
framework in U-Boot supports).
Keep rpmh_write_async() for simplicity and make it wrap the regular
rpmh_write().
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Drop unused/unsupported Linux headers and add dm/device.h for U-Boot.
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Minor adjustments to fix building with U-Boot and work correctly as a
synchronous driver without interrupts. RPMh is fast enough that we can
get away with just firing off requests and assuming they complete.
U-Boot behaviour changes are annotated with a "U-Boot:" comment.
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Rework the rpmh-rsc initialization to use U-Boot's driver model and
initialize cmd-db.
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Remove unsupported / unused Linux headers and add those needed for
U-Boot.
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Since U-Boot is single threaded, we can avoid most of the complexity
that comes with handling more than one in-flight TCS. Drop all the rpmh
code associated with multi-threading as we'll instead wait for a
response on each TCS.
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Keep the header pointer in the .data section so we don't initialize it
again after relocation, adjust cmd_db_get_header() to work with the
U-Boot API, and skip validating the header since all cmd-db users are
children of the rpmh-rsc and those children will only probe if cmd-db
initializes successfully.
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Integrate cmd-db into the U-Boot driver model.
This is just a wrapper around an in-memory database, so we just need to
get the address and validate that cmd-db is there.
Since cmd_db_header will be stored in the .data section we can skip
bind if it's already set.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Due to our simpler rpmh-rsc driver and lack of debugfs, we don't need
quite a few cmd-db functions, just drop them.
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Add True Random Number Generator (TRNG) driver for Exynos chips. This
implementation is heavily based on Linux kernel's counterpart [1]. It
also follows upstream dt-bindings [2].
TRNG block is usually a part of SSS (Security Sub System) IP-core on
Exynos chips. Because SSS access on Exynos850 is protected by TZPC
(TrustZone Protection Control), it's not possible to read/write TRNG
registers from U-Boot, as it's running in EL1 mode. Instead, the
corresponding SMC calls should be used to make the secure software
running in EL3 mode access it for us. Those SMC calls are handled by
LDFW (Loadable Firmware), which has to be loaded first. For example, for
E850-96 board it's done in its board_init(), so by the time RNG
capabilities are needed the LDFW should be already loaded and TRNG
should be functional.
[1] drivers/char/hw_random/exynos-trng.c
[2] dts/upstream/Bindings/rng/samsung,exynos5250-trng.yaml
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Add ACLK (operating clock) and PCLK (bus clock) for Security Sub System
(SSS) in Exynos850. Those clocks are needed for RNG enablement.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/21728
- Conversions to DM_I2C and DM_SERIAL.
- Support for I2C3 and PWM1 for the imx6q clock driver.
- Improvements for udoo-neo
- Describe the i.MX93 CPU clocks in the devicetree to fix CPU clock printing
- Fix for SPI and NANC clk-imx8mn clock driver
