3 Commits

Author	SHA1	Message	Date
Zong Li	40c76dfed2	riscv: cache: support cache enable in SPL stage ... The power gating feature of pl2 should be enabled as early as possible, it would be better to put it in SPL stage. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>	2023-12-27 17:28:57 +08:00
Tom Rini	0b9441ae76	riscv: Remove common.h usage ... We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>	2023-10-24 16:34:45 -04:00
Zong Li	213ed175b0	riscv: lib: implement enable_caches for sifive cache ... The enable_caches is a generic hook for architecture-implemented, we define this function to enable composable cache of sifive platforms. In sifive_cache, it invokes the generic cache_enable interface of cache uclass to execute the relative implementation in SiFive ccache driver. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>	2021-09-07 10:34:29 +08:00