Update simple-framebuffer device-tree node by enumerating framebuffer
related information in existing simple-framebuffer node in Linux
device-tree file and enabling it.
In case there is no simple-framebuffer stub detected in Linux kernel
device-tree and video is still active, then update the device-tree to
reserve the framebuffer region for the active splash screen.
This helps preserve the splash screen till the display server takes over
after OS is booted.
Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
CONFIG_VIDEO conditional compilation checks are no longer needed since
FDT_SIMPLEFB Kconfig now depends on VIDEO Kconfig.
Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
The fdt_simplefb.c APIs rely on video-uclass APIs and structures to
fill/update framebuffer information, so compile it only when VIDEO
Kconfig is enabled, as otherwise below warning can be seen if VIDEO
Kconfig is disabled:
"boot/fdt_simplefb.c:96:12: warning: fdt_simplefb_enable_existing_node
defined but not used [-Wunused-function]
96 | static int fdt_simplefb_enable_existing_node(void *blob)"
Reported-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
The VNBYTES() macro has been updated to silence possible warnings
regarding authorized (but unusual) uses of this macro, but the comment
was kept unchanged. A year has passed so let's fix the comment now to
avoid confusions.
Fixes: cc05d352fbc ("video: Add parentheses around VNBYTES() macro")
Suggested-by: Tom Rini <trini@konsulko.com>
Link: https://lore.kernel.org/u-boot/20240906183432.GG3879073@bill-the-cat/
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
In v2024.10, "make envtools" is broken for at least these defconfigs:
am335x_evm_defconfig
rpi_3_defconfig
rpi_4_defconfig
mx7dsabresd_defconfig
wandboard_defconfig
imx8mp_evk_defconfig
The only defconfig we use for which it is not broken is
stm32mp13_defconfig. They all work just fine in v2024.07.
The symptoms are slightly different, but all related to the fact that
some transitively included header uses IS_ENABLED or CONFIG_IS_ENABLED
without linux/kconfig.h having already been included.
A simple git bisect doesn't produce anything sensible, it ends up at
3a9f642ca94 (crypto: nuvoton: npcm_sha: Support SHA 384/512) which
clearly has nothing to do with this. But digging deeper, one
eventually finds 0f92fa45603 ("env: Remove <common.h> and add needed
includes").
So at first I tried adding "#include <linux/kconfig.h>" in
include/env_default.h and include/env_flags.h. That fixes it for some,
but not all, of the above. For example rpi_3_defconfig still fails,
then in log.h complaining about BIT() and u8 not being defined. At
least BIT() is should have gotten from bitops.h, except that that's
behind ifdef __KERNEL__, so not set for the envtools build.
It turns out that the envtools source code in fw_env_private.h already
has some hackery to deal with all this, in the form of the __ASSEMBLY__
games it plays before including config.h. It seems that if we just
make sure to do that include early enough, so that config.h is indeed
parsed with that __ASSEMBLY__ hackery in place, everything builds
fine.
Fixes: 0f92fa45603 ("env: Remove <common.h> and add needed includes")
Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Chia-Wei Wang <chiawei_wang@aspeedtech.com> says:
Aspeed AST2700 SoCs integrates the Caliptra secure IP, where an ECDSA384
signature verification HW interface is exported for SoC crypto needs.
This patch series firstly extends the FIT image signing/verify common
code to support the ECDSA384 algorithm. For better convenience, the
device tree for ECDSA public key storage is also revised by referring
to RSA implementations.
After the FIT common code revision, the driver is implemented for
AST2700 to leverage the Caliptra ECDSA384 signature verification.
These are verified by signed FIT images with the algorithm "sha384,ecdsa384".
Link: https://lore.kernel.org/r/20241014095620.216936-1-chiawei_wang@aspeedtech.com
Aspeed AST27xx SoCs integrate the CPTRA 1.0 secure IP, which export
an ECDSA384_SIGNATURE_VERIFY mailbox command service for SoC to use.
This patch is verified by the FIT signature verification using the
"sha384,ecdsa384" algorithm.
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The padding algorithm is not mandatory for all signing algorithm.
For example, ECDSA does not require a padding method.
For RSA requiring PKCS padding, the belonging info->crypto(), assigned
with rsa_verify_key(), also has the check on the validity of info->padding().
Thus, remove the info->padding check from the upper, general layer.
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add ECDSA384 algorithm support for image signing and verification.
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add AVS and PMIC regulator configs
Also, disable it explicitly in am68_sk_r5_defconfig as it includes
j721s2_evm_r5_defconfig for re-usability.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Reviewed-by: Aniket Limaye <a-limaye@ti.com>
Also adds bootph-pre-ram property to VTM node and the pmic node.
vdd-supply is used to assign the buck regulator that the AVS driver can
use to program the proper voltage which it picked up from e-fuse.
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Reviewed-by: Aniket Limaye <a-limaye@ti.com>
Adaptive Voltage Scaling (AVS) Class 0 is a procedure for lowering the
voltage on certain device power rails. Initialize AVS Class 0.
Link: https://www.ti.com/lit/pdf/spruj28 (Section 5.2.3.3.2.5 AVS-Class0)
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Reviewed-by: Aniket Limaye <a-limaye@ti.com>
Different devices have different MPU clk and dev ID. Currently it had
been hardcoded. Move it to DT based extraction.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Reviewed-by: Aniket Limaye <a-limaye@ti.com>
Check if AVS could not be programmed and print a warning.
Fixes: 9d233b4e3ed6 ("misc: k3_avs: add driver for K3 Adaptive Voltage Scaling Class 0")
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Reviewed-by: Aniket Limaye <a-limaye@ti.com>
This Kconfig depends on DM_PMIC but hadn't be explicitly stated which
could cause config related issues.
Adds the dependency in Kconfig for tps65941.
Fixes: 6b86dd0c1ead ("power: pmic: tps65941: Add support for tps65941 family of PMICs")
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Reviewed-by: Aniket Limaye <a-limaye@ti.com>
Siddharth Vadapalli <s-vadapalli@ti.com> says:
Hello,
This series adds support for the Cadence PCIe controller on TI's K3
family of SoCs to which the J7200 SoC belongs. The driver is an adaptation
of the Linux driver (drivers/pci/controller/cadence/pci-j721e.c) and has
been implemented specifically for Root-Complex mode of operation on the
J7200 SoC. A minor set of changes will be sufficient to support other K3
SoCs as well with plans to implement it in the near future.
Link: https://lore.kernel.org/r/20241014053924.4027491-1-s-vadapalli@ti.com
TI's J7200 SoC has a single instance of PCIe Controller namely PCIe1 which
is a Cadence PCIe Controller. To support PCIe functionality with the PCIe1
instance of PCIe, enable the corresponding configs.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Add support for the Cadence PCIe Controller present on TI's K3 SoCs.
This driver is an adaptation of the Linux driver.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Neil Armstrong <neil.armstrong@linaro.org> says:
We experience huge problems with cache handling on Qualcomm
systems, and it appears the dcache handling in the DWC3 gadget
code is quite wrong and causes operational issues.
This serie fixes the dcache operations on unaligned data,
and properly invalidate buffers when reading back data from
hardware.
Link: https://lore.kernel.org/r/20241011-u-boot-dwc3-gadget-dcache-fixup-v4-0-5f3498d8035b@linaro.org
On Qualcomm systems, the setup buffer and even buffers are in
a bad state at interrupt handling, so invalidate the dcache lines
for the setup_buf and event buffer to make sure we read correct
data written by the hardware.
This fixes the following error:
dwc3-generic-peripheral usb@a600000: UNKNOWN IRQ type -1
dwc3-generic-peripheral usb@a600000: UNKNOWN IRQ type 4673109
and invalid situation in dwc3_gadget_giveback() because setup_buf content
is read at 0s and leads to fatal crash fixed by [1].
[1] https://lore.kernel.org/all/20240528-topic-sm8x50-dwc3-gadget-crash-fix-v1-1-58434ab4b3d3@linaro.org/
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Marek Vasut <marex@denx.de>
The current flush operation will omit doing a flush/invalidate on
the first and last bytes if the base address and size are not aligned
with CACHELINE_SIZE.
This causes operation failures Qualcomm platforms.
Take in account the alignment and size of the buffer and also
flush the previous and last cacheline.
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Since setup_buf is also consumed by hardware DMA, aligns it's
allocation like other hardware buffers by introduce setup_buf_addr
populated by dma_alloc_coherent(), and use it to pass the physical
address of the buffer to the hardware.
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
i2c updates for v2025.01-rc1
- Add support for the following Maxim chips using the existing PCA954x
driver from Maxim:
- MAX7356
- MAX7357
- MAX7358
- MAX7367
- MAX7368
- MAX7369
- introduce "i2c-gpio,sda-output-only" functionality
from Alex
Some I2C slave devices are read-only and don't even answer with NACK.
For example FD65x segment LED controllers.
Make them usable with i2c-gpio,sda-output-only that are already supported
by Linux 6.3+.
Signed-off-by: Alex Shumsky <alexthreed@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Add support for the following Maxim chips using the existing PCA954x
driver:
- MAX7356
- MAX7357
- MAX7358
- MAX7367
- MAX7368
- MAX7369
All added Maxim chips behave like the PCA954x, where a single SMBUS byte
write selects up to 8 channels to be bridged to the primary bus.
Tested using the MAX7358.
Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
expo improvements
binman support for signing FIT images
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Merge tag 'dm-pull-17oct24-take2' of https://gitlab.denx.de/u-boot/custodians/u-boot-dm
A few new x86 commands and minor improvements
expo improvements
binman support for signing FIT images
Move the SR3 bit definition in the right place. Fix
what is likely a rebase artifact. No functional change.
Fixes: 215f1d5794c6 ("mtd: spi-nor: Clear Winbond SR3 WPS bit on boot")
Signed-off-by: Marek Vasut <marex@denx.de>
Fixes of unreleased buffer, deadcode and wrong variable type detected
by coverity scan.
Addresses-Coverity-ID: 510809: Resource leaks (RESOURCE_LEAK)
Addresses-Coverity-ID: 510806: Control flow issues (DEADCODE)
Addresses-Coverity-ID: 510794 Control flow issues (NO_EFFECT)
Signed-off-by: Raymond Mao <raymond.mao@linaro.org>
Building on 32-bit results in a build failure:
cmd/upl.c:75:51: warning: format ‘%lx’ expects argument of type
‘long unsigned int’, but argument 3 has type ‘size_t’
{aka ‘unsigned int’} [-Wformat=]
75 | printf("UPL handoff written to %lx size %lx\n", addr, abuf_size(&buf));
| ~~^ ~~~~~~~~~~~~~~~
| | |
| | size_t {aka unsigned int}
| long unsigned int
| %x
Fixes: 264f4b0b34c0 ("upl: Add a command")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
lmb_add_region() returns a positive integer if the added regions causes
existing regions to be coalesced. We still want to notify the EFI
subsystem about these added regions though, so adjust lmb_add() to only
bail on errors.
This fixes EFI memory allocation on boards with adjacent memory banks as is the
case on several Qualcomm boards like the RB3 Gen 2.
Fixes: 2f6191526a13 (lmb: notify of any changes to the LMB memory map)
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Reviewed-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Without asm/cpu_x86.h inclusion a compiler is not happy:
arch/x86/cpu/cpu_x86.c:14:5: warning: no previous prototype for ‘cpu_x86_bind’ [-Wmissing-prototypes]
arch/x86/cpu/cpu_x86.c:29:5: warning: no previous prototype for ‘cpu_x86_get_vendor’ [-Wmissing-prototypes]
arch/x86/cpu/cpu_x86.c:41:5: warning: no previous prototype for ‘cpu_x86_get_desc’ [-Wmissing-prototypes]
arch/x86/cpu/cpu_x86.c:55:5: warning: no previous prototype for ‘cpu_x86_get_count’ [-Wmissing-prototypes]
Add missing header inclusion.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The compiler is not happy to have no prototypes for the functions that
are not defined static. Add them. This helps avoiding the compiler warnings:
arch/x86/cpu/cpu.c:197:13: warning: no previous prototype for ‘board_final_init’ [-Wmissing-prototypes]
arch/x86/cpu/cpu.c:205:13: warning: no previous prototype for ‘board_final_cleanup’ [-Wmissing-prototypes]
arch/x86/cpu/cpu.c:307:5: warning: no previous prototype for ‘reserve_arch’ [-Wmissing-prototypes]
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Some functions are not used anywhere except the same file
where they are defined. Mark them static. This helps avoiding
the compiler warnings:
arch/x86/cpu/cpu.c:343:6: warning: no previous prototype for ‘detect_coreboot_table_at’ [-Wmissing-prototypes]
arch/x86/cpu/mtrr.c:90:6: warning: no previous prototype for ‘mtrr_write_all’ [-Wmissing-prototypes]
arch/x86/cpu/i386/interrupt.c:240:6: warning: no previous prototype for ‘__do_irq’ [-Wmissing-prototypes]
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Most of the copies of the print_cpuinfo() call the default method.
Remove all of those in order to have only the default one when
no `cpu` command is compiled.
This also helps avoiding compiler warning, e.g.:
arch/x86/cpu/tangier/tangier.c:23:5: warning: no previous prototype for ‘print_cpuinfo’ [-Wmissing-prototypes]
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The real-time clock is needed for most X86 systems and it is useful to
be able to read from it. Enable the rtc command by default.
Signed-off-by: Simon Glass <sjg@chromium.org>
Update to a newer version which supports settings in CMOS RAM and
linear framebuffer.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
The scene_txt_str() function calls expo_str() so there is no need to
call it beforehand. Drop this unnecessary code.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present menu items are stored according to their sequence number in
the menu. In some cases we may want to have holes in that sequence, or
not use a sequence at all.
Add a new 'value' property for menu items. This will be used for
reading and writing, if present. If there is no 'value' property, then
the normal sequence number will be used instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
Set aside some expo IDs for 'save' and 'discard' buttons. This avoids
needing to store the IDs for these. Adjust the documentation and expo
tool for the new EXPOID_BASE_ID value.
Ignore these objects when saving and loading the cedit, since they do
not contain real data.
Adjust 'cedit run' to return failure when the user exits the expo
without saving. Update the test for this change as well.
Signed-off-by: Simon Glass <sjg@chromium.org>
If expo_set_dynamic_start() is never called, the first scene created
will have an ID of 0, which is invalid. Correct this by setting a
default value.
Add a test to check this.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present a fixed position is used for menu items, 200 pixels to the
right of the left side of the labels. This means that a menu item with
a very long label may overlap the items.
It seems better to calculate the maximum label width and then place the
items to the right of all of them.
To implement this, add a new struct to containing arrangement
information. Calculate it before doing the actual arrangement. Add a
new style item which sets the amount of space from the right side of
the labels to left side of the items.
Signed-off-by: Simon Glass <sjg@chromium.org>
When starting a new text line, an assumption is made that the current
vertical position is a multiple of the character height. When this is
not true, characters can be written after the end of the framebuffer.
This can causes crashes and strange errors from QEMU.
Adjust the scrolling check when processing a newline character, to
avoid any problems.
Add some comments to make things a little clearer.
Signed-off-by: Simon Glass <sjg@chromium.org>
