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3 Commits

Author SHA1 Message Date
Patrick Delaunay
e70f70aa65 ram: stm32mp1: add driver 
Add driver and binding for stm32mp1 ddr controller and phy

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
 2018-03-19 16:14:21 -04:00
Patrice Chotard
f303aaf21b ram: stm32: add second SDRAM bank management 
FMC is able to manage 2 SDRAM banks, but the current driver
implementation is only able to manage the first SDRAM bank.

Even if only bank2 is used, some bank1 registers must be
configured.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
 2017-07-26 11:29:15 -04:00
Vikas Manocha
fd198ee1a8 ARM: DT: stm32f7: add sdram pin contol node 
Also added DT binding doc for stm32 fmc(flexible memory controller).

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>
 2017-05-08 11:39:03 -04:00