The number of DDR controllers to be initialised and used should depend
on the device tree with the constraint of the maximum number of
controllers the device supports. Since J721S2 has multiple (2)
controllers, instead of hardcoding the number of probes, move to
depending on the device tree UCLASS_RAM nodes present.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
This commit enables support for DM_SERIAL in the vexpress_ca9x4 boards.
When running the board with the DM_SERIAL driver, the board ran out of
memory in SPL when initialising the DM serial driver.
Thus this required an increase in the pre-allocated SRAM memory. I did
increase it to 0x800, and it now works graciously.
It could probably be set lower, but I do not see any reason not to use the
available SRAM at this point.
Also adds stdout-path to the 'chosen' node in the device tree.
Signed-off-by: Ole P. Orhagen <ole.orhagen@northern.tech>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Writing to eMMC using HS200 mode work more reliably then other modes on
RK356x boards.
Add device tree props and enable Kconfig options for eMMC HS200 mode on
the generic RK3566/RK3568 board. Also enable the pinctrl driver in SPL
and add missing rk3568-generic.dtb to Makefile.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Testing has shown that writing to eMMC using a slower mode then HS200
typically generate an ERROR on first attempt on RK3588.
# Rescan using MMC legacy mode
=> mmc rescan 0
# Write a single block to sector 0x4000 fails with ERROR
=> mmc write 20000000 4000 1
# Write a single block to sector 0x4000 now works
=> mmc write 20000000 4000 1
With the MMC_SPEED_MODE_SET Kconfig option enabled.
Writing to eMMC using HS200 mode work more reliably than slower modes on
RK35xx boards. Enable MMC_HS200_SUPPORT Kconfig option by default to
prefer use of HS200 mode on RK356x and RK3588.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Testing has shown that writing to eMMC using DDR52 mode does not seem to
work on RK356x and RK3588 boards.
A simple test of writing a single block to e.g. sector 0x4000 fails:
# Rescan using DDR52 mode
=> mmc rescan 4
# Write a single block to sector 0x4000 fails with ERROR
=> mmc write 20000000 4000 1
With the MMC_SPEED_MODE_SET Kconfig option enabled.
Fix this by removing the mmc-ddr-1_8v prop from sdhci nodes in affected
board u-boot.dtsi files.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Remove unnecessary status props from rk35xx u-boot.dtsi files, regular
device tree files or default value already enable the affected nodes.
Also reorder bootph-pre-ram and clock-frequency props alphabetically in
rk3588s-u-boot.dtsi uart2 node.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add a default u-boot,spl-boot-order prop to rk3588s-u-boot.dtsi and
remove the prop from board u-boot.dtsi files using the default value.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Sync rk3588 device tree from linux v6.7.
Also drop the rockchip,rk3568-dwc3 compatible now that dwc3-generic
driver support the rockchip,rk3588-dwc3 compatible.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Move uart2 bootph-pre-ram and clock-frequency props from board to SoC
u-boot.dtsi. Regular board device tree already enables the uart2 node,
so status prop is dropped from u-boot.dtsi file.
Also remove unnecessary stdout-path = &uart2, regular board device tree
already provide a stdout-path = "serial2:" value.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Rockchip RK3399 and RK3588 SoCs can support wide range of bootflows.
Without full bootflow commands, it can be difficult to
figure out issues if any, hence enable by default.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Shantur Rathore <i@shantur.com>
rv1126 requires OPTEE as it provides pcsi support. Mainline Linux
kernel will fail to boot without this.
Select SPL_OPTEE_IMAGE when building FIT image. TEE must be provided
when building.
Signed-off-by: Tim Lunn <tim@feathertop.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Sonoff iHost is gateway device designed to provide a Smart Home Hub,
it is based on Rockchip RV1126. There is also a version with 2GB RAM
based off the RV1109 dual core SoC however this works with the same
config as the RV1126 for uboot purposes.
Features:
- Rockchip RV1126
- 4GB DDR4
- 8GB eMMC
- microSD slot
- RMII Ethernet PHY
- 1x USB 2.0 Host
- 1x USB 2.0 OTG
- Realtek RTL8723DS WiFi/BT
- EFR32MG21 Silabs Zigbee radio
- Speaker/Microphone
Signed-off-by: Tim Lunn <tim@feathertop.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Sync linux dts files for rv1126 boards from linux v6.8-rc1 tag. Includes
the newly added dts for Sonoff iHost.
Signed-off-by: Tim Lunn <tim@feathertop.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This patch add support for additional bank info used by LPDDR5.
Series-version: 2
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
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Merge tag 'u-boot-at91-2024.04-a' of https://source.denx.de/u-boot/custodians/u-boot-at91
First set of u-boot-at91 features for the 2024.04 cycle:
This set includes some DT alignments and solves a compile issue for
custom nand defconfigs.
MBOX and Watchdog on RPi5/bcm2712 have a different base IO offsets.
Find them via devicetree blob passed by bootloader.
Signed-off-by: Dmitry Malkin <dmitry@bedrocksystems.com>
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
Tested-by: Jens Maus <mail@jens-maus.de>
Tested-by: Darko Alavanja <darko.alavanja@konsulko.com>
Signed-off-by: Ivan T. Ivanov <iivanov@suse.de>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
This includes:
* 1GB of RAM (from 4GB or 8GB total)
* AXI ranges (main peripherals)
When HDMI cable is plugged in at boot time firmware will
insert "simple-framebuffer" device into devicetree and will
shrink first memory region to 0x3f800000UL. Board setup then
will properly reserve framebuffer region.
When no HDMI cable is plugged in the size of the region will
be 0x3fc00000UL.
Signed-off-by: Dmitry Malkin <dmitry@bedrocksystems.com>
Tested-by: Jens Maus <mail@jens-maus.de>
Tested-by: Darko Alavanja <darko.alavanja@konsulko.com>
Signed-off-by: Ivan T. Ivanov <iivanov@suse.de>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Devarsh Thakkar <devarsht@ti.com> says:
Move video memory reservation for SPL at end of RAM so that it does
not interefere with reservations for next stage so that the next stage
need not have holes in between for passed regions and instead it can
maintain continuity in reservations.
Also catch the bloblist before starting reservations to avoid the same
problem.
While at it, also fill missing fields in video handoff struct before
passing it to next stage.
This is as per discussions at :
For moving SPL framebuffer reservation at end of RAM:
https://lore.kernel.org/all/CAPnjgZ3xSoe_G3yrqwuAvoiVjUfZ+YQgkOR0ZTVXGT9VK8TwJg@mail.gmail.com/
For filling missing video handoff fields :
https://lore.kernel.org/all/CAPnjgZ1Hs0rNf0JDirp6YPsOQ5=QqQSP9g9qRwLoOASUV8a4cw@mail.gmail.com/
Setup video memory before page table reservation using
"spl_reserve_video_from_ram_top" which ensures framebuffer memory gets
reserved from the end of RAM.
This is done to enable the next stage to directly skip the
pre-reserved area from previous stage right from the end of RAM without
having to make any gaps/holes to accommodate those regions which was the
case before as previous stage reserved region not from the end of RAM.
Use gd->ram_top instead of local ram_top and update gd->reloc_addr after
each reservation to ensure further regions are reserved properly.
Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
Reviewed-by: Nikhil M Jain <n-jain1@ti.com>
Some 32-bit SoCs can use SCP firmware to implement additional PSCI
functionality, such as system suspend. In order to load this firmware
from SPL, we need to generate and use a FIT instead of a legacy image.
Adjust the binman FIT definition so it does not rely on TF-A BL31, as
this is not used on 32-bit SoCs. Instead, after loading the firmware,
U-Boot proper is executed directly. This requires to provide an
entry point property for the U-Boot image node, which confuses some
loaders like sunxi-fel, so protect that to only be used if we have no
BL31.
Signed-off-by: Samuel Holland <samuel@sholland.org>
[Andre: filter U-Boot entry point property]
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This is easier to read than the #ifdef staircase, provides better
visibility into the memory map (alongside the other Kconfig
definitions), and allows these addresses to be reused from code.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
This is a Chinese TV box based on Allwinner H618 SoC.
The DRAM parameters were derived from the values found in a firmware update.
Signed-off-by: Nick Alilovic <nickalilovic@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Sync the devicetree files from the official Linux kernel tree, v6.8-rc1.
This time only small changes in the existing files, but five new boards
got added, which opens the door for their respective defconfig files.
As before, this omits the non-backwards compatible changes to the R_INTC
controller, to remain compatible with older kernels.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
At the moment every Allwinner board builds and requires an SPL, even
though we select this individually in each _defconfig file.
For experiments and for early bringup of new SoCs it would be beneficial
to only build U-Boot proper, for instance to postpone a tedious SPL port
(including DRAM support) in the initial phase.
Protect some SPL related symbols that we unconditionally select at the
moment with "if SPL", to avoid Kconfig conflicts when CONFIG_SPL is
disabled.
This alone does not cleanly build U-Boot proper only yet, but gets it
far enough so that the binary can be harvested.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The usage of the common.h include file is deprecated, and has already
been removed from several files.
Get rid of all inclusions in the arch/arm/mach-sunxi directory. Most
files actually don't need the header at all, for the few others just
include the headers that we actually require.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The cpu_sun9i.h header file defined the base addresses for quite some
peripherals of the Allwinner A80 CPU, even though we now only use a
fraction of that.
Most of the addresses are now either read from the DT, or were never
used in U-Boot in the first place.
Removed the ones that are not used in the whole of the U-Boot source.
to make it clear that this file only contains addresses that are needed
for the SPL operation.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The cpu_sun4i.h header file defined the base addresses for quite some
peripherals of earlier Allwinner CPUs, even though we now only use a
fraction of that.
Most of the addresses are now either read from the DT, or were never
used in U-Boot in the first place.
Removed the ones that are not used in the whole of the U-Boot source.
to make it clear that this file only contains addresses that are needed
for the SPL operation.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The cpu_sun50i_h6.h header file defined the base addresses for quite some
peripherals of the Allwinner H6 and related CPUs, even though we now only
use a fraction of that.
Most of the addresses are now either read from the DT, or were never used
in U-Boot in the first place.
Removed the ones that are not used in the whole of the U-Boot source.
to make it clear that this file only contains addresses that are needed
for the SPL operation.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Add two functions, one which returns the SoC speed grade and one
which returns the SoC operating temperature range.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
mach-k3/am625_fdt.c does fdt fixup depending on fields in the device
identification register. Move the accessors to the device identification
register as inline functions into the am62_hardware.h header, so that
they can be used for other functionality.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Add support for WinLink E850-96 board [1]. It's based on Exynos850 SoC
and follows 96boards specification, so it's compatible with 96boards
mezzanine boards [2]. This patch enables next features:
* Serial console
* USI
* PMU (muxing AP UART path)
* Pinctrl
* Clocks
* Timer (ARMv8 architected)
* Reset control
It's quite a minimal enablement. Features like MMC, USB and Ethernet
will be enabled later.
The rationale for config values is as follows:
* TEXT_BASE = 0xf8800000
That's where BL2 loads the U-Boot payload, so TEXT_BASE must be
exactly this value. Overall the memory map is designed in a way to
keep the bootloader in the upper 128 MiB area of RAM, which is
0xf8000000..0xffffffff. That includes bootloader's code, stack,
data, heap, MMU tables, etc. All the memory below that 128 MiB chunk
can be used for storing boot images (0x80000000..0xf8000000).
* CUSTOM_SYS_INIT_SP_ADDR = 0xf8c00000
Just 4 MiB above the TEXT_BASE address, to leave enough space for
U-Boot code and stack itself (grows downwards).
* SYS_LOAD_ADDR = 0x80000000
The beginning of RAM. That's where Linux kernel image must be
loaded.
* SYS_MALLOC_LEN = 0x81f000
8 MiB for malloc() + ENV_SIZE (128 KiB)
* SYS_MALLOC_F_LEN = 0x4000
Increase malloc() pool size available before relocation from 8 KiB
(default) to 16 KiB. Otherwise "alloc space exhausted" message
appears in U-Boot log during board_init_f() stage. There are next
reasons for doing so:
1. Having "bootph-all" flags in some dts nodes leads to binding
those during pre-relocation stage, and binding (DM) uses
dynamic memory allocation
2. clk-exynos850 driver uses CCF clocks, which in turn use dynamic
memory allocation
Device tree file was imported from Linux kernel. All nodes and boot
phase flags added in exynos850-e850-96-u-boot.dtsi are only needed to
enable serial console:
* oscclk -> cmu_top -> cmu_peri: generate UART/USI clocks
* pinctrl_alive and uart1_pins: needed to mux UART pins
* pmu_system_controller: configures AP UART path to uart1_pins
* usi_uart: configures USI block to operate as a UART protocol
* serial_0: enables serial console (UART)
[1] https://www.96boards.org/product/e850-96b/
[2] https://www.96boards.org/products/mezzanine/
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Samsung Exynos850 is ARMv8-based mobile-oriented SoC. It features
Cortex-A55 CPU (8 cores) and it's built using 8nm process.
Add Exynos850 support by enabling next features:
* Import Exynos850 SoC dtsi files from Linux kernel
* Add Exynos850 MMU memory map
* Introduce ARCH_EXYNOS9 platform config option
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
The help for CONFIG_MTD explains that it needs to be enabled for various
things like NAND, etc to be available. It however then doesn't enforce
this dependency and so if you have none of these systems present you
still need to disable a number of options. Fix this by making places
that select/imply one type of flash, but did not do the same, also do
this for "MTD". Make boards which hadn't been enabling MTD already but
need it now, do so. In a few places, disable CONFIG_CMD_MTDPARTS as it
wasn't previously enabled but was now being implied.
Signed-off-by: Tom Rini <trini@konsulko.com>
This specific bit logic is used to determine what NAND chip is present
on a board in order to then know what revision of the board we have and
so what DDR chips are present. We can only do this if we have a NAND
chip, and so we will have NAND_OMAP_GPMC enabled.
Signed-off-by: Tom Rini <trini@konsulko.com>
- Allow i.MX8M Plus DHCOM to operate in overdrive mode.
- Allow i.MX8M Plus eDM SBC to operate in overdrive mode.
- Enable the 'kaslrseed' command on DH i.MX8M Plus DHCOM.
- Select LTO by default on i.MX8M.
- Convert pico-dwarf/hobbit-imx6ul to CONFIG_DM_SERIAL.
- Fix 'reset' command on wandboard.
Commit 68dcbdd594d4 ("ARM: imx: Add weak default reset_cpu()") caused
the 'reset' command in U-Boot to not cause a board reset.
Fix it by switching to the watchdog driver model via sysreset, which
is the preferred method for implementing the watchdog reset.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
In an attempt to select ARMV8_SPL_EXCEPTION_VECTORS, the SPL size
could not fit into the internal SRAM of some imx8m targets:
aarch64: + imx8mm_phg
+aarch64-linux-ld.bfd: u-boot-spl section `__u_boot_list' will not fit in region `.sram'
+aarch64-linux-ld.bfd: region `.sram' overflowed by 1824 bytes
Select LTO to prevent that.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
The reserved space is extended to 32MB in Linux kernel because
additional space is needed for authorization execution of JIC/RBF file.
U-Boot required to align with Linux.
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
This patch is to add SPI clock support for stratix10. Get clock rate
function always returning 0 because the DW-SPI driver get the rate
from clock node in dts but Stratix10 does not support device tree
clock node.To overcome this spi will get the clock_rate directly
from spi clock controller override the weaker function.
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
Port from Linux v6.7-rc4. Should not hurt U-Boot but makes diffing
easier and allows referencing node names in board dts.
Signed-off-by: Alexander Dahl <ada@thorsis.com>
