Placing the snps,reset content needed for Ethernet to probe in a common
uboot.dtsi results in the content not being used and broken Ethernet. Fix
this by creating two board specific dtsi files with the right content.
Fixes: 67d5128df950 ("ARM: dts: add support for WeTek Hub and WeTek Play2")
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Link: https://lore.kernel.org/r/20240324151905.3817732-2-christianshewitt@gmail.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Enable both usbotg1 and usbotg2 ports. Disable over-current as OC pins are
not connected to the SoC.
This addition to imx93-phyboard-segin-u-boot.dtsi is temporary,
until USB support is added to imx93-phyboard-segin.dts in Linux.
Signed-off-by: Mathieu Othacehe <othacehe@gnu.org>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Marek Vasut <marex@denx.de>
This message is used to commit into the fuses any new SRK revocation and
FW version information that have been found into the NXP (ELE FW) and
OEM containers.
Signed-off-by: Mathieu Othacehe <othacehe@gnu.org>
The lowest speed grade of Toradex AM62 SoMs is K speed, resulting in a
max value of 800MHz for the CPU operating frequency. A solution with
runtime selection of the CPU frequency is already planned to avoid these
kinds of problems in the future.
Fixes: 8fb8a6d49977 ("arm: dts: k3-am625-verdin-r5:Change CPU frequency to 1000MHz")
Signed-off-by: Joao Paulo Goncalves <joao.goncalves@toradex.com>
mach Kconfig file select some options independently of if SPL is actually
enabled. It ends up in situation that SPL is disabled but symbols are still
present in .config. That's why add SPL dependency for them but also group
them with other SPL options in ARCH_ZYNQMP fragment with using imply
option. This should ensure the same behavior as default y.
Also fixed SPL_ZYNQMP_PSU_INIT_ENABLED for the same.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/8dc4b799d36f963a3e1ebb5b24793632dc360b61.1710258674.git.michal.simek@amd.com
Current Cache Size ID Register (ccsidr_el1) has two "flavors"
depending on whether FEAT_CCIDX is implemented or not.
When FEAT_CCIDX is implemented Associativity parameter
is coded on bits [23:3] and NumSets parameter on bits [55:32].
When FEAT_CCIDX is not implemented then Associativity parameter
is coded on bits [12:3] and NumSets parameter on bits [27:13].
Current U-Boot code does not check whether FEAT_CCIDX is implemented
and always parses ccsidr_el1 as if FEAT_CCIDX was not implemented.
This is of course wrong on systems where FEAT_CCIDX is implemented.
This patch fixes that problems and tests whether FEAT_CCIDX
is implemented or not and accordingly parses the ccsidr_el1 register.
Signed-off-by: Lukasz Wiecaszek <lukasz.wiecaszek@gmail.com>
Arm's GIC-600 features a Power Register (GICR_PWRR),
which needs to be programmed to enable redistributor
operation. Power on the redistributor and wait until
the power on state is reflected by checking the bit
GICR_PWRR.RDPD == 0. While running U-Boot in EL3
without enabling this register, GICR_WAKER.ChildrenAsleep
bit is not getting cleared and loops infinitely.
This register(GICR_PWRR) must be programmed to mark the frame
as powered on, before accessing other registers in the frame.
Rest of initialization sequence remains the same.
ARM GIC-600 IP complies with ARM GICv3 architecture.
Enable this config if GIC-600 IP present.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Corrects the ti,sci property to point to dm_tifs node for proper
functioning of mcu_ringacc and mcu_udmap.
Fixes: df73e791ce09 ("arm: dts: j7200: dts sync with Linux 6.6-rc1")
Signed-off-by: Aniket Limaye <a-limaye@ti.com>
- Add the missing bootph-all property in the flash subnode for ospi
- Add the missing overrides for the ospi node in the r5 devicetree
Signed-off-by: Aniket Limaye <a-limaye@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
load_firmware() API calls fs-loader APIs and checks for CONFIG_FS_LOADER
before calling those APIs. The if check only checks for CONFIG_FS_LOADER
but not for CONFIG_SPL_FS_LOADER.
When CONFIG_FS_LOADER is enabled, load_firmware() API calls fs-loader APIs
but this is done at SPL stage and at this time FS_LOADER is not built yet
as a result we see below build error.
AR spl/boot/built-in.o
LD spl/u-boot-spl
arm-none-linux-gnueabihf-ld.bfd: arch/arm/mach-k3/common.o: in function
`load_firmware':
/home/danish/workspace/u-boot/arch/arm/mach-k3/common.c:184: undefined
reference to `get_fs_loader'
arm-none-linux-gnueabihf-ld.bfd:
/home/danish/workspace/u-boot/arch/arm/mach-k3/common.c:185: undefined
reference to `request_firmware_into_buf'
make[2]: *** [/home/danish/workspace/u-boot/scripts/Makefile.spl:527:
spl/u-boot-spl] Error 1
make[1]: *** [/home/danish/workspace/u-boot/Makefile:2055:
spl/u-boot-spl] Error 2
make[1]: Leaving directory '/home/danish/uboot_images/am64x/r5'
make: *** [Makefile:177: sub-make] Error 2
Fix this by modifying the if check to CONFIG_IS_ENABLED(FS_LOADER) instead
of IS_ENABLED(CONFIG_FS_LOADER) as the former will check for the
appropriate config option (CONFIG_SPL_FS_LOADER / CONFIG_FS_LOADER) based
on the build stage.
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
Acked-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
- A new driver in the misc to register setting from device tree. This
also provides user a clean interface and all register settings are
centralized in one place, device tree.
- Enable Agilex5 platform for Intel product. Changes, modification and
new files are created for board, dts, configs and makefile to create
the base for Agilex5.
Build-tested on SoC64 boards, boot tested on some of them.
This patch is to enable Agilex5 platform for Intel
product. Changes, modification and new files are
created for board, dts, configs and makefile to
create the base for Agilex5.
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
Add socfpga_dtreg driver enablement for Intel SoCFPGA.
Signed-off-by: Wan Yee Lau <wan.yee.lau@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
Move to imx8m{m,n,p}-venice to OF_UPSTREAM:
- replace the non-upstream generic imx8m{m,n,p}-venice dt with one of the
dt's from the OF_LIST
- handle the fact that dtbs now have a 'freescale/' prefix
- imply OF_UPSTREAM
- remove rudundant files from arch/arm/dts leaving only the
*-u-boot.dtsi files
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
On imx8m[m|p|q].dtsi, upstream Linux uses different names for NPU/VPU
IP block nodes. It leads variants without such HW block having it
enabled by default.
This patch adds the upstream Linux node's paths to the disable list while
keep the compatibility with downstream Linux.
Signed-off-by: Vitor Soares <vitor.soares@toradex.com>
Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Please pull the updates for rockchip platform:
- Add board: rk3588 Generic, Cool Pi CM5, Theobroma-Systems RK3588 Jaguar SBC,
Toybrick TB-RK3588X;
rk3588s Cool Pi 4B;
rk3566 Pine64 PineTab2;
- Add saradc v2 support;
- Add PMIC RK806 support;
- rk3588 disable force_jtag by default;
- Migrate to use IO-domain driver for all boards;
- Use common bss and stack addresses for rk33xx and rk35xx boards;
- Other updates for driver, config and dts;
ADC support is implied by the Rockchip arch Kconfig but that means it
should be possible to disable ADC support and still be able to build.
However the weak implementation of rockchip_dnl_key_pressed() currently
blindly use functions from the ADC subsystem which do not exist when ADC
is not enabled, failing the build.
Therefore, let's encapsulate this logic with a check on the ADC symbol
being selected.
Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Currently, if the environment is stored on an MMC device, the device
number is hardcoded by CONFIG_SYS_MMC_ENV_DEV. This is problematic
because many boards can choose between booting from an SD card or a
removable eMMC. For example, the Rock64 defconfig sets
CONFIG_SYS_MMC_ENV_DEV=1, which corresponds to the SD card. If an eMMC
is used as the boot device and no SD card is installed, it is impossible
to save the environment.
To avoid this problem, we can choose the environment MMC device based on
the boot device. The theobroma-systems boards already contain code to do
this, so this commit simply moves it to the common Rockchip board file,
with some refactoring. I also removed another implementation of
mmc_get_env_dev() from tinker_rk3288 that performed MMC boot device
detection by reading a bootrom register.
This has been tested on a Rock64v2.
Signed-off-by: Ben Wolsieffer <benwolsieffer@gmail.com>
Reviewed-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Add support to the RGxx3 device for the Powkiddy RGB10MAX3. This device
is extremely similar to all the other devices and can use the same
bootloader with the same detection logic.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Remove unnecessary clock frequency defines from the RGxx3 u-boot dts.
Move the necessary defines to the RGxx3 main dts file.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Move the call to gpt_capsule_update_setup() from the weak function
rk_board_late_init() into the main board_late_init() function.
Also change to use IS_ENABLED() instead for defined().
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Move ROCK Pi 4 specific board code from the shared evb_rk3399 target
into its own board target and update related defconfigs to use the new
TARGET_ROCKPI4_RK3399 option.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Christopher Obbard <chris.obbard@collabora.com>
Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
USB gadget is not working fully as expected on RK3328, it uses a
board_usb_init() function to initialize the DWC2 OTG port.
The board_usb_init() function does not intgrate with the generic phy
framework and as a result the USB phy is not properly configured before
or after USB gadget use.
Having both USB_DWC2 and DWC2_OTG enabled for the same board is also
causing some issues.
Trying to use rockusb or ums command after usb stop result in a freeze
due to usb stop is putting the phy in a suspended state.
=> usb start
=> usb stop
=> ums 0 mmc 0
--> freeze due to usb phy is suspended <--
Fix this by only using one of USB_DWC2 (host) or DWC2_OTG (peripheral)
depending on the most likely usage of the otg port and by migrating to
use DM_USB_GADGET instead of a board_usb_init() function.
The nanopi-r2 and orangepi-r1-plus variants share OTG and power using a
Type-C connector, mark these boards dr_mode as peripheral, the most
likely usage is for recovery and image download.
The rock64 and roc-cc currently use dr_mode as host, remove the DWC2_OTG
driver from these boards to ensure that the USB_DWC2 driver is used.
The rock-pi-e board does not enable the usb20_otg node so both USB_DWC2
and DWC2_OTG is removed from this board.
Enable RockUSB and UMS on all boards with a otg port in peripheral mode.
Also with the migration to DM_USB_GADGET completed the U-Boot specific
change to reorder usb nodes in the soc device tree can be reverted.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Change to use the common Product ID 0x0010 when the ums command is used.
This matches downstream vendor U-Boot and is a Product ID that tools
such as rkdeveloptool and RKDevTool will identify as MSC mode.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The board_usb_init() and board_usb_cleanup() functions is always
included when USB_GADGET and USB_GADGET_DWC2_OTG is enabled.
Prepare for a change to use DM_USB_GADGET with DWC2_OTG by adding an
extra ifdef condition. The extra separate ifdef for USB_GADGET prepare
for next patch that adds a g_dnl_bind_fixup() function.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Currently the following memory layout is typically used on RK3588:
[ 0, 256K) - SPL binary
[ 256K, 2M) - TF-A / reserved
[ -X, 4M) - SPL pre-reloc stack (SPL_STACK)
[ 3.5M, 4M) - pre-reloc malloc heap (SPL_SYS_MALLOC_F_LEN)
[ -X, 6M) - SPL reloc stack (SPL_STACK_R_ADDR)
[ 5M, 6M) - reloc malloc heap (SPL_STACK_R_MALLOC_SIMPLE_LEN)
[ 10M, +X) - U-Boot proper binary (TEXT_BASE)
[ -X, 12M) - U-Boot proper pre-reloc stack (CUSTOM_SYS_INIT_SP_ADDR)
[11.5M, 12M) - pre-reloc malloc heap (SYS_MALLOC_F_LEN)
[ 64M, +16K) - SPL bss (SPL_BSS_START_ADDR, SPL_BSS_MAX_SIZE)
SPL can safely load U-Boot proper + FDT to [10M, 11.5M) with this layout.
However, on ROCK 5A the SPL stacks is overlapping:
[ -X, 16M) - SPL pre-reloc stack (SPL_STACK)
[15.5M, 16M) - pre-reloc malloc heap (SPL_SYS_MALLOC_F_LEN)
[ -X, 16M) - SPL reloc stack (SPL_STACK_R_ADDR)
[ 15M, 16M) - reloc malloc heap (SPL_STACK_R_MALLOC_SIMPLE_LEN)
Because bind and probe udevice instanses is allocated on the pre-reloc
malloc heap, there is going to be an overlap when reloc malloc heap
reaches close to 512 KiB of usage.
Migrate to use common bss, stack and malloc heap size and addresses to
mitigate these limitations and allow for a larger U-Boot proper size.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
(Update for new boards defconfig)
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
With the stack and text base used by U-Boot SPL and proper on RK3399
there is a high likelihood of overlapping when U-Boot proper + FDT nears
or exceeded 1 MiB in size.
Currently the following memory layout is typically used on RK3399:
[ 0, 256K) - SPL binary
[ 256K, 2M) - TF-A / reserved
[ 2M, +X) - U-Boot proper binary (TEXT_BASE)
[ -X, 3M) - U-Boot proper pre-reloc stack (CUSTOM_SYS_INIT_SP_ADDR)
[ -16K, 3M) - pre-reloc malloc heap (SYS_MALLOC_F_LEN)
[ -X, 4M) - SPL pre-reloc stack (SPL_STACK)
[ -16K, 4M) - pre-reloc malloc heap (SPL_SYS_MALLOC_F_LEN)
[ 4M, +8K) - SPL bss (SPL_BSS_START_ADDR, SPL_BSS_MAX_SIZE)
[ -X, 64M) - SPL reloc stack (SPL_STACK_R_ADDR)
[ 63M, 64M) - reloc malloc heap (SPL_STACK_R_MALLOC_SIMPLE_LEN)
SPL can safely load U-Boot proper + FDT to [2M, 4M-16K) with this layout.
However, the stack at [-X, 3M) used during U-Boot proper pre-reloc is
restricting the safe size of U-Boot proper + FDT to be less than 1 MiB.
Migrate to use common bss, stack and malloc heap size and addresses to
fix this restriction and allow for a larger U-Boot proper image size.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
With the stack and text base used by U-Boot SPL and proper on RK3328
there is a high likelihood of overlapping when U-Boot proper + FDT nears
or exceeded 1 MiB in size.
Currently the following memory layout is typically used on RK3328:
[ 0, 256K) - SPL binary
[ 256K, 2M) - TF-A / reserved
[ 2M, +X) - U-Boot proper binary (TEXT_BASE)
[ -X, 3M) - U-Boot proper pre-reloc stack (CUSTOM_SYS_INIT_SP_ADDR)
[ -8K, 3M) - pre-reloc malloc heap (SYS_MALLOC_F_LEN)
[ -X, 4M) - SPL pre-reloc stack (SPL_STACK)
[ -8K, 4M) - pre-reloc malloc heap (SPL_SYS_MALLOC_F_LEN)
[ -X, 6M) - SPL reloc stack (SPL_STACK_R_ADDR)
[ 5M, 6M) - reloc malloc heap (SPL_STACK_R_MALLOC_SIMPLE_LEN)
[ 32M, +8K) - SPL bss (SPL_BSS_START_ADDR, SPL_BSS_MAX_SIZE)
SPL can safely load U-Boot proper + FDT to [2M, 4M-8K) with this layout.
However, the stack at [-X, 3M) used during U-Boot proper pre-reloc is
restricting the safe size of U-Boot proper + FDT to be less than 1 MiB.
Migrate to use common bss, stack and malloc heap size and addresses to
fix this restriction and allow for a larger U-Boot proper image size.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
On Rockchip the typical aarch64 boot steps are as follows:
- BROM load TPL to SRAM
- TPL init full DRAM
- use stack in SRAM at TPL_STACK addr
- use malloc heap on stack, size is TPL_SYS_MALLOC_F_LEN
- TPL jump back to BROM
- BROM load SPL to beginning of DRAM
- SPL init storage devices
- use bss in DRAM at SPL_BSS_START_ADDR, size is SPL_BSS_MAX_SIZE
- use stack in DRAM at SPL_STACK addr (or CUSTOM_SYS_INIT_SP_ADDR)
- use malloc heap on stack, size is SPL_SYS_MALLOC_F_LEN
- SPL load FIT images from storage to DRAM
- use stack in DRAM at SPL_STACK_R_ADDR
- use new malloc heap on stack, size is SPL_STACK_R_MALLOC_SIMPLE_LEN
- SPL jump to TF-A at 0x40000
- (optional) TF-A load OPTEE
- TF-A jump to U-Boot proper at TEXT_BASE
- U-Boot proper init pre-reloc devices
- use stack in DRAM at CUSTOM_SYS_INIT_SP_ADDR
- use malloc heap on stack, size is SYS_MALLOC_F_LEN
- U-Boot proper relocate to end of usable DRAM
- U-Boot proper init devices and complete boot
SPL have access to full DRAM, however, current configuration for text
base, stack addr and malloc heap size used at the different boot steps
are at risk of overlapping, e.g. when U-Boot proper + FDT grows close
to 1 MiB on RK3328/RK3399 or when pre-reloc and reloc stack and malloc
heap overlap on ROCK 5A.
Fix this by defining safe defaults for bss, stack and malloc size and
addresses. A range at around [60 MiB, 64 MiB) was chosen to be used for
bss and stack until U-Boot proper have been relocated to end of usable
DRAM. The range was primarily chosen to be able to accommodate SoCs with
a small amount of embedded DRAM, e.g. RK3308G has 64 MiB DRAM.
Overiew of the new common memory layout:
[ 0, 2M) - SPL / TF-A / reserved
[ 2M, +X) - U-Boot proper pre-reloc
[ -X, 64M) - bss, stack and malloc heap
During SPL pre-reloc phase:
[ 0, 256K) - SPL binary is loaded by BROM to beginning of DRAM
[ -X, 63M) - SPL pre-reloc stack
[ -32K, 63M) - SPL pre-reloc malloc heap
[63.5M, +32K) - SPL bss
After SPL reloc phase:
[ 0, 256K) - SPL binary
[ 256K, +X) - TF-A image is loaded by SPL
[ 2M, +X) - U-Boot proper + FDT image is loaded by SPL
[ -X, 62M) - SPL reloc stack
[ 60M, 62M) - SPL reloc malloc heap
[ -32K, 63M) - SPL init malloc heap, memory allocated during SPL
pre-reloc phase is still in use at reloc phase
[63.5M, +32K) - SPL bss
During U-Boot proper pre-reloc phase:
[ 0, 2M) - TF-A / reserved
[ 2M, +X) - U-Boot proper + FDT
[ -X, 63M) - U-Boot proper pre-reloc stack (shared addr with SPL)
[ -64K, 63M) - U-Boot proper pre-reloc malloc heap
After U-Boot proper has relocated to top of memory we should be able to
use 2M+ for loading kernel, initrd, scripts etc.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The Pine64 PineTab2 is a tablet computer based on the Rockchip RK3566
SoC. The table features 4/8 GB LPDDR4 RAM and 64/128 GB eMMC storage.
Features tested on a Pine64 PineTab2 8GB v2.0:
- SD-card boot
- eMMC boot
- SPI Flash boot
- USB host
Device tree is imported from linux maintainer branch v6.9-armsoc/dts64,
commit 1b7e19448f8f ("arm64: dts: rockchip: Add devicetree for Pine64
PineTab2").
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add a minimal generic RK3588S/RK3588 board that only have eMMC and SDMMC
enabled. This defconfig can be used to boot from eMMC or SD-card on most
RK3588S/RK3588 boards that follow reference board design.
Also fix the alphabetical order of RK3588 boards listed in Makefile and
documentation.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
TB-RK3588X board is a Rockchip Toybrick RK3588 based development board.
Specification:
Rockchip Rk3588 SoC
4x ARM Cortex-A76, 4x ARM Cortex-A55
8/16GB Memory LPDDR4x
Mali G610MC4 GPU
2× MIPI-CSI0 Connector
1x 2Lanes PCIe3.0 Connector
1x SATA3.0 Connector
32GB eMMC Module
2x USB 2.0, 2x USB 3.0
1x HDMI Output, 1x HDMI Input
2x Ethernet Port
Functions work normally:
[1] USB2.0 Host
[2] Ethernet0 with PHY RTL8211F
More information can be obtained from the following websites:
[1] https://t.rock-chips.com/en/wiki/EN/tb-rk3588x_en/index.html
[2] http://t.rock-chips.com/
Kernel commits:
8ffe365f8dc7 ("arm64: dts: rockchip: Add devicetree support for TB-RK3588X board")
7140387ff49d ("dt-bindings: arm: rockchip: Add Toybrick TB-RK3588X")
Reviewed-by: Weizhao Ouyang <weizhao.ouyang@arm.com>
Signed-off-by: Elon Zhang <zhangzj@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
FIT checksum validation is very slow in SPL due to D-cache not being
enabled.
Enable caches in SPL on ARM64 SoCs to speed up FIT checksum validation,
from seconds to milliseconds.
This change enables caches in SPL on all Rockchip ARM64 boards, the
Kconfig options SPL_SYS_ICACHE_OFF and SPL_SYS_DCACHE_OFF can be used to
disable caches for a specific board or SoC if needed.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Cool Pi CM5 EVB works as a mother board connect with CM5.
CM5 Specification:
- Rockchip RK3588
- LPDDR4 2/4/8/16 GB
- TF scard slot
- eMMC 8/32/64/128 GB module
- SPI Nor 8MB
- Gigabit ethernet x 1 with PHY YT8531
- Gigabit ethernet x 1 drived by PCIE with YT6801S
CM5 EVB Specification:
- HDMI Type A out x 2
- HDMI Type D in x 1
- USB 2.0 Host x 2
- USB 3.0 OTG x 1
- USB 3.0 Host x 1
- PCIE M.2 E Key for Wireless connection
- PCIE M.2 M Key for NVME connection
- 40 pin header
The dts is from linux-6.8 rc1.
Signed-off-by: Andy Yan <andyshrk@163.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
[0]https://patchwork.kernel.org/project/linux-rockchip/patch/2450634.jE0xQCEvom@phil/
CoolPi 4B is a rk3588s based SBC.
Specification:
- Rockchip RK3588S
- LPDDR4 2/4/8/16 GB
- TF scard slot
- eMMC 8/32/64/128 GB module
- SPI Nor 8MB
- Gigabit ethernet drived by PCIE with RTL8111HS
- HDMI Type D out
- Mini DP out
- USB 2.0 Host x 2
- USB 3.0 OTG x 1
- USB 3.0 Host x 1
- WIFI/BT module AIC8800
- 40 pin header
The dts is from linux-6.8 rc1.
Signed-off-by: Andy Yan <andyshrk@163.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
[0]https://patchwork.kernel.org/project/linux-rockchip/patch/2450634.jE0xQCEvom@phil/
The rockchip-efuse driver supports the efuse found on RK3399. This
hardware block is part of the SoC and contains the CPUID, which can
be used to generate stable serial numbers and MAC addresses.
Enable the driver and reading cpuid by default for RK3399.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Christopher Obbard <chris.obbard@collabora.com>
Reviewed-by: Dragan Simic <dsimic@manjaro.org>
The rockchip-efuse driver supports the efuse found on RK3328. This
hardware block is part of the SoC and contains the CPUID, which can
be used to generate stable serial numbers and MAC addresses.
Enable the driver and reading cpuid by default for RK3328.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Christopher Obbard <chris.obbard@collabora.com>
Reviewed-by: Dragan Simic <dsimic@manjaro.org>
Add Kconfig options to enable support for booting from SPI NOR flash on
Orange Pi R1 Plus boards.
The generated bootable u-boot-rockchip-spi.bin can be written to 0x0 of
SPI NOR flash. The FIT image is loaded from 0x60000, same as on RK35xx
boards.
=> sf probe
SF: Detected zb25vq128 with page size 256 Bytes, erase size 4 KiB, total 16 MiB
=> load mmc 1:1 10000000 u-boot-rockchip-spi.bin
1376768 bytes read in 66 ms (19.9 MiB/s)
=> sf update ${fileaddr} 0 ${filesize}
device 0 offset 0x0, size 0x150200
1126912 bytes written, 249856 bytes skipped in 14.22s, speed 100542 B/s
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Tianling Shen <cnsztl@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add Kconfig options to enable support for booting from SPI NOR flash on
Pine64 Rock64.
The generated bootable u-boot-rockchip-spi.bin can be written to 0x0 of
SPI NOR flash. The FIT image is loaded from 0x60000, same as on RK35xx
boards.
=> sf probe
SF: Detected gd25q128 with page size 256 Bytes, erase size 4 KiB, total 16 MiB
=> load mmc 1:1 10000000 u-boot-rockchip-spi.bin
1359872 bytes read in 65 ms (20 MiB/s)
=> sf update ${fileaddr} 0 ${filesize}
device 0 offset 0x0, size 0x14c000
1118208 bytes written, 241664 bytes skipped in 8.516s, speed 163516 B/s
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Dragan Simic <dsimic@manjaro.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Similar to RK35xx the BootRom in RK3328 can read all data and look for
idbloader at 0x8000, same as it does for SD and eMMC.
Use the rksd format and modify the mkimage offset to generate a bootable
u-boot-rockchip-spi.bin that can be written to 0x0 of SPI NOR flash.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This reverts commit 3523c07867b403d5b3b68812aebac8a5afa5be4c.
Booting from SPI was already allowed before this commit was first
introduced. A few lines further down the exact same code already existed
and still does.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Replace the rockchip,cryptov1-rng compatible with compatibles used in
the linux device tree for RK3288, RK3328 and RK3399 to ease sync of SoC
device tree from linux.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
When RK3328 boards run SPL from eMMC and fail to load FIT from eMMC due
to it being missing or checksum validation fails there is a fallback to
read FIT from SD-card. However, without proper pinctrl configuration
reading FIT from SD-card will fail:
U-Boot SPL 2024.04-rc1 (Feb 05 2024 - 22:18:22 +0000)
Trying to boot from MMC1
mmc_load_image_raw_sector: mmc block read error
Trying to boot from MMC2
Card did not respond to voltage select! : -110
spl: mmc init failed with error: -95
Trying to boot from MMC1
mmc_load_image_raw_sector: mmc block read error
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###
Fix this by tagging related emmc and sdmmc pinctrl nodes with bootph
props. Also sort and move common nodes shared by all boards to the SoC
u-boot.dtsi.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Update defconfig for rk3328-orangepi-r1-plus boards with new defaults.
Remove the SPL_DRIVERS_MISC=y option, no misc driver is used in SPL.
Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash
of FIT images. This help indicate if there is an issue loading any of
the images to DRAM or SRAM. Also add LEGACY_IMAGE_FORMAT=y to keep
support for scripts.
Remove SPL_I2C=y and SPL_PMIC_RK8XX=y, the related i2c and pmic nodes is
not included in the SPL fdt.
Add CMD_GPIO=y and CMD_REGULATOR=y to add the helpful gpio and regulator
commands.
Add ROCKCHIP_EFUSE=y and remove NET_RANDOM_ETHADDR=y, ethaddr and
eth1addr is set based on cpuid read from eFUSE.
Add SPL_DM_SEQ_ALIAS=y option to use alias sequence number in SPL.
Add DM_ETH_PHY=y, PHY_GIGE=y, PHY_MOTORCOMM=y, PHY_REALTEK=y and remove
&gmac2io to support reset of onboard ethernet PHYs. Also add DM_MDIO=y
to ensure device tree props is used by motorcomm PHY driver.
Add PHY_ROCKCHIP_INNO_USB2=y option to support the onboard USB PHY.
Remove REGULATOR_PWM=y, the pwm-regulator compatible is not used.
Add RNG_ROCKCHIP=y and DM_RNG=y options to support the onboard random
generator.
Also add missing device tree files to MAINTAINERS file.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Tianling Shen <cnsztl@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
