Add a basic software implementation of the ARM64 pagetable walker. This
can be used for debugging U-Boot's pagetable, as well as dumping the
pagetable from the previous bootloader stage if it used one (by reading
out the ttbr address).
One can either call dump_pagetable() to print the pagetable to the
console with the default formatter, or implement their own pagetable
handler using walke_pagetable() with a custom pte_walker_cb_t callback.
All of the added code is discarded when unused, hence there is no need
to add an additional Kconfig option for this.
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
The APTable attribute is two bits wide according to the ARMv8-A
architecture reference manual. Fix the macro accordingly.
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/21310
- Enable SPL DTO application support for i.MX8MP DHCOM PDK2.
- Migrate imx8mn_bsh_smm_s2 and imx6ulz_bsh_smm_m2 to OF_UPSTREAM.
- Drop redundant imports with dts/upstream.
- Miscellaneous improvements for Gateworks i.MX8M boards.
Enable Quality of Service (QoS) blocks for Display SubSystem (DSS), by
servicing the DSS - DDR traffic from the Real-Time (RT) queue. This is
done by setting the DSS DMA orderID to greater than 9.
Before setting up the QoS, the ORDERID needs to be mapped to VBUSM sources
using setup_navss_nb() function call that sets the threadmap for NBSS
registers. (Section 10.2.9.2.10 "Quality of Service" in TRM[0])
Section 3.2.1 "Quality of Service (QoS)" in the TRM[0] provide more
details.
[0]: https://www.ti.com/lit/zip/spruj52
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Enable Quality of Service (QoS) blocks for Display SubSystem (DSS), by
servicing the DSS - DDR traffic from the Real-Time (RT) queue. This is
done by setting the DSS DMA orderID to greater than 9.
Before setting up the QoS, the ORDERID needs to be mapped to VBUSM sources
using setup_navss_nb() function call that sets the threadmap for NBSS
registers. (Section 10.2.9.2.10 "Quality of Service" in TRM[0])
Section 3.2.1 "Quality of Service (QoS)" in the TRM[0] provide more
details.
[0]: https://www.ti.com/lit/zip/spruj28
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Enable Quality of Service (QoS) blocks for Display SubSystem (DSS), by
servicing the DSS - DDR traffic from the Real-Time (RT) queue. This is
done by setting the DSS DMA orderID to greater than 7.
Before setting up the QoS, the ORDERID needs to be mapped to VBUSM sources
using setup_navss_nb() function call that sets the threadmap for NBSS
registers. (Section 10.2.10.1.2 "NB Parameters" in TRM[0])
Section 3.3.2 "Quality of Service (QoS)" in the TRM[0] provide more
details.
[0]: https://www.ti.com/lit/zip/spruil1
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>
For the QOS registers, instead of using the raw values for calculation
for each reg field, use a defined macro which takes in argument for all
the reg fields to get the desired value.
Do the similar simplification for QOS register and group registers and
make the corresponding changes for am62a_qos_uboot file.
Suggested-by: Andrew Davis <afd@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Acked-by: Andrew Davis <afd@ti.com>
QoS bit mapping are common across all K3 SoCs so move those defines
to common header file (k3_qos.h).
This ensures that we do not define these for each SoC.
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
The assigned-clock no longer have to be dropped, the clock are now
defined in clk-imx8mp.c and used by DWMAC driver to configure the
DWMAC clock. Drop the workarounds from U-Boot specific DT extras.
Having the clocks dropped causes the EQoS to be non-functional.
See commit c7ea9612df0f ("arm64: dts: imx8mp: Drop EQoS clock
workaround").
Fixes: 48c6f9777cee ("board: gateworks: venice: add imx8mp-gw7905-2x support")
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
The GW74xx USB1 controller connects to a dual-role connector using a GPIO
for role detection via the usb-connector Linux driver (usb-conn-gpio.c).
This drive does not exist yet in U-Boot so for now we will just default
USB1 to host mode.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Migrate imx8mn_bsh_smm_s2 and imx8mn_bsh_smm_s2pro boards to OF_UPSTREAM.
Signed-off-by: Patrick Barsanti <patrick.barsanti@amarulasolutions.com>
Tested-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Add the secondary cores nodes in the dts file
Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Rui Miguel Silva <rui.silva@linaro.org>
In EFI sub-system we rely on invalidate_icache_all() to invalidate the
instruction cache after loading binaries. Add the missing implementation on
ARM1136, ARM1176.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Jayesh Choudhary <j-choudhary@ti.com> says:
Hello there,
This series add the U-Boot support for our new platform of K3-SOC
family - J722S-EVM which is a superset of AM62P. It shares the same
memory map and thus the nodes are being reused from AM62P includes
instead of duplicating the definitions.
Some highlights of J722S SoC (in addition to AM62P SoC features) are:
- Two Cortex-R5F for Functional Safety or general-purpose usage and
two C7x floating point vector DSP with Matrix Multiply Accelerator
for deep learning.
- Vision Processing Accelerator (VPAC) with image signal processor
and Depth and Motion Processing Accelerator (DMPAC).
- 7xUARTs, 3xSPI, 5xI2C, 2xUSB2, 2xCAN-FD, 3xMMC and SD, GPMC for
NAND/FPGA connection, OSPI memory controller, 5xMcASP for audio,
4xCSI-RX for Camera, 1 PCIe Gen3 controller, USB3.0 eCAP/eQEP,
ePWM, among other peripherals.
TRM: <https://www.ti.com/lit/zip/sprujb3>
Schematics: <https://www.ti.com/lit/zip/sprr495>
Boot test log:
<https://gist.github.com/Jayesh2000/0313e58fde377f877a9a8f1acc2579ef>
Include the uboot device tree files needed to boot the board.
Co-developed-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Introduce the basic functions and definitions needed to properly
initialize TI J722S family of SoCs.
Co-developed-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Include the clock and lpsc tree files needed for the wkup spl to
initialize the proper PLLs and power domains to boot the SoC.
Reviewed-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Include the part number for TI's j722s family of SoC
to identify it during boot.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Sort CONFIG_SOC* and K3_SOC_ID alphabetically.
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Add a fixed partitions node to the AM64x device tree so that it can
be used to fixup the Linux device tree.
Signed-off-by: Nathan Morrisson <nmorrisson@phytec.com>
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Daniel Schultz <d.schultz@phytec.de>
Add a fixed partitions node to the AM62x device tree so that it can
be used to fixup the Linux device tree.
Signed-off-by: Nathan Morrisson <nmorrisson@phytec.com>
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Daniel Schultz <d.schultz@phytec.de>
Test whether this system is compatible with STM32MP15xx DHCOM SoM,
if so, test whether R292 pull up is populated on pin PC3, which is
an indication that the second MAC chip, KS8851-16MLL, is populated.
Use this information to patch 'status' DT property into the second
ethernet MAC DT node and enable/disable the MAC on systems where
the chip is/isn't populated respectively.
Use spl_perform_fixups() to patch the U-Boot proper DT from SPL and
ft_board_setup() to patch Linux DT from U-Boot proper. This way both
software components are configured the same way.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Add generic SoM compatible string into machine compatible string
for all STM32MP15xx based DH electronics DHSOM. This way, common
board code can match on this compatible. No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
In Odyssey board, we should reset the PHY chipset, toggling G0 pin.
Signed-off-by: Heesub Shin <heesub@gmail.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
In Odyssey board, KSZ9031 is at the PHY address 0x7, not 0x0. This
commit fixes it.
Signed-off-by: Heesub Shin <heesub@gmail.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
In Odyssey board, we should use the internal clock from RCC as the
transmit clock, instead of the external clock from ETH_CLK125 pad. This
commit adds a property, st,eth-clk-sel, so that the ETH_CLK_SEL mux
selects ETH_CLK.
Signed-off-by: Heesub Shin <heesub@gmail.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Odyssey board requires ETH_CLK of 125Mhz. This commit sets PLL4_P/Q/R to
125, 62.5 and 62.5Mhz in respectively.
Signed-off-by: Heesub Shin <heesub@gmail.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
This stm32mp135f-dhcor-dhsbc board is a stack of DHCOR SoM based on
STM32MP135F SoC (900MHz / crypto capabilities) populated on DHSBC
carrier board.
The SoM contains the following peripherals:
- STPMIC (power delivery)
- 512MB DDR3L memory
- eMMC and SDIO WiFi module
The DHSBC carrier board contains the following peripherals:
- Two RGMII Ethernet ports
- USB-A Host port, USB-C peripheral port, USB-C power supply plug
- Expansion connector
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Add both ethernet MACs based on GMAC SNPS IP on stm32mp13.
Signed-off-by: Christophe Roullier <christophe.roullier@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
This patch makes STM32 PWR regulators available on stm32mp13xx.
This requires TFA to clear RCC_SECCFGR, is disabled by default
on stm32mp13xx and can only be enabled on board config level.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
This patch adds STM32 PWR regulators DT support on stm32mp131.
This requires TFA to clear RCC_SECCFGR, is disabled by default
and can only be enabled on board DT level.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Since commit 7b78d6438a2b3 ("efi_loader: Reserve unaccessible memory")
memory region above ram_top is tagged in EFI memory map as
EFI_BOOT_SERVICES_DATA.
In case of STM32MP1/STM32MP13 platforms, above ram_top, there is one
reserved-memory region tagged "no-map" dedicated to OP-TEE :
_ addr=de000000 size=2000000 for stm32mp157x-dkx and stm32mp135f-dk
_ addr=fe000000 size=2000000 for stm32mp157c-ev1
Before booting kernel, EFI memory map is first built, the OPTEE region is
tagged as EFI_BOOT_SERVICES_DATA and when reserving LMB, the tag LMB_NONE
is used.
Then after, the LMB are completed by boot_fdt_add_mem_rsv_regions()
which try to add again the same OPTEE region (addr=de000000 size=2000000
in case of stm32mp157x-dkx / stm32mp135f-dk or addr=fe000000 size=2000000
in case for stm2mp157c-ev1)
but now with LMB_NOMAP tag which produces the following error message :
_ for stm32mp157x-dkx / stm32mp135f-dk :
"ERROR: reserving fdt memory region failed (addr=de000000 size=2000000 flags=4)"
_ for stm32mp157c-ev1 :
"ERROR: reserving fdt memory region failed (addr=fe000000 size=2000000 flags=4)"
To avoid this, OPTEE area shouldn't be used by EFI, so we need to mark
it as reserved.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
common:
- spl: Introduce SoC specific init function
xilinx:
- Enable FF-A and NVMEM
- Rename spl_board_init() to spl_soc_init()
zynqmp:
- DT alignments
- Enable reset from SPL
- Enable USB3 for KD240
- Align multiboot register on Kria for proper reboot
- Allow multiboot environment write even in saved environment
- Move zynqmp commands from board/ to arch/
- Clean up xilinx_zynqmp.h
versal:
- Do not prioritize boot device if driver is not enabled
versal-net:
- Setup location for redundant variables in SPI
versal2:
- Add support for new SOC
mmc:
- Fix tap delay for SD on Versal NET
spi:
- Add SPI_NOR_OCTAL_READ flag for mx66uw2g345gx0 flash part
gpio:
- Cover MODEPIN firmware dependency
-----BEGIN PGP SIGNATURE-----
iF0EABECAB0WIQQbPNTMvXmYlBPRwx7KSWXLKUoMIQUCZnBfewAKCRDKSWXLKUoM
Ib/7AJ0cn3q7lMpxbSbRj33oftI8Vy8+owCeN35Nl8TN9l/DHbfusER4uVfnOVw=
=YMIB
-----END PGP SIGNATURE-----
Merge tag 'xilinx-for-v2024.10-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next
AMD/Xilinx changes for v2024.10-rc1
common:
- spl: Introduce SoC specific init function
xilinx:
- Enable FF-A and NVMEM
- Rename spl_board_init() to spl_soc_init()
zynqmp:
- DT alignments
- Enable reset from SPL
- Enable USB3 for KD240
- Align multiboot register on Kria for proper reboot
- Allow multiboot environment write even in saved environment
- Move zynqmp commands from board/ to arch/
- Clean up xilinx_zynqmp.h
versal:
- Do not prioritize boot device if driver is not enabled
versal-net:
- Setup location for redundant variables in SPI
versal2:
- Add support for new SOC
mmc:
- Fix tap delay for SD on Versal NET
spi:
- Add SPI_NOR_OCTAL_READ flag for mx66uw2g345gx0 flash part
gpio:
- Cover MODEPIN firmware dependency
Rename spl_board_init() to spl_soc_init(). SoC specific
implementation should be separated from board specific implementation
in order to be extended by board developers.
Signed-off-by: Lukas Funke <lukas.funke@weidmueller.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20240327121153.2455126-3-lukas.funke-oss@weidmueller.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
The zynqmp cmds.c is currently tied to the board but the commands
contained within are more closely tied to the architecture. To
allow usage of those commands when the architecture is ZynqMP but
the board is not, this change moves the cmds into the arch/ tree.
The source file is renamed to zynqmp.c to reflect the command name
as well.
Signed-off-by: Charlie Johnston <charlie.johnston@loftorbital.com>
Link: https://lore.kernel.org/r/20240410195008.405061-2-charlie.johnston@loftorbital.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Make sure the OS would not get any spurious IWDG pretimeout IRQ
right after the system wakes up. This may happen in case the SoC
got woken up by another source than the IWDG pretimeout and the
pretimeout IRQ arrived immediately afterward, but too late to be
handled by the suspend main loop. In case either of the IWDG is
enabled, ping it first and then return to the OS.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@foundries.io>
