This board is configured with CONFIG_USB1_VBUS_PIN="PH24", but no
regulator exists in its device tree. Add the regulator, so USB will
continue to work when the PHY driver switches to using the regulator
uclass instead of a GPIO.
Update the device tree here because it does not exist in Linux.
Signed-off-by: Samuel Holland <samuel@sholland.org>
This is now handled automatically by the pinctrl driver.
Cover-letter:
sunxi: Add and use a pinctrl driver
This series resolves some longstanding TODOs by implementing a pinctrl
driver for sunxi platforms and converting DM drivers to use it.
I am sending this as RFC because I have only tested this on a limited
amount of hardware, and there are quite a few magic numbers involved,
so it is likely I missed something. Also, I'm not sure the how best to
split up the patches by subsystem, or if that is necessary.
This series depends on the sunxi-gpio series I just sent.
END
Series-to: sunxi
Series-to: sjg
Series-prefix: RFC
Signed-off-by: Samuel Holland <samuel@sholland.org>
When the DM_I2C driver is loaded, the pin setup is done automatically
from the device tree by the pinctrl driver.
Clean up the code in the process: remove #ifdefs and recognize that the
pin configuration is the same for all sun8i/sun50i SoCs, not just those
which select CONFIG_MACH_SUN8I.
Signed-off-by: Samuel Holland <samuel@sholland.org>
When the DM_I2C driver is loaded, the pin setup is done automatically
from the device tree by the pinctrl driver.
Signed-off-by: Samuel Holland <samuel@sholland.org>
This is now handled automatically by the clock and pinctrl drivers.
SPL still calls this function because it needes the non-DM code.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Where multiple options were available, the one matching board.c and the
device trees was chosen.
Pin lists and mux values were taken from the Linux drivers.
Signed-off-by: Samuel Holland <samuel@sholland.org>
When a pinctrl driver is available, it will take care of setting up
these pins. However, for now this code is still needed in SPL.
Signed-off-by: Samuel Holland <samuel@sholland.org>
This includes UART0 and R_UART (s_uart) on all supported platforms, plus
the additional UART configurations from arch/arm/mach-sunxi/board.c.
Pin lists and mux values were taken from the Linux drivers.
Signed-off-by: Samuel Holland <samuel@sholland.org>
The sunxi pinctrl hardware has bias and drive control. Add driver
support for configuring those options.
Signed-off-by: Samuel Holland <samuel@sholland.org>
The pinmux command uses this function to display pinmux status.
Since the driver cannot map pin numbers to a list of supported
functions, only functions which are common across all pins can be
reported by name.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Implement the operations to get pin and function names, and to set the
mux for a pin. The pin count and pin names are calculated as if each
bank has the maximum number of pins. Function names are simply the index
into a list of { function name, mux value } pairs.
We assume all pins associated with a function use the same mux value for
that function. This is generally true within a group of pins on a single
port, but generally false when some peripheral can be muxed to multiple
ports. For example, A64 UART3 uses mux 3 on port D, and mux 2 on port H.
But all of the port D pins use the same mux value, and so do all of the
port H pins. This applies even when the pins for some function are not
contiguous, and when the lower-numbered mux values are unused. A good
example of both of these cases is SPI0 on most SoCs.
This strategy saves a lot of space (which is especially important for
SPL), but where the mux value for a certain function differs across
ports, it forces us to choose a single port for that function at build
time. Since almost all boards use the default (i.e. reference design)
pin muxes[1], this is unlikely to be a problem.
[1]: See commit dda9fa734f81 ("sunxi: Simplify MMC pinmux selection")
Signed-off-by: Samuel Holland <samuel@sholland.org>
Create a do-nothing driver for each sunxi pin controller variant.
Since only one driver can automatically bind to a DT node, since the
GPIO driver already requires a manual binding process, and since the
pinctrl driver needs access to some of the same information, refactor
the GPIO driver to be bound by the pinctrl driver. This commit should
cause no functional change.
Signed-off-by: Samuel Holland <samuel@sholland.org>
This adds a new PSCI implementation which communicates with SCP firmware
running on the AR100 using the SCPI protocol. This allows it to support
the full set of PSCI v1.1 features, including CPU idle states, system
suspend, and multiple reset methods.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Add the new option, function IDs, and prototypes for PSCI v1.1
implementations. In the process, fix some issues with the existing
definitions:
- Fix the incorrectly-named ARM_PSCI_0_2_FN64_SYSTEM_RESET2.
- Replace the deprecated "affinity_level" naming with "power_level".
Signed-off-by: Samuel Holland <samuel@sholland.org>
Now that issues with the BROM have been sorted out, we can implement
PSCI system suspend on H3 by delegating to SCP firmware. Let's start by
including the firmware in the FIT image and starting the coprocessor if
valid firmware is loaded.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Due to a bug in the H3 SoC, where the CPU 0 hotplug flag cannot be
written, resuming CPU 0 requires using the "Super Standby" code path in
the BROM instead of the hotplug path. This path requires jumping to an
eGON image in SRAM.
Add support to the build system to generate this eGON image and include
it in the FIT, and add code to direct the BROM to its location in SRAM.
Since the Super Standby code path in the BROM initializes the CPU and
AHB1 clocks to 24 MHz, those registers need to be restored after control
passes back to U-Boot. Furthermore, because the BROM lowers the AHB1
clock divider to /1 before switching to the lower-frequency parent,
PLL_PERIPH0 must be bypassed to prevent AHB1 from temporarily running at
600 MHz. Otherwise, this locks up the SoC.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Do not try to send an SGI from CPU 0 to itself. Since FIQs are masked
when entering monitor mode, this will hang. Plus, CPU 0 cannot fully
power itself off anyway. Instead, have it turn FIQs back on and continue
servicing SGIs from other cores.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Now that the sunxi_gpio driver handles pull-up/down via the driver
model, pin configuration does not need a platform-specific function.
Series-to: sunxi
Cover-letter:
gpio: sunxi: Handle pin configuration flags
This series updates the sunxi GPIO driver to handle pin pull-up/down,
so consumer drivers do not need to call the non-DM sunxi_gpio_set_*
functions. As an example, the last patch updates the MMC driver to use
this functionality. The helpers added here will also be used for the
upcoming DM_PINCTRL driver.
END
Signed-off-by: Samuel Holland <samuel@sholland.org>
This, along with gpio_flags_xlate(), allows the GPIO driver to handle
pull-up/down flags provided by consumer drivers or in the device tree.
Signed-off-by: Samuel Holland <samuel@sholland.org>
The GPIO and pinctrl drivers need these setters for pin configuration.
Since they are DM drivers, they should not be using hardcoded base
addresses. Factor out variants of the setter functions which take a
pointer to the GPIO bank's MMIO registers.
Signed-off-by: Samuel Holland <samuel@sholland.org>
The return values of these functions are always zero, and they are
never checked. Since they are not needed, remove them.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Due to a bug in the H3 SoC, where the CPU 0 hotplug flag cannot be
written, resuming CPU 0 requires using the "Super Standby" code path in
the BROM instead of the hotplug path. This path requires jumping to an
eGON image in SRAM.
This resume image, whose single purpose is to jump back to the secure
monitor, only needs to contain a single instruction. Padding the image
to 8 KiB would be wasteful of SRAM. Hook up the -B (block size) option
so users can set the block/padding size.
Series-to: sunxi
Signed-off-by: Samuel Holland <samuel@sholland.org>
Now that Crust (SCP firmware) has support for H3, we need a FIT image to
load it. H3 also needs to load a SoC-specific eGon blob to support CPU 0
hotplug. Let's first enable FIT support before adding extra firmware.
Update the binman description to work on either 32-bit or 64-bit SoCs:
- Make BL31 optional, since it is not used on 32-bit SoCs (though BL32
may be used in the future).
- Explicitly set the minimum offset of the FIT to 32 KiB, since SPL on
some boards is still only 24 KiB large even with FIT support enabled.
CONFIG_SPL_PAD_TO cannot be used because it is not defined for H616.
FIT unlocks more features (signatures, multiple DTBs, etc.), so enable
it by default. A10 (sun4i) only has 24 KiB of SRAM A1, so it needs
SPL_FIT_IMAGE_TINY. For simplicity, enable that option everywhere.
Cover-letter:
sunxi: SPL FIT support for 32-bit sunxi SoCs
This series makes the necessary changes so 32-bit sunxi SoCs can load
additional device trees or firmware from SPL along with U-Boot proper.
There was no existing binman entry property that put the FIT at the
right offset. The minimum offset is 32k, but this matches neither the
SPL size (which is no more than 24k on some SoCs) nor the FIT alignment
(which is 512 bytes in practice due to SPL size constraints). So instead
of adding a new property, I fixed what is arguably a bug in the offset
property -- though this strategy will not work if someone is
intentionally creating overlapping entries.
END
Series-to: sunxi
Series-to: sjg
Signed-off-by: Samuel Holland <samuel@sholland.org>
Currently, if the "offset" property is given for an entry, the section's
running offset is completely ignored. This causes entries to overlap if
the provided offset is less than the size of the entries earlier in the
section. Avoid the overlap by only using the provided offset when it is
greater than the running offset.
The motivation for this change is the rule used by SPL to find U-Boot on
sunxi boards: U-Boot starts 32 KiB after the start of SPL, unless SPL is
larger than 32 KiB, in which case U-Boot immediately follows SPL.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Copy the devicetree source for the H6 SoC and all existing boards
verbatim from the Linux v5.15 tag.
This update should not impact any existing U-Boot functionality.
Series-to: sunxi
Cover-letter:
sunxi: Devicetree sync from Linux v5.15
This series brings all of our devicetrees up to date with the latest
stable Linux version.
<< something about ABI compat >>
Here is the list of new files which were not added by this sync:
- sun4i-a10-topwise-a721.dts
- sun50i-a100-allwinner-perf1.dts
- sun50i-a100.dtsi
- sun50i-h6-pine-h64-model-b.dts
- sun5i-a13-licheepi-one.dts
- sun5i-a13-pocketbook-touch-lux-3.dts
- sun5i-gr8-evb.dts
- sun7i-a20-linutronix-testbox-v2.dts
- sun7i-a20-olinuxino-lime-emmc.dts
- sun8i-a23-ippo-q8h-v1.2.dts
- sun8i-a23-ippo-q8h-v5.dts
- sun8i-a33-et-q8-v1.6.dts
- sun8i-a33-ippo-q8h-v1.2.dts
- sun8i-h3-nanopi-r1.dts
- sun8i-r16-nintendo-nes-classic.dts
- sun8i-r16-nintendo-super-nes-classic.dts
- sun8i-r40-feta40i.dtsi
- sun8i-r40-oka40i-c.dts
- sun8i-s3-elimo-impetus.dtsi
- sun8i-s3-elimo-initium.dts
- sun8i-t3-cqa3t-bv3.dts
- sun8i-v3-sl631-imx179.dts
- sun8i-v3-sl631.dtsi
END
Signed-off-by: Samuel Holland <samuel@sholland.org>
Copy the devicetree source for the H5 SoC and all existing boards
from the Linux v5.15 tag, with minor changes to account for the
different directory layout for 64-bit SoCs.
While there were some recent changes to the shared H3/H5 devicetree,
the only H5-specific change is fixing the EMAC phy-mode in one board.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Copy the devicetree source for the A64 SoC and all existing boards
verbatim from the Linux v5.15 tag.
As with the other SoCs, updates of note are EMAC phy-mode changes to set
RGMII delays.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Copy the devicetree for the R40 SoC verbatim from the Linux v5.15 tag.
None of the existing boards had any devicetree updates.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Copy the devicetree source for the V3(s)/S3 SoCs and all existing boards
verbatim from the Linux v5.15 tag.
This update should not impact any existing U-Boot functionality.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Copy the devicetree source for the H2+/H3 SoCs and all existing boards
verbatim from the Linux v5.15 tag.
As with the other SoCs, updates of note are EMAC phy-mode changes to set
RGMII delays.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Copy the devicetree source for the A83T SoC and all existing boards
verbatim from the Linux v5.15 tag.
As with the other SoCs, updates of note are EMAC phy-mode changes to set
RGMII delays, and adding detection GPIO properties in the USB PHY nodes.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Copy the devicetree source for the A80 SoC and all existing boards
verbatim from the Linux v5.15 tag.
This update should not impact any existing U-Boot functionality.
Signed-off-by: Samuel Holland <samuel@sholland.org>
