We tried to enable USB_EHCI_GENERIC and USB_OHCI_GENERIC by default.
This did not work because those symbols depend on USB_EHCI_HCD and
USB_OHCI_HCD, which were not enabled. Fix this by implying all four.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Implement the .get_function operation, so the gpio command can report
the current function. Since the GPIOF_FUNC (versus GPIOF_UNUSED) mux
values vary among the PMICs, report all non-GPIO mux values as UNKNOWN.
Signed-off-by: Samuel Holland <samuel@sholland.org>
There are three major variants of the AXP PMIC GPIO functionality (plus
PMICs with no GPIOs at all). Except for GPIO3 on the AXP209, which uses
a different register layout, it is straightforward to support all three
variants with a single driver. Do this, and in the process remove the
GPIO-related definitions from the PMIC-specific headers, and therefore
the dependency on AXP_PMIC_BUS.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Now that the PMIC driver implements the DM_PMIC uclass, those functions
can be used instead of the platform-specific "pmic_bus" functions.
Since the driver still uses the single set of register definitions from
axpXXX.h (as selected by AXPxxx_POWER), it still depends on one of those
choices, and therefore also AXP_PMIC_BUS.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Now that the PMIC has a DM driver and binds device tree subnodes, the
GPIO device can be bound that way, instead of from inside board code.
Since the driver still uses the single set of register definitions from
axpXXX.h (as selected by AXPxxx_POWER), it does not differentiate among
the supported compatibles.
Signed-off-by: Samuel Holland <samuel@sholland.org>
This is less confusing than half of the driver using "axp_gpio" and the
other half using "gpio_axp".
Signed-off-by: Samuel Holland <samuel@sholland.org>
Now that the sunxi_gpio driver handles pull-up/down via the driver
model, we can switch to DM_GPIO for these pins with no loss in
functionality. Since the driver now gets its pin configuration from
the device tree, we can remove the Kconfig symbols.
Signed-off-by: Samuel Holland <samuel@sholland.org>
The struct is only used to overlay the MMIO region, so the behavior is
the same. This obsoletes the Kconfig option for the number of ports.
Series-to: Marek Vasut <marex@denx.de> (maintainer:USB)
Series-to: u-boot@lists.denx.de (open list)
Signed-off-by: Samuel Holland <samuel@sholland.org>
With one exception (sun9i), all sunxi SoCs released to date use variants
of the same USB PHY. Instead of requiring each new SoC to duplicate the
PHY driver selection, enable it by default.
Series-to: Andre Przywara <andre.przywara@arm.com>
Series-to: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
This more closely matches the U-Boot driver to the Linux version.
Series-to: sunxi
Cover-letter:
mtd: nand: sunxi: Convert to devicetree and the driver model
This series converts the sunxi NAND driver to get its resources (clocks,
resets, pins) from the devicetree, and probe using the driver model.
In addition to the immediate cleanup, this allows backporting more
patches (bugfixes, newer SoC support) from the Linux driver.
END
Signed-off-by: Samuel Holland <samuel@sholland.org>
It is possible to use host-side USB with externally-provided VBUS. For
example, some USB OTG cables have an extra power input which powers
both the board and the USB peripheral.
To support this setup, skip enabling the VBUS switch/regulator if VBUS
voltage is already present. This behavior matches the Linux PHY driver.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Clocks, resets, and pinmuxes are now handled by the driver model, so the
only thing the "board" code needs to do is load the driver. This matches
the pattern used by other DM raw NAND drivers (there is no NAND uclass).
The actual board code is now only needed in SPL.
Signed-off-by: Samuel Holland <samuel@sholland.org>
As a first step toward converting this driver to the driver model, use
the ofnode abstraction to replace direct references to the FDT blob.
Using ofnode_read_u32_index removes an extra pair of loops and makes the
allwinner,rb property optional, matching the devicetree binding.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Each chip is required to have a unique CS number ("reg" property) in the
range 0-7, so there is no need to separately count the number of chips.
Signed-off-by: Samuel Holland <samuel@sholland.org>
NAND is always at function 2 on port C.
Pin lists and mux values were taken from the Linux drivers.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Currently NAND clock setup is done in board code, both in SPL and in
U-Boot proper. Add the NAND clocks/resets here so they can be used by
the "full" NAND driver once it is converted to the driver model.
The bit locations are copied from the Linux CCU drivers.
Signed-off-by: Samuel Holland <samuel@sholland.org>
reg must contain enough cells for the entire next address/size pair
after skipping `index` pairs. The previous code allows an out-of-bounds
read when na + ns > 1.
Series-to: Simon Glass <sjg@chromium.org>
Fixes: 69b41388ba45 ("dm: core: Add a new api to get indexed device address")
Signed-off-by: Samuel Holland <samuel@sholland.org>
The MMC controller driver is (and ought to be) the only user of these
register definitions. Put them in a header next to the driver to remove
the dependency on a specific ARM platform's headers.
Due to the sunxi_mmc_init() prototype, the file was not renamed. None of
the register definitions were changed.
Signed-off-by: Samuel Holland <samuel@sholland.org>
As the SPL code for sunxi boards does not use the driver model, we have
two mmc_ops structures, one for DM, one for non-DM. The actual hardware
access code is shared, with the respective callback functions using that
common code.
To make this more obvious and easier to read, reorder the functions to
group them: we first have the common code, then the non-DM bits, and
the proper DM implementation at the end.
Also document this structure in the comment at the beginning of the file.
No functional change intended.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The sunxi MMC code does not use the DM in the SPL, as we don't have a
device tree available that early, also no space for it.
This also means we cannot access the card-detect GPIO information from
there, so we have Kconfig symbols called CONFIG_MMCx_CD_PIN, which each
board has to define. This is a burden, also requires extra GPIO code in
the SPL.
As the SPL is the natural successor of the BootROM (from which we are
loaded), we can actually ignore the CD pin completely, as this is what
the BootROM does as well: CD GPIOs are board specific, but the BootROM
is not, so accesses the MMC devices anyway.
Remove the card detect code from the non-DM implementation of the sunxi
MMC driver, to get rid of this unneeded code.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
While R40 puts the EMAC syscon register at a different address from
other variants, the relevant portion of the register's layout is the
same. Factor out the register offset so the same code can be shared
by all variants. This matches what the Linux driver does.
This change provides two benefits beyond the simplification:
- R40 boards now respect the RX delays from the devicetree
- This resolves a warning on architectures where readl/writel
expect the address to have a pointer type, not phys_addr_t.
Series-to: sunxi
Cover-letter:
net: sun8i-emac: Allwinner D1 Support
D1 is a RISC-V SoC containing an EMAC compatible with the A64 EMAC.
However, there are a couple of issues with the driver preventing it
being built for RISC-V. These are resolved by patches 2-3. Patch 1 is
a general cleanup.
END
Signed-off-by: Samuel Holland <samuel@sholland.org>
