Merge branch 'patch/usb-fam' into allwinner

# Conflicts:
#	drivers/phy/allwinner/Kconfig

.azure-pipelines.yml

@@ -2,7 +2,7 @@ variables:
   windows_vm: windows-2019
   ubuntu_vm: ubuntu-22.04
   macos_vm: macOS-12
-  ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20221130-11Jan2023
+  ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20221003-17Oct2022
   # Add '-u 0' options for Azure pipelines, otherwise we get "permission
   # denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer",
   # since our $(ci_runner_image) user is not root.
@@ -30,7 +30,7 @@ stages:
           %CD:~0,2%\msys64\usr\bin\bash -lc "pacman --noconfirm --needed -Sy make gcc bison flex diffutils openssl-devel libgnutls-devel libutil-linux-devel"
         displayName: 'Install Toolchain'
       - script: |
-          echo make tools-only_defconfig tools-only > build-tools.sh
+          echo make tools-only_defconfig tools-only NO_SDL=1 > build-tools.sh
           %CD:~0,2%\msys64\usr\bin\bash -lc "bash build-tools.sh"
         displayName: 'Build Host Tools'
         env:
@@ -47,24 +47,43 @@ stages:
       - script: brew install make ossp-uuid
         displayName: Brew install dependencies
       - script: |
-          gmake tools-only_config tools-only \
+          gmake tools-only_config tools-only NO_SDL=1 \
             HOSTCFLAGS="-I/usr/local/opt/openssl@1.1/include" \
             HOSTLDFLAGS="-L/usr/local/opt/openssl@1.1/lib" \
             -j$(sysctl -n hw.logicalcpu)
         displayName: 'Perform tools-only build'
 
-  - job: check_for_new_CONFIG_symbols_outside_Kconfig
+  - job: check_for_migrated_symbols_in_board_header
-    displayName: 'Check for new CONFIG symbols outside Kconfig'
+    displayName: 'Check for migrated symbols in board header'
     pool:
       vmImage: $(ubuntu_vm)
     container:
       image: $(ci_runner_image)
       options: $(container_option)
     steps:
-      # If grep succeeds and finds a match the test fails as we should
+      - script: |
-      # have no matches.
+          KSYMLST=`mktemp`
-      - script: git grep -E '^#[[:blank:]]*(define|undef)[[:blank:]]*CONFIG_'
+          KUSEDLST=`mktemp`
-                  include/configs `find arch -name config.h` && exit 1 || exit 0
+          RET=0
+          cat `find . -name "Kconfig*"` | \
+             sed -n -e 's/^\s*config *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p' \
+             -e 's/^\s*menuconfig *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p' \
+             | sort -u > $KSYMLST
+          for CFG in `find include/configs -name "*.h"`; do
+             (grep '#define[[:blank:]]CONFIG_' $CFG | \
+                sed -n 's/#define.\(CONFIG_[A-Za-z0-9_]*\).*/\1/p' ; \
+                grep '#undef[[:blank:]]CONFIG_' $CFG | \
+                sed -n 's/#undef.\(CONFIG_[A-Za-z0-9_]*\).*/\1/p') | \
+                sort -u > ${KUSEDLST} || true
+             NUM=`comm -123 --total --output-delimiter=, ${KSYMLST} ${KUSEDLST} | \
+                cut -d , -f 3`
+             if [[ $NUM -ne 0 ]]; then
+                echo "Unmigrated symbols found in $CFG:"
+                comm -12 ${KSYMLST} ${KUSEDLST}
+                RET=1
+             fi
+          done
+          exit $RET
 
   - job: cppcheck
     displayName: 'Static code analysis with cppcheck'
@@ -76,8 +95,8 @@ stages:
     steps:
       - script: cppcheck -j$(nproc) --force --quiet --inline-suppr .
 
-  - job: docs
+  - job: htmldocs
-    displayName: 'Build documentation'
+    displayName: 'Build HTML documentation'
     pool:
       vmImage: $(ubuntu_vm)
     container:
@@ -89,7 +108,6 @@ stages:
           . /tmp/venvhtml/bin/activate
           pip install -r doc/sphinx/requirements.txt
           make htmldocs
-          make infodocs
 
   - job: todo
     displayName: 'Search for TODO within source tree'
@@ -186,7 +204,7 @@ stages:
       options: $(container_option)
     steps:
       - script: |
-          export PATH=/opt/gcc-12.2.0-nolibc/arm-linux-gnueabi/bin:$PATH
+          export PATH=/opt/gcc-11.1.0-nolibc/arm-linux-gnueabi/bin:$PATH
           test/nokia_rx51_test.sh
 
   - job: pylint
@@ -224,7 +242,7 @@ stages:
           TEST_PY_BD: "sandbox"
         sandbox_clang:
           TEST_PY_BD: "sandbox"
-          OVERRIDE: "-O clang-14"
+          OVERRIDE: "-O clang-13"
         sandbox_nolto:
           TEST_PY_BD: "sandbox"
           BUILD_ENV: "NO_LTO=1"
@@ -344,7 +362,6 @@ stages:
           cat << "EOF" >> test.sh
           # the below corresponds to .gitlab-ci.yml "before_script"
           cd ${WORK_DIR}
-          git config --global --add safe.directory ${WORK_DIR}
           git clone --depth=1 https://source.denx.de/u-boot/u-boot-test-hooks /tmp/uboot-test-hooks
           ln -s travis-ci /tmp/uboot-test-hooks/bin/`hostname`
           ln -s travis-ci /tmp/uboot-test-hooks/py/`hostname`
@@ -429,8 +446,6 @@ stages:
       matrix:
         arc_microblaze_xtensa:
           BUILDMAN: "arc microblaze xtensa"
-        amlogic:
-          BUILDMAN: "amlogic"
         arm11_arm7_arm920t_arm946es:
           BUILDMAN: "arm11 arm7 arm920t arm946es"
         arm926ejs:
@@ -460,9 +475,9 @@ stages:
         imx6:
           BUILDMAN: "mx6 -x boundary,engicam,freescale,technexion,toradex"
         imx:
-          BUILDMAN: "mx -x mx6,imx8,freescale,technexion,toradex"
+          BUILDMAN: "mx -x mx6,freescale,technexion,toradex"
-        imx8_imx9:
+        imx8:
-          BUILDMAN: "imx8 imx9"
+          BUILDMAN: "imx8"
         keystone2_keystone3:
           BUILDMAN: "k2 k3"
         sandbox_asan:
@@ -470,7 +485,7 @@ stages:
           OVERRIDE: "-a ASAN"
         sandbox_clang_asan:
           BUILDMAN: "sandbox"
-          OVERRIDE: "-O clang-14 -a ASAN"
+          OVERRIDE: "-O clang-13 -a ASAN"
         samsung_socfpga:
           BUILDMAN: "samsung socfpga"
         sun4i:
@@ -516,11 +531,9 @@ stages:
         uniphier:
           BUILDMAN: "uniphier"
         aarch64_catch_all:
-          BUILDMAN: "aarch64 -x amlogic,bcm,imx8,imx9,k3,tegra,ls1,ls2,lx216,mvebu,uniphier,renesas,sunxi,samsung,socfpga,rk,versal,zynq"
+          BUILDMAN: "aarch64 -x bcm,imx8,k3,tegra,ls1,ls2,lx216,mvebu,uniphier,renesas,sunxi,samsung,socfpga,rk,versal,zynq"
-        rockchip_32bit:
+        rockchip:
-          BUILDMAN: "rk -x aarch64"
+          BUILDMAN: "rk"
-        rockchip_64bit:
-          BUILDMAN: "rk&aarch64"
         renesas:
           BUILDMAN: "renesas"
         zynq:
@@ -536,12 +549,11 @@ stages:
           cd ${WORK_DIR}
           # make environment variables available as tests are running inside a container
           export BUILDMAN="${BUILDMAN}"
-          git config --global --add safe.directory ${WORK_DIR}
           EOF
           cat << "EOF" >> build.sh
           if [[ "${BUILDMAN}" != "" ]]; then
               ret=0;
-              tools/buildman/buildman -o /tmp -PEWM ${BUILDMAN} ${OVERRIDE} || ret=$?;
+              tools/buildman/buildman -o /tmp -P -E -W ${BUILDMAN} ${OVERRIDE} || ret=$?;
               if [[ $ret -ne 0 ]]; then
                   tools/buildman/buildman -o /tmp -seP ${BUILDMAN};
                   exit $ret;

.checkpatch.conf

@@ -4,7 +4,7 @@
 # Temporary for false positive in checkpatch
 --ignore COMPLEX_MACRO
 
-# For CFG_SYS_I2C_NOPROBES
+# For CONFIG_SYS_I2C_NOPROBES
 --ignore MULTISTATEMENT_MACRO_USE_DO_WHILE
 
 # For simple_strtoul

.gitlab-ci.yml

@@ -2,7 +2,7 @@
 
 # Grab our configured image.  The source for this is found
 # in the u-boot tree at tools/docker/Dockerfile
-image: trini/u-boot-gitlab-ci-runner:jammy-20221130-11Jan2023
+image: trini/u-boot-gitlab-ci-runner:jammy-20221003-17Oct2022
 
 # We run some tests in different order, to catch some failures quicker.
 stages:
@@ -14,7 +14,6 @@ stages:
   stage: test.py
   before_script:
     # Clone uboot-test-hooks
-    - git config --global --add safe.directory "${CI_PROJECT_DIR}"
     - git clone --depth=1 https://source.denx.de/u-boot/u-boot-test-hooks /tmp/uboot-test-hooks
     - ln -s travis-ci /tmp/uboot-test-hooks/bin/`hostname`
     - ln -s travis-ci /tmp/uboot-test-hooks/py/`hostname`
@@ -82,8 +81,7 @@ build all 32bit ARM platforms:
   stage: world build
   script:
     - ret=0;
-      git config --global --add safe.directory "${CI_PROJECT_DIR}";
+      ./tools/buildman/buildman -o /tmp -P -E -W arm -x aarch64 || ret=$?;
-      ./tools/buildman/buildman -o /tmp -PEWM arm -x aarch64 || ret=$?;
       if [[ $ret -ne 0 ]]; then
         ./tools/buildman/buildman -o /tmp -seP;
         exit $ret;
@@ -95,8 +93,7 @@ build all 64bit ARM platforms:
     - virtualenv -p /usr/bin/python3 /tmp/venv
     - . /tmp/venv/bin/activate
     - ret=0;
-      git config --global --add safe.directory "${CI_PROJECT_DIR}";
+      ./tools/buildman/buildman -o /tmp -P -E -W aarch64 || ret=$?;
-      ./tools/buildman/buildman -o /tmp -PEWM aarch64 || ret=$?;
       if [[ $ret -ne 0 ]]; then
         ./tools/buildman/buildman -o /tmp -seP;
         exit $ret;
@@ -106,7 +103,6 @@ build all PowerPC platforms:
   stage: world build
   script:
     - ret=0;
-      git config --global --add safe.directory "${CI_PROJECT_DIR}";
       ./tools/buildman/buildman -o /tmp -P -E -W powerpc || ret=$?;
       if [[ $ret -ne 0 ]]; then
         ./tools/buildman/buildman -o /tmp -seP;
@@ -117,21 +113,37 @@ build all other platforms:
   stage: world build
   script:
     - ret=0;
-      git config --global --add safe.directory "${CI_PROJECT_DIR}";
+      ./tools/buildman/buildman -o /tmp -P -E -W -x arm,powerpc || ret=$?;
-      ./tools/buildman/buildman -o /tmp -PEWM -x arm,powerpc || ret=$?;
       if [[ $ret -ne 0 ]]; then
         ./tools/buildman/buildman -o /tmp -seP;
         exit $ret;
       fi;
 
-check for new CONFIG symbols outside Kconfig:
+check for migrated symbols in board header:
   stage: testsuites
   script:
-    - git config --global --add safe.directory "${CI_PROJECT_DIR}"
+    - KSYMLST=`mktemp`;
-    # If grep succeeds and finds a match the test fails as we should
+      KUSEDLST=`mktemp`;
-    # have no matches.
+      RET=0;
-    - git grep -E '^#[[:blank:]]*(define|undef)[[:blank:]]*CONFIG_'
+      cat `find . -name "Kconfig*"` |
-        include/configs `find arch -name config.h` && exit 1 || exit 0
+         sed -n -e 's/^\s*config *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p'
+         -e 's/^\s*menuconfig *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p'
+         | sort -u > $KSYMLST;
+      for CFG in `find include/configs -name "*.h"`; do
+         (grep '#define[[:blank:]]CONFIG_' $CFG |
+            sed -n 's/#define.\(CONFIG_[A-Za-z0-9_]*\).*/\1/p' ;
+            grep '#undef[[:blank:]]CONFIG_' $CFG |
+            sed -n 's/#undef.\(CONFIG_[A-Za-z0-9_]*\).*/\1/p') |
+            sort -u > ${KUSEDLST} || true;
+         NUM=`comm -123 --total --output-delimiter=, ${KSYMLST} ${KUSEDLST} |
+            cut -d , -f 3`;
+         if [[ $NUM -ne 0 ]]; then
+            echo "Unmigrated symbols found in $CFG:";
+            comm -12 ${KSYMLST} ${KUSEDLST};
+            RET=1;
+         fi;
+      done;
+      exit $RET
 
 # QA jobs for code analytics
 # static code analysis with cppcheck (we can add --enable=all later)
@@ -149,15 +161,14 @@ grep TODO/FIXME/HACK:
     # search for HACK within source tree and ignore HACKKIT board
     - grep -r HACK . | grep -v HACKKIT
 
-# build documentation
+# build HTML documentation
-docs:
+htmldocs:
   stage: testsuites
   script:
     - virtualenv -p /usr/bin/python3 /tmp/venvhtml
     - . /tmp/venvhtml/bin/activate
     - pip install -r doc/sphinx/requirements.txt
     - make htmldocs
-    - make infodocs
 
 # some statistics about the code base
 sloccount:
@@ -209,7 +220,7 @@ Run binman, buildman, dtoc, Kconfig and patman testsuites:
 Run tests for Nokia RX-51 (aka N900):
   stage: testsuites
   script:
-    - export PATH=/opt/gcc-12.2.0-nolibc/arm-linux-gnueabi/bin:$PATH;
+    - export PATH=/opt/gcc-11.1.0-nolibc/arm-linux-gnueabi/bin:$PATH;
       test/nokia_rx51_test.sh
 
 # Check for any pylint regressions
@@ -240,7 +251,7 @@ sandbox test.py:
 sandbox with clang test.py:
   variables:
     TEST_PY_BD: "sandbox"
-    OVERRIDE: "-O clang-14"
+    OVERRIDE: "-O clang-13"
   <<: *buildman_and_testpy_dfn
 
 sandbox without LTO test.py:

Kconfig

@@ -264,8 +264,8 @@ config HAS_CUSTOM_SYS_INIT_SP_ADDR
 	default y if TFABOOT
 	help
 	  Typically, we use an initial stack pointer address that is calculated
-	  by taking the statically defined CFG_SYS_INIT_RAM_ADDR, adding the
+	  by taking the statically defined CONFIG_SYS_INIT_RAM_ADDR, adding the
-	  statically defined CFG_SYS_INIT_RAM_SIZE and then subtracting the
+	  statically defined CONFIG_SYS_INIT_RAM_SIZE and then subtracting the
 	  build-time constant of GENERATED_GBL_DATA_SIZE.  On MIPS a different
 	  but statica calculation is performed.  However, some platforms will
 	  take a different approach.  Say Y here to define the address statically
@@ -333,7 +333,7 @@ config SPL_SYS_MALLOC_F_LEN
 	  particular needs this to operate, so that it can allocate the
 	  initial serial device and any others that are needed.
 
-	  It is possible to enable CFG_SYS_SPL_MALLOC_START to start a new
+	  It is possible to enable CONFIG_SYS_SPL_MALLOC_START to start a new
 	  malloc() region in SDRAM once it is inited.
 
 config TPL_SYS_MALLOC_F_LEN
@@ -456,12 +456,11 @@ config BUILD_TARGET
 	string "Build target special images"
 	default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_ARRIA10
 	default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_GEN5
-	default "u-boot-with-spl.kwb" if ARMADA_32BIT && SPL
+	default "u-boot-spl.kwb" if ARCH_MVEBU && SPL
 	default "u-boot-elf.srec" if RCAR_GEN3
 	default "u-boot.itb" if !BINMAN && SPL_LOAD_FIT && (ARCH_ROCKCHIP || \
-				ARCH_SUNXI || RISCV || ARCH_ZYNQMP)
+				RISCV || ARCH_ZYNQMP)
-	default "u-boot.kwb" if (ARCH_KIRKWOOD || ARMADA_32BIT) && !SPL
+	default "u-boot.kwb" if ARCH_KIRKWOOD
-	default "u-boot-with-spl.bin" if MPC85xx && !E500MC && !E5500 && !E6500 && SPL
 	default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT
 	default "u-boot-with-spl.imx" if ARCH_MX6 && SPL
 	help
@@ -509,9 +508,6 @@ config SYS_LOAD_ADDR
 	hex "Address in memory to use by default"
 	default 0x01000000 if ARCH_SOCFPGA
 	default 0x02000000 if PPC || X86
-	default 0x81000000 if MACH_SUNIV
-	default 0x22000000 if MACH_SUN9I
-	default 0x42000000 if ARCH_SUNXI
 	default 0x82000000 if ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_K3
 	default 0x82000000 if ARCH_MX6 && (MX6SL || MX6SLL  || MX6SX || MX6UL || MX6ULL)
 	default 0x12000000 if ARCH_MX6 && !(MX6SL || MX6SLL  || MX6SX || MX6UL || MX6ULL)
@@ -584,18 +580,6 @@ config SYS_SRAM_SIZE
 	default 0x10000 if TARGET_TRICORDER
 	default 0x0
 
-config SYS_MONITOR_LEN
-	int "Maximum size in bytes reserved for U-Boot in memory"
-	default 1048576 if X86
-	default 786432 if ARCH_SUNXI
-	default 0
-	help
-	  Size of memory reserved for monitor code, used to determine
-	  _at_compile_time_ (!) if the environment is embedded within the
-	  U-Boot image, or in a separate flash sector, among other uses where
-	  we need to set a maximum size of the U-Boot binary itself that will
-	  be loaded.
-
 config MP
 	bool "Support for multiprocessor"
 	help

MAINTAINERS

@@ -192,7 +192,6 @@ N:	aspeed
 
 ARM BROADCOM BCM283X / BCM27XX
 M:	Matthias Brugger <mbrugger@suse.com>
-M:	Peter Robinson <pbrobinson@gmail.com>
 S:	Maintained
 F:	arch/arm/dts/bcm283*
 F:	arch/arm/mach-bcm283x/
@@ -409,21 +408,11 @@ T:	git https://source.denx.de/u-boot/custodians/u-boot-atmel.git
 F:	arch/arm/mach-at91/
 F:	board/atmel/
 F:	drivers/cpu/at91_cpu.c
-F:	drivers/memory/atmel-ebi.c
 F:	drivers/misc/microchip_flexcom.c
 F:	drivers/timer/atmel_tcb_timer.c
 F:	include/dt-bindings/mfd/atmel-flexcom.h
 F:	drivers/timer/mchp-pit64b-timer.c
 
-ARM MSC SM2S IMX8MP SOM
-M:	Martyn Welch <martyn.welch@collabora.com>
-M:	Ian Ray <ian.ray@ge.com>
-S:	Maintained
-F:	arch/arm/dts/imx8mp-msc-sm2s*
-F:	board/msc/sm2s_imx8mp/
-F:	configs/msc_sm2s_imx8mp_defconfig
-F:	include/configs/msc_sm2s_imx8mp.h
-
 ARM NEXELL S5P4418
 M:	Stefan Bosch <stefan_b@posteo.net>
 S:	Maintained
@@ -437,7 +426,6 @@ F:	drivers/gpio/nx_gpio.c
 F:	drivers/i2c/nx_i2c.c
 F:	drivers/mmc/nexell_dw_mmc_dm.c
 F:	drivers/pinctrl/nexell/
-F:	drivers/serial/serial_s5p4418_pl011.c
 F:	drivers/video/nexell/
 F:	drivers/video/nexell_display.c
 F:	include/configs/s5p4418_nanopi2.h
@@ -497,12 +485,6 @@ F:	arch/arm/mach-exynos/
 F:	arch/arm/mach-s5pc1xx/
 F:	arch/arm/cpu/armv7/s5p-common/
 
-ARM SANCLOUD
-M:	Paul Barker <paul.barker@sancloud.com>
-R:	Marc Murphy <marc.murphy@sancloud.com>
-S:	Supported
-F:	arch/arm/dts/am335x-sancloud*
-
 ARM SNAPDRAGON
 M:	Ramon Fried <rfried.dev@gmail.com>
 S:	Maintained
@@ -570,9 +552,10 @@ F:	drivers/spi/stm32_spi.c
 F:	drivers/video/stm32/stm32_ltdc.c
 F:	drivers/watchdog/stm32mp_wdt.c
 F:	include/dt-bindings/clock/stm32fx-clock.h
-F:	include/dt-bindings/clock/stm32mp*
+F:	include/dt-bindings/clock/stm32mp1-clks.h
+F:	include/dt-bindings/clock/stm32mp1-clksrc.h
 F:	include/dt-bindings/pinctrl/stm32-pinfunc.h
-F:	include/dt-bindings/reset/stm32mp*
+F:	include/dt-bindings/reset/stm32mp1-resets.h
 F:	include/stm32_rcc.h
 F:	tools/stm32image.c
 N:	stm
@@ -672,7 +655,6 @@ M:	Michal Simek <michal.simek@amd.com>
 S:	Maintained
 T:	git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git
 F:	arch/arm/mach-versal-net/
-F:	drivers/soc/soc_xilinx_versal_net.c
 N:	(?<!uni)versal-net
 
 ARM VERSAL
@@ -862,6 +844,7 @@ F:	cmd/dfu.c
 F:	cmd/usb_*.c
 F:	common/dfu.c
 F:	common/update.c
+F:	common/usb_storage.c
 F:	doc/api/dfu.rst
 F:	doc/usage/dfu.rst
 F:	drivers/dfu/
@@ -896,11 +879,6 @@ M:	Heinrich Schuchardt <xypron.glpk@gmx.de>
 M:	Ilias Apalodimas <ilias.apalodimas@linaro.org>
 S:	Maintained
 T:	git https://source.denx.de/u-boot/custodians/u-boot-efi.git
-F:	arch/arm/lib/*_efi.*
-F:	cmd/bootefi.c
-F:	cmd/eficonfig.c
-F:	cmd/efidebug.c
-F:	cmd/nvedit_efi.c
 F:	doc/api/efi.rst
 F:	doc/develop/uefi/*
 F:	doc/mkeficapsule.1
@@ -1198,7 +1176,6 @@ M:	Sean Anderson <seanga2@gmail.com>
 S:	Maintained
 F:	doc/api/nvmem.rst
 F:	drivers/misc/nvmem.c
-F:	drivers/reboot-mode/reboot-mode-nvmem.c
 F:	include/nvmem.h
 
 NXP C45 TJA11XX PHY DRIVER
@@ -1490,7 +1467,6 @@ T:	git https://source.denx.de/u-boot/custodians/u-boot-usb.git
 F:	drivers/usb/
 F:	common/usb.c
 F:	common/usb_kbd.c
-F:	common/usb_storage.c
 F:	include/usb.h
 
 USB xHCI

Makefile

@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0+
 
-VERSION = 2023
+VERSION = 2022
-PATCHLEVEL = 01
+PATCHLEVEL = 10
 SUBLEVEL =
 EXTRAVERSION =
 NAME =
@@ -761,10 +761,10 @@ KBUILD_CFLAGS += $(call cc-disable-warning, maybe-uninitialized)
 # change __FILE__ to the relative path from the srctree
 KBUILD_CFLAGS	+= $(call cc-option,-fmacro-prefix-map=$(srctree)/=)
 
-KBUILD_CFLAGS	+= -gdwarf-4
+KBUILD_CFLAGS	+= -g
 # $(KBUILD_AFLAGS) sets -g, which causes gcc to pass a suitable -g<format>
 # option to the assembler.
-KBUILD_AFLAGS	+= -gdwarf-4
+KBUILD_AFLAGS	+= -g
 
 # Report stack usage if supported
 # ARC tools based on GCC 7.1 has an issue with stack usage
@@ -806,8 +806,6 @@ KBUILD_CPPFLAGS += $(KCPPFLAGS)
 KBUILD_AFLAGS += $(KAFLAGS)
 KBUILD_CFLAGS += $(KCFLAGS)
 
-KBUILD_LDFLAGS  += $(call ld-option,--no-warn-rwx-segments)
-
 KBUILD_HOSTCFLAGS += $(if $(CONFIG_TOOLS_DEBUG),-g)
 
 # Use UBOOTINCLUDE when you must reference the include/ directory.
@@ -1015,6 +1013,23 @@ INPUTS-y += u-boot.img
 endif
 endif
 
+ifeq ($(CONFIG_MACH_SUN8I_H3)$(CONFIG_ARMV7_PSCI),yy)
+INPUTS-$(CONFIG_ARMV7_PSCI) += u-boot-resume.img
+
+MKIMAGEFLAGS_u-boot-resume.img := -B 0x400 -T sunxi_egon
+
+u-boot-resume.img: u-boot-resume.bin
+	$(call if_changed,mkimage)
+
+OBJCOPYFLAGS_u-boot-resume.bin := -O binary
+
+u-boot-resume.bin: u-boot-resume.o
+	$(call if_changed,objcopy)
+
+u-boot-resume.S: u-boot
+	@sed -En 's/(0x[[:xdigit:]]+) +psci_cpu_entry/ldr pc, =\1/p' $<.map > $@
+endif
+
 INPUTS-$(CONFIG_X86) += u-boot-x86-start16.bin u-boot-x86-reset16.bin \
 	$(if $(CONFIG_SPL_X86_16BIT_INIT),spl/u-boot-spl.bin) \
 	$(if $(CONFIG_TPL_X86_16BIT_INIT),tpl/u-boot-tpl.bin)
@@ -1075,6 +1090,10 @@ cmd_lzma = lzma -c -z -k -9 $< > $@
 
 cfg: u-boot.cfg
 
+quiet_cmd_cfgcheck = CFGCHK  $2
+cmd_cfgcheck = $(srctree)/scripts/check-config.sh $2 \
+		$(srctree)/scripts/config_whitelist.txt $(srctree)
+
 quiet_cmd_ofcheck = OFCHK   $2
 cmd_ofcheck = $(srctree)/scripts/check-of.sh $2 \
 		$(srctree)/scripts/of_allowlist.txt
@@ -1106,14 +1125,17 @@ define deprecated
 
 endef
 
-# Timestamp file to make sure that binman always runs
+PHONY += inputs
-.binman_stamp: $(INPUTS-y) FORCE
+inputs: $(INPUTS-y)
+
+all: .binman_stamp inputs
 ifeq ($(CONFIG_BINMAN),y)
 	$(call if_changed,binman)
 endif
-	@touch $@
 
-all: .binman_stamp
+# Timestamp file to make sure that binman always runs
+.binman_stamp: FORCE
+	@touch $@
 
 ifeq ($(CONFIG_DEPRECATED),y)
 	$(warning "You have deprecated configuration options enabled in your .config! Please check your configuration.")
@@ -1136,12 +1158,16 @@ endif
 	$(call deprecated,CONFIG_WDT,DM watchdog,v2019.10,\
 		$(CONFIG_WATCHDOG)$(CONFIG_HW_WATCHDOG))
 	$(call deprecated,CONFIG_DM_I2C,I2C drivers,v2022.04,$(CONFIG_SYS_I2C_LEGACY))
-	@# CFG_SYS_TIMER_RATE has brackets in it for some boards which
+	@# CONFIG_SYS_TIMER_RATE has brackets in it for some boards which
 	@# confuses this rule. Use if() to send just a single character which
 	@# is enable to tell 'deprecated' that one of these symbols exists
-	$(call deprecated,CONFIG_TIMER,Timer drivers,v2023.01,$(if $(strip $(CFG_SYS_TIMER_RATE)$(CFG_SYS_TIMER_COUNTER)),x))
+	$(call deprecated,CONFIG_TIMER,Timer drivers,v2023.01,$(if $(strip $(CONFIG_SYS_TIMER_RATE)$(CONFIG_SYS_TIMER_COUNTER)),x))
 	$(call deprecated,CONFIG_DM_SERIAL,Serial drivers,v2023.04,$(CONFIG_SERIAL))
 	$(call deprecated,CONFIG_DM_SCSI,SCSI drivers,v2023.04,$(CONFIG_SCSI))
+	@# Check that this build does not use CONFIG options that we do not
+	@# know about unless they are in Kconfig. All the existing CONFIG
+	@# options are whitelisted, so new ones should not be added.
+	$(call cmd,cfgcheck,u-boot.cfg)
 	@# Check that this build does not override OF_HAS_PRIOR_STAGE by
 	@# disabling OF_BOARD.
 	$(call cmd,ofcheck,$(KCONFIG_CONFIG))
@@ -1327,8 +1353,8 @@ cmd_binman = $(srctree)/tools/binman/binman $(if $(BINMAN_DEBUG),-D) \
 		$(foreach f,$(BINMAN_TOOLPATHS),--toolpath $(f)) \
                 --toolpath $(objtree)/tools \
 		$(if $(BINMAN_VERBOSE),-v$(BINMAN_VERBOSE)) \
-		build -u -d u-boot.dtb -O . -m \
+		build -u -d u-boot.dtb -O . -m --allow-missing \
-		$(if $(BINMAN_ALLOW_MISSING),--allow-missing --ignore-missing) \
+		--fake-ext-blobs \
 		-I . -I $(srctree) -I $(srctree)/board/$(BOARDDIR) \
 		-I arch/$(ARCH)/dts -a of-list=$(CONFIG_OF_LIST) \
 		$(foreach f,$(BINMAN_INDIRS),-I $(f)) \
@@ -1355,8 +1381,8 @@ u-boot.ldr.hex u-boot.ldr.srec: u-boot.ldr FORCE
 # U-Boot entry point, needed for booting of full-blown U-Boot
 # from the SPL U-Boot version.
 #
-ifndef CFG_SYS_UBOOT_START
+ifndef CONFIG_SYS_UBOOT_START
-CFG_SYS_UBOOT_START := $(CONFIG_TEXT_BASE)
+CONFIG_SYS_UBOOT_START := $(CONFIG_TEXT_BASE)
 endif
 
 # Boards with more complex image requirements can provide an .its source file
@@ -1381,7 +1407,7 @@ endif
 
 ifdef CONFIG_SPL_LOAD_FIT
 MKIMAGEFLAGS_u-boot.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
-	-a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \
+	-a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
 	-p $(CONFIG_FIT_EXTERNAL_OFFSET) \
 	-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \
 	$(patsubst %,-b arch/$(ARCH)/dts/%.dtb,$(subst ",,$(DEVICE_TREE))) \
@@ -1389,10 +1415,10 @@ MKIMAGEFLAGS_u-boot.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
 	$(patsubst %,-b arch/$(ARCH)/dts/%.dtbo,$(subst ",,$(CONFIG_OF_OVERLAY_LIST)))
 else
 MKIMAGEFLAGS_u-boot.img = -A $(ARCH) -T firmware -C none -O u-boot \
-	-a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \
+	-a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
 	-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board"
 MKIMAGEFLAGS_u-boot-ivt.img = -A $(ARCH) -T firmware_ivt -C none -O u-boot \
-	-a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \
+	-a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
 	-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board"
 u-boot-ivt.img: MKIMAGEOUTPUT = u-boot-ivt.img.log
 endif
@@ -1413,7 +1439,7 @@ KWD_CONFIG_FILE = $(shell \
 MKIMAGEFLAGS_u-boot.kwb = -n $(KWD_CONFIG_FILE) \
 	-T kwbimage -a $(CONFIG_TEXT_BASE) -e $(CONFIG_TEXT_BASE)
 
-MKIMAGEFLAGS_u-boot-with-spl.kwb = -n $(KWD_CONFIG_FILE) \
+MKIMAGEFLAGS_u-boot-spl.kwb = -n $(KWD_CONFIG_FILE) \
 	-T kwbimage -a $(CONFIG_TEXT_BASE) -e $(CONFIG_TEXT_BASE) \
 	$(if $(KEYDIR),-k $(KEYDIR))
 
@@ -1423,7 +1449,7 @@ MKIMAGEFLAGS_u-boot.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \
 UBOOT_BIN := u-boot.bin
 
 MKIMAGEFLAGS_u-boot-lzma.img = -A $(ARCH) -T standalone -C lzma -O u-boot \
-	-a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \
+	-a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
 	-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board"
 
 u-boot.bin.lzma: u-boot.bin FORCE
@@ -1454,7 +1480,7 @@ u-boot.itb: u-boot-nodtb.bin \
 	$(BOARD_SIZE_CHECK)
 endif
 
-u-boot-with-spl.kwb: u-boot.bin spl/u-boot-spl.bin FORCE
+u-boot-spl.kwb: u-boot.bin spl/u-boot-spl.bin FORCE
 	$(call if_changed,mkimage)
 	$(BOARD_SIZE_CHECK)
 
@@ -2366,7 +2392,7 @@ tcheck:
 # Documentation targets
 # ---------------------------------------------------------------------------
 DOC_TARGETS := xmldocs latexdocs pdfdocs htmldocs epubdocs cleandocs \
-	       linkcheckdocs dochelp refcheckdocs texinfodocs infodocs
+	       linkcheckdocs dochelp refcheckdocs
 PHONY += $(DOC_TARGETS)
 $(DOC_TARGETS): scripts_basic FORCE
 	$(Q)$(MAKE) $(build)=doc $@
@@ -2433,13 +2459,11 @@ endif
 	$(Q)$(MAKE) -f $(srctree)/scripts/Makefile.modpost
 
 quiet_cmd_genenv = GENENV  $@
-cmd_genenv = \
+cmd_genenv = $(OBJCOPY) --dump-section .rodata.default_environment=$@ env/common.o; \
-	$(objtree)/tools/printinitialenv | \
+	sed --in-place -e 's/\x00/\x0A/g' $@; sed --in-place -e '/^\s*$$/d' $@; \
-	sed -e '/^\s*$$/d' | \
+	sort --field-separator== -k1,1 --stable $@ -o $@
-	sort --field-separator== -k1,1 --stable -o $@
 
-u-boot-initial-env: $(env_h) FORCE
+u-boot-initial-env: u-boot.bin
-	$(Q)$(MAKE) $(build)=tools $(objtree)/tools/printinitialenv
 	$(call if_changed,genenv)
 
 # Consistency checks

README

@@ -298,7 +298,7 @@ The following options need to be configured:
 
 		Enables a workaround for erratum A004510.  If set,
 		then CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV and
-		CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY must be set.
+		CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY must be set.
 
 		CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
 		CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 (optional)
@@ -314,7 +314,7 @@ The following options need to be configured:
 		See Freescale App Note 4493 for more information about
 		this erratum.
 
-		CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
+		CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
 
 		This is the value to write into CCSR offset 0x18600
 		according to the A004510 workaround.
@@ -330,7 +330,7 @@ The following options need to be configured:
 		Freescale DDR driver in use. This type of DDR controller is
 		found in mpc83xx, mpc85xx as well as some ARM core SoCs.
 
-		CFG_SYS_FSL_DDR_ADDR
+		CONFIG_SYS_FSL_DDR_ADDR
 		Freescale DDR memory-mapped register base.
 
 		CONFIG_SYS_FSL_IFC_CLK_DIV
@@ -339,9 +339,9 @@ The following options need to be configured:
 		CONFIG_SYS_FSL_LBC_CLK_DIV
 		Defines divider of platform clock(clock input to eLBC controller).
 
-		CFG_SYS_FSL_DDR_SDRAM_BASE_PHY
+		CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
 		Physical address from the view of DDR controllers. It is the
-		same as CFG_SYS_DDR_SDRAM_BASE for  all Power SoCs. But
+		same as CONFIG_SYS_DDR_SDRAM_BASE for  all Power SoCs. But
 		it could be different for ARM SoCs.
 
 - MIPS CPU options:
@@ -352,7 +352,7 @@ The following options need to be configured:
 		be swapped if a flash programmer is used.
 
 - ARM options:
-		CFG_SYS_EXCEPTION_VECTORS_HIGH
+		CONFIG_SYS_EXCEPTION_VECTORS_HIGH
 
 		Select high exception vectors of the ARM core, e.g., do not
 		clear the V bit of the c1 register of CP15.
@@ -373,6 +373,12 @@ The following options need to be configured:
 		such as ARM architectural timer initialization.
 
 - Linux Kernel Interface:
+		CONFIG_MEMSIZE_IN_BYTES		[relevant for MIPS only]
+
+		When transferring memsize parameter to Linux, some versions
+		expect it to be in bytes, others in MB.
+		Define CONFIG_MEMSIZE_IN_BYTES to make it in bytes.
+
 		CONFIG_OF_LIBFDT
 
 		New kernel versions are expecting firmware settings to be
@@ -409,16 +415,16 @@ The following options need to be configured:
 		the defaults discussed just above.
 
 - Cache Configuration for ARM:
-		CFG_SYS_PL310_BASE - Physical base address of PL310
+		CONFIG_SYS_PL310_BASE - Physical base address of PL310
 					controller register space
 
 - Serial Ports:
-		CFG_PL011_CLOCK
+		CONFIG_PL011_CLOCK
 
 		If you have Amba PrimeCell PL011 UARTs, set this variable to
 		the clock speed of the UARTs.
 
-		CFG_PL01x_PORTS
+		CONFIG_PL01x_PORTS
 
 		If you have Amba PrimeCell PL010 or PL011 UARTs on your board,
 		define this to a list of base addresses for each (supported)
@@ -429,6 +435,15 @@ The following options need to be configured:
 		Define this variable to enable hw flow control in serial driver.
 		Current user of this option is drivers/serial/nsl16550.c driver
 
+- Serial Download Echo Mode:
+		CONFIG_LOADS_ECHO
+		If defined to 1, all characters received during a
+		serial download (using the "loads" command) are
+		echoed back. This might be needed by some terminal
+		emulations (like "cu"), but may as well just take
+		time on others. This setting #define's the initial
+		value of the "loads_echo" environment variable.
+
 - Removal of commands
 		If no commands are needed to boot, you can disable
 		CONFIG_CMDLINE to remove them. In this case, the command line
@@ -454,8 +469,33 @@ The following options need to be configured:
 		to 0 disables calling WATCHDOG_RESET() from the timer
 		interrupt.
 
+- Real-Time Clock:
+
+		When CONFIG_CMD_DATE is selected, the type of the RTC
+		has to be selected, too. Define exactly one of the
+		following options:
+
+		CONFIG_RTC_PCF8563	- use Philips PCF8563 RTC
+		CONFIG_RTC_MC13XXX	- use MC13783 or MC13892 RTC
+		CONFIG_RTC_MC146818	- use MC146818 RTC
+		CONFIG_RTC_DS1307	- use Maxim, Inc. DS1307 RTC
+		CONFIG_RTC_DS1337	- use Maxim, Inc. DS1337 RTC
+		CONFIG_RTC_DS1338	- use Maxim, Inc. DS1338 RTC
+		CONFIG_RTC_DS1339	- use Maxim, Inc. DS1339 RTC
+		CONFIG_RTC_DS164x	- use Dallas DS164x RTC
+		CONFIG_RTC_ISL1208	- use Intersil ISL1208 RTC
+		CONFIG_RTC_MAX6900	- use Maxim, Inc. MAX6900 RTC
+		CONFIG_RTC_DS1337_NOOSC	- Turn off the OSC output for DS1337
+		CONFIG_SYS_RV3029_TCR	- enable trickle charger on
+					  RV3029 RTC.
+
+		Note that if the RTC uses I2C, then the I2C interface
+		must also be configured. See I2C Support, below.
+
 - GPIO Support:
-		The CFG_SYS_I2C_PCA953X_WIDTH option specifies a list of
+		CONFIG_PCA953X		- use NXP's PCA953X series I2C GPIO
+
+		The CONFIG_SYS_I2C_PCA953X_WIDTH option specifies a list of
 		chip-ngpio pairs that tell the PCA953X driver the number of
 		pins supported by a particular chip.
 
@@ -541,13 +581,13 @@ The following options need to be configured:
 		CONFIG_SH_ETHER
 		Support for Renesas on-chip Ethernet controller
 
-			CFG_SH_ETHER_USE_PORT
+			CONFIG_SH_ETHER_USE_PORT
 			Define the number of ports to be used
 
-			CFG_SH_ETHER_PHY_ADDR
+			CONFIG_SH_ETHER_PHY_ADDR
 			Define the ETH PHY's address
 
-			CFG_SH_ETHER_CACHE_WRITEBACK
+			CONFIG_SH_ETHER_CACHE_WRITEBACK
 			If this option is set, the driver enables cache flush.
 
 - TPM Support:
@@ -579,6 +619,11 @@ The following options need to be configured:
 		Support for generic parallel port TPM devices. Only one device
 		per system is supported at this time.
 
+			CONFIG_TPM_TIS_BASE_ADDRESS
+			Base address where the generic TPM device is mapped
+			to. Contemporary x86 systems usually map it at
+			0xfed40000.
+
 		CONFIG_TPM
 		Define this to enable the TPM support library which provides
 		functional interfaces to some TPM commands.
@@ -618,6 +663,21 @@ The following options need to be configured:
 		variable usbtty to be cdc_acm should suffice. The following
 		might be defined in YourBoardName.h
 
+			CONFIG_USB_DEVICE
+			Define this to build a UDC device
+
+			CONFIG_USB_TTY
+			Define this to have a tty type of device available to
+			talk to the UDC device
+
+			CONFIG_USBD_HS
+			Define this to enable the high speed support for usb
+			device and usbtty. If this feature is enabled, a routine
+			int is_usbd_high_speed(void)
+			also needs to be defined by the driver to dynamically poll
+			whether the enumeration has succeded at high speed or full
+			speed.
+
 		If you have a USB-IF assigned VendorID then you may wish to
 		define your own vendor specific values either in BoardName.h
 		or directly in usbd_vendor_info.h. If you don't define
@@ -702,6 +762,11 @@ The following options need to be configured:
 		entering dfuMANIFEST state. Host waits this timeout, before
 		sending again an USB request to the device.
 
+- Journaling Flash filesystem support:
+		CONFIG_SYS_JFFS2_FIRST_SECTOR,
+		CONFIG_SYS_JFFS2_FIRST_BANK, CONFIG_SYS_JFFS2_NUM_BANKS
+		Define these for a default partition on a NOR device
+
 - Keyboard Support:
 		See Kconfig help for available keyboard drivers.
 
@@ -715,6 +780,38 @@ The following options need to be configured:
 		Some PHY like Intel LXT971A need extra delay after
 		command issued before MII status register can be read
 
+- IP address:
+		CONFIG_IPADDR
+
+		Define a default value for the IP address to use for
+		the default Ethernet interface, in case this is not
+		determined through e.g. bootp.
+		(Environment variable "ipaddr")
+
+- Server IP address:
+		CONFIG_SERVERIP
+
+		Defines a default value for the IP address of a TFTP
+		server to contact when using the "tftboot" command.
+		(Environment variable "serverip")
+
+- Gateway IP address:
+		CONFIG_GATEWAYIP
+
+		Defines a default value for the IP address of the
+		default router where packets to other networks are
+		sent to.
+		(Environment variable "gatewayip")
+
+- Subnet mask:
+		CONFIG_NETMASK
+
+		Defines a default value for the subnet mask (or
+		routing prefix) which is used to determine if an IP
+		address belongs to the local subnet or needs to be
+		forwarded through a router.
+		(Environment variable "netmask")
+
 - BOOTP Recovery Mode:
 		CONFIG_BOOTP_RANDOM_DELAY
 
@@ -840,26 +937,26 @@ The following options need to be configured:
 		with a list of GPIO LEDs that have inverted polarity.
 
 - I2C Support:
-		CFG_SYS_NUM_I2C_BUSES
+		CONFIG_SYS_NUM_I2C_BUSES
 		Hold the number of i2c buses you want to use.
 
-		CFG_SYS_I2C_DIRECT_BUS
+		CONFIG_SYS_I2C_DIRECT_BUS
 		define this, if you don't use i2c muxes on your hardware.
-		if CFG_SYS_I2C_MAX_HOPS is not defined or == 0 you can
+		if CONFIG_SYS_I2C_MAX_HOPS is not defined or == 0 you can
 		omit this define.
 
-		CFG_SYS_I2C_MAX_HOPS
+		CONFIG_SYS_I2C_MAX_HOPS
 		define how many muxes are maximal consecutively connected
 		on one i2c bus. If you not use i2c muxes, omit this
 		define.
 
-		CFG_SYS_I2C_BUSES
+		CONFIG_SYS_I2C_BUSES
 		hold a list of buses you want to use, only used if
-		CFG_SYS_I2C_DIRECT_BUS is not defined, for example
+		CONFIG_SYS_I2C_DIRECT_BUS is not defined, for example
-		a board with CFG_SYS_I2C_MAX_HOPS = 1 and
+		a board with CONFIG_SYS_I2C_MAX_HOPS = 1 and
-		CFG_SYS_NUM_I2C_BUSES = 9:
+		CONFIG_SYS_NUM_I2C_BUSES = 9:
 
-		 CFG_SYS_I2C_BUSES	{{0, {I2C_NULL_HOP}}, \
+		 CONFIG_SYS_I2C_BUSES	{{0, {I2C_NULL_HOP}}, \
 					{0, {{I2C_MUX_PCA9547, 0x70, 1}}}, \
 					{0, {{I2C_MUX_PCA9547, 0x70, 2}}}, \
 					{0, {{I2C_MUX_PCA9547, 0x70, 3}}}, \
@@ -955,24 +1052,43 @@ The following options need to be configured:
 		You should define these to the GPIO value as given directly to
 		the generic GPIO functions.
 
-		CFG_I2C_MULTI_BUS
+		CONFIG_SYS_I2C_INIT_BOARD
+
+		When a board is reset during an i2c bus transfer
+		chips might think that the current transfer is still
+		in progress. On some boards it is possible to access
+		the i2c SCLK line directly, either by using the
+		processor pin as a GPIO or by having a second pin
+		connected to the bus. If this option is defined a
+		custom i2c_init_board() routine in boards/xxx/board.c
+		is run early in the boot sequence.
+
+		CONFIG_I2C_MULTI_BUS
 
 		This option allows the use of multiple I2C buses, each of which
 		must have a controller.	 At any point in time, only one bus is
 		active.	 To switch to a different bus, use the 'i2c dev' command.
 		Note that bus numbering is zero-based.
 
-		CFG_SYS_I2C_NOPROBES
+		CONFIG_SYS_I2C_NOPROBES
 
 		This option specifies a list of I2C devices that will be skipped
-		when the 'i2c probe' command is issued.
+		when the 'i2c probe' command is issued.	 If CONFIG_I2C_MULTI_BUS
+		is set, specify a list of bus-device pairs.  Otherwise, specify
+		a 1D array of device addresses
 
 		e.g.
-			#define CFG_SYS_I2C_NOPROBES {0x50,0x68}
+			#undef	CONFIG_I2C_MULTI_BUS
+			#define CONFIG_SYS_I2C_NOPROBES {0x50,0x68}
 
 		will skip addresses 0x50 and 0x68 on a board with one I2C bus
 
-		CFG_SYS_RTC_BUS_NUM
+			#define CONFIG_I2C_MULTI_BUS
+			#define CONFIG_SYS_I2C_NOPROBES	{{0,0x50},{0,0x68},{1,0x54}}
+
+		will skip addresses 0x50 and 0x68 on bus 0 and address 0x54 on bus 1
+
+		CONFIG_SYS_RTC_BUS_NUM
 
 		If defined, then this indicates the I2C bus number for the RTC.
 		If not defined, then U-Boot assumes that RTC is on I2C bus 0.
@@ -1018,7 +1134,7 @@ The following options need to be configured:
 		will require a board or device specific function to
 		be written.
 
-		CFG_FPGA_DELAY
+		CONFIG_FPGA_DELAY
 
 		If defined, a function that provides delays in the FPGA
 		configuration driver.
@@ -1030,19 +1146,19 @@ The following options need to be configured:
 		configuration if the INIT_B line goes low (which
 		indicated a CRC error).
 
-		CFG_SYS_FPGA_WAIT_INIT
+		CONFIG_SYS_FPGA_WAIT_INIT
 
 		Maximum time to wait for the INIT_B line to de-assert
 		after PROB_B has been de-asserted during a Virtex II
 		FPGA configuration sequence. The default time is 500
 		ms.
 
-		CFG_SYS_FPGA_WAIT_BUSY
+		CONFIG_SYS_FPGA_WAIT_BUSY
 
 		Maximum time to wait for BUSY to de-assert during
 		Virtex II FPGA configuration. The default is 5 ms.
 
-		CFG_SYS_FPGA_WAIT_CONFIG
+		CONFIG_SYS_FPGA_WAIT_CONFIG
 
 		Time to wait after FPGA configuration. The default is
 		200 ms.
@@ -1063,17 +1179,24 @@ The following options need to be configured:
 		completely disabled. Anybody can change or delete
 		these parameters.
 
+		Alternatively, if you define _both_ an ethaddr in the
+		default env _and_ CONFIG_OVERWRITE_ETHADDR_ONCE, a default
+		Ethernet address is installed in the environment,
+		which can be changed exactly ONCE by the user. [The
+		serial# is unaffected by this, i. e. it remains
+		read-only.]
+
 		The same can be accomplished in a more flexible way
 		for any variable by configuring the type of access
 		to allow for those variables in the ".flags" variable
-		or define CFG_ENV_FLAGS_LIST_STATIC.
+		or define CONFIG_ENV_FLAGS_LIST_STATIC.
 
 - Protected RAM:
-		CFG_PRAM
+		CONFIG_PRAM
 
 		Define this variable to enable the reservation of
 		"protected RAM", i. e. RAM which is not overwritten
-		by U-Boot. Define CFG_PRAM to hold the number of
+		by U-Boot. Define CONFIG_PRAM to hold the number of
 		kB you want to reserve for pRAM. You can overwrite
 		this default value by defining an environment
 		variable "pram" to the number of kB you want to
@@ -1124,7 +1247,7 @@ The following options need to be configured:
 		symbols.
 
 - Default Environment:
-		CFG_EXTRA_ENV_SETTINGS
+		CONFIG_EXTRA_ENV_SETTINGS
 
 		Define this to contain any number of null terminated
 		strings (variable = value pairs) that will be part of
@@ -1133,7 +1256,7 @@ The following options need to be configured:
 		For example, place something like this in your
 		board's config file:
 
-		#define CFG_EXTRA_ENV_SETTINGS \
+		#define CONFIG_EXTRA_ENV_SETTINGS \
 			"myvar1=value1\0" \
 			"myvar2=value2\0"
 
@@ -1158,6 +1281,13 @@ The following options need to be configured:
 		this is instead controlled by the value of
 		/config/load-environment.
 
+		CONFIG_STANDALONE_LOAD_ADDR
+
+		This option defines a board specific value for the
+		address where standalone program gets loaded, thus
+		overwriting the architecture dependent default
+		settings.
+
 - Automatic software updates via TFTP server
 		CONFIG_UPDATE_TFTP
 		CONFIG_UPDATE_TFTP_CNT_MAX
@@ -1259,20 +1389,24 @@ The following options need to be configured:
 		CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_COUNT,
 		CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE,
 		CONFIG_SYS_NAND_BLOCK_SIZE, CONFIG_SYS_NAND_BAD_BLOCK_POS,
-		CFG_SYS_NAND_ECCPOS, CFG_SYS_NAND_ECCSIZE,
+		CONFIG_SYS_NAND_ECCPOS, CONFIG_SYS_NAND_ECCSIZE,
-		CFG_SYS_NAND_ECCBYTES
+		CONFIG_SYS_NAND_ECCBYTES
 		Defines the size and behavior of the NAND that SPL uses
 		to read U-Boot
 
-		CFG_SYS_NAND_U_BOOT_DST
+		CONFIG_SYS_NAND_U_BOOT_DST
 		Location in memory to load U-Boot to
 
-		CFG_SYS_NAND_U_BOOT_SIZE
+		CONFIG_SYS_NAND_U_BOOT_SIZE
 		Size of image to load
 
-		CFG_SYS_NAND_U_BOOT_START
+		CONFIG_SYS_NAND_U_BOOT_START
 		Entry point in loaded image to jump to
 
+		CONFIG_SYS_NAND_HW_ECC_OOBFIRST
+		Define this if you need to first read the OOB and then the
+		data. This is used, for example, on davinci platforms.
+
 		CONFIG_SPL_RAM_DEVICE
 		Support for running image already present in ram, in SPL binary
 
@@ -1325,24 +1459,33 @@ Configuration Settings:
 - CONFIG_SYS_PROMPT:	This is what U-Boot prints on the console to
 		prompt for user input.
 
-- CFG_SYS_BAUDRATE_TABLE:
+- CONFIG_SYS_BAUDRATE_TABLE:
 		List of legal baudrate settings for this board.
 
-- CFG_SYS_MEM_RESERVE_SECURE
+- CONFIG_SYS_MEM_RESERVE_SECURE
 		Only implemented for ARMv8 for now.
-		If defined, the size of CFG_SYS_MEM_RESERVE_SECURE memory
+		If defined, the size of CONFIG_SYS_MEM_RESERVE_SECURE memory
 		is substracted from total RAM and won't be reported to OS.
 		This memory can be used as secure memory. A variable
 		gd->arch.secure_ram is used to track the location. In systems
 		the RAM base is not zero, or RAM is divided into banks,
 		this variable needs to be recalcuated to get the address.
 
-- CFG_SYS_SDRAM_BASE:
+- CONFIG_SYS_LOADS_BAUD_CHANGE:
+		Enable temporary baudrate change while serial download
+
+- CONFIG_SYS_SDRAM_BASE:
 		Physical start address of SDRAM. _Must_ be 0 here.
 
-- CFG_SYS_FLASH_BASE:
+- CONFIG_SYS_FLASH_BASE:
 		Physical start address of Flash memory.
 
+- CONFIG_SYS_MONITOR_LEN:
+		Size of memory reserved for monitor code, used to
+		determine _at_compile_time_ (!) if the environment is
+		embedded within the U-Boot image, or in a separate
+		flash sector.
+
 - CONFIG_SYS_MALLOC_LEN:
 		Size of DRAM reserved for malloc() use.
 
@@ -1364,16 +1507,35 @@ Configuration Settings:
 		boards which do not use the full malloc in SPL (which is
 		enabled with CONFIG_SYS_SPL_MALLOC).
 
-- CFG_SYS_BOOTMAPSZ:
+- CONFIG_SYS_NONCACHED_MEMORY:
+		Size of non-cached memory area. This area of memory will be
+		typically located right below the malloc() area and mapped
+		uncached in the MMU. This is useful for drivers that would
+		otherwise require a lot of explicit cache maintenance. For
+		some drivers it's also impossible to properly maintain the
+		cache. For example if the regions that need to be flushed
+		are not a multiple of the cache-line size, *and* padding
+		cannot be allocated between the regions to align them (i.e.
+		if the HW requires a contiguous array of regions, and the
+		size of each region is not cache-aligned), then a flush of
+		one region may result in overwriting data that hardware has
+		written to another region in the same cache-line. This can
+		happen for example in network drivers where descriptors for
+		buffers are typically smaller than the CPU cache-line (e.g.
+		16 bytes vs. 32 or 64 bytes).
+
+		Non-cached memory is only supported on 32-bit ARM at present.
+
+- CONFIG_SYS_BOOTMAPSZ:
 		Maximum size of memory mapped by the startup code of
 		the Linux kernel; all data that must be processed by
 		the Linux kernel (bd_info, boot arguments, FDT blob if
 		used) must be put below this limit, unless "bootm_low"
 		environment variable is defined and non-zero. In such case
 		all data for the Linux kernel must be between "bootm_low"
-		and "bootm_low" + CFG_SYS_BOOTMAPSZ.	 The environment
+		and "bootm_low" + CONFIG_SYS_BOOTMAPSZ.	 The environment
 		variable "bootm_mapsize" will override the value of
-		CFG_SYS_BOOTMAPSZ.  If CFG_SYS_BOOTMAPSZ is undefined,
+		CONFIG_SYS_BOOTMAPSZ.  If CONFIG_SYS_BOOTMAPSZ is undefined,
 		then the value in "bootm_size" will be used instead.
 
 - CONFIG_SYS_BOOT_GET_CMDLINE:
@@ -1404,8 +1566,26 @@ Configuration Settings:
 - CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 		Use buffered writes to flash.
 
+- CONFIG_FLASH_SPANSION_S29WS_N
+		s29ws-n MirrorBit flash has non-standard addresses for buffered
+		write commands.
+
+- CONFIG_FLASH_SHOW_PROGRESS
+		If defined (must be an integer), print out countdown
+		digits and dots.  Recommended value: 45 (9..1) for 80
+		column displays, 15 (3..1) for 40 column displays.
+
+- CONFIG_FLASH_VERIFY
+		If defined, the content of the flash (destination) is compared
+		against the source after the write operation. An error message
+		will be printed when the contents are not identical.
+		Please note that this option is useless in nearly all cases,
+		since such flash programming errors usually are detected earlier
+		while unprotecting/erasing/programming. Please only enable
+		this option if you really know what you are doing.
+
 - CONFIG_ENV_FLAGS_LIST_DEFAULT
-- CFG_ENV_FLAGS_LIST_STATIC
+- CONFIG_ENV_FLAGS_LIST_STATIC
 	Enable validation of the values given to environment variables when
 	calling env set.  Variables can be restricted to only decimal,
 	hexadecimal, or boolean.  If CONFIG_CMD_NET is also defined,
@@ -1436,7 +1616,7 @@ Configuration Settings:
 		Define this to a list (string) to define the ".flags"
 		environment variable in the default or embedded environment.
 
-	- CFG_ENV_FLAGS_LIST_STATIC
+	- CONFIG_ENV_FLAGS_LIST_STATIC
 		Define this to a list (string) to define validation that
 		should be done if an entry is not found in the ".flags"
 		environment variable.  To override a setting in the static
@@ -1451,6 +1631,11 @@ The following definitions that deal with the placement and management
 of environment data (variable area); in general, we support the
 following configurations:
 
+- CONFIG_BUILD_ENVCRC:
+
+	Builds up envcrc with the target environment so that external utils
+	may easily extract it and embed it in final U-Boot images.
+
 BE CAREFUL! The first access to the environment happens quite early
 in U-Boot initialization (when we try to get the setting of for the
 console baudrate). You *MUST* have mapped your NVRAM area then, or
@@ -1491,6 +1676,13 @@ use the "saveenv" command to store a valid environment.
 - CONFIG_SYS_FAULT_MII_ADDR:
 		MII address of the PHY to check for the Ethernet link state.
 
+- CONFIG_NS16550_MIN_FUNCTIONS:
+		Define this if you desire to only have use of the NS16550_init
+		and NS16550_putc functions for the serial driver located at
+		drivers/serial/ns16550.c.  This option is useful for saving
+		space for already greatly restricted images, including but not
+		limited to NAND_SPL configurations.
+
 - CONFIG_DISPLAY_BOARDINFO
 		Display information about the board that U-Boot is running on
 		when U-Boot starts up. The board function checkboard() is called
@@ -1511,11 +1703,11 @@ Low Level (hardware related) configuration options:
 		Default (power-on reset) physical address of CCSR on Freescale
 		PowerPC SOCs.
 
-- CFG_SYS_CCSRBAR:
+- CONFIG_SYS_CCSRBAR:
 		Virtual address of CCSR.  On a 32-bit build, this is typically
 		the same value as CONFIG_SYS_CCSRBAR_DEFAULT.
 
-- CFG_SYS_CCSRBAR_PHYS:
+- CONFIG_SYS_CCSRBAR_PHYS:
 		Physical address of CCSR.  CCSR can be relocated to a new
 		physical address, if desired.  In this case, this macro should
 		be set to that address.	 Otherwise, it should be set to the
@@ -1523,17 +1715,17 @@ Low Level (hardware related) configuration options:
 		is typically relocated on 36-bit builds.  It is recommended
 		that this macro be defined via the _HIGH and _LOW macros:
 
-		#define CFG_SYS_CCSRBAR_PHYS ((CFG_SYS_CCSRBAR_PHYS_HIGH
+		#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH
-			* 1ull) << 32 | CFG_SYS_CCSRBAR_PHYS_LOW)
+			* 1ull) << 32 | CONFIG_SYS_CCSRBAR_PHYS_LOW)
 
-- CFG_SYS_CCSRBAR_PHYS_HIGH:
+- CONFIG_SYS_CCSRBAR_PHYS_HIGH:
-		Bits 33-36 of CFG_SYS_CCSRBAR_PHYS.	This value is typically
+		Bits 33-36 of CONFIG_SYS_CCSRBAR_PHYS.	This value is typically
 		either 0 (32-bit build) or 0xF (36-bit build).	This macro is
 		used in assembly code, so it must not contain typecasts or
 		integer size suffixes (e.g. "ULL").
 
-- CFG_SYS_CCSRBAR_PHYS_LOW:
+- CONFIG_SYS_CCSRBAR_PHYS_LOW:
-		Lower 32-bits of CFG_SYS_CCSRBAR_PHYS.  This macro is
+		Lower 32-bits of CONFIG_SYS_CCSRBAR_PHYS.  This macro is
 		used in assembly code, so it must not contain typecasts or
 		integer size suffixes (e.g. "ULL").
 
@@ -1541,7 +1733,7 @@ Low Level (hardware related) configuration options:
 		DO NOT CHANGE unless you know exactly what you're
 		doing! (11-4) [MPC8xx systems only]
 
-- CFG_SYS_INIT_RAM_ADDR:
+- CONFIG_SYS_INIT_RAM_ADDR:
 
 		Start address of memory area that can be used for
 		initial data and stack; please note that this must be
@@ -1559,6 +1751,21 @@ Low Level (hardware related) configuration options:
 - CONFIG_SYS_OR_TIMING_SDRAM:
 		SDRAM timing
 
+- CONFIG_SYS_MAMR_PTA:
+		periodic timer for refresh
+
+- CONFIG_SYS_SRIO:
+		Chip has SRIO or not
+
+- CONFIG_SRIO1:
+		Board has SRIO 1 port available
+
+- CONFIG_SRIO2:
+		Board has SRIO 2 port available
+
+- CONFIG_SRIO_PCIE_BOOT_MASTER
+		Board can support master function for Boot from SRIO and PCIE
+
 - CONFIG_SYS_SRIOn_MEM_VIRT:
 		Virtual Address of SRIO port 'n' memory region
 
@@ -1580,6 +1787,13 @@ Low Level (hardware related) configuration options:
 		Sets the EBC0_CFG register for the NDFC. If not defined
 		a default value will be used.
 
+- CONFIG_SPD_EEPROM
+		Get DDR timing information from an I2C EEPROM. Common
+		with pluggable memory modules such as SODIMMs
+
+  SPD_EEPROM_ADDRESS
+		I2C address of the SPD EEPROM
+
 - CONFIG_SYS_SPD_BUS_NUM
 		If SPD EEPROM is on an I2C bus other than the first
 		one, specify here. Note that the value must resolve
@@ -1652,6 +1866,11 @@ Low Level (hardware related) configuration options:
 		If defined, the x86 reset vector code is included. This is not
 		needed when U-Boot is running from Coreboot.
 
+- CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
+		Option to disable subpage write in NAND driver
+		driver that uses this:
+		drivers/mtd/nand/raw/davinci_nand.c
+
 Freescale QE/FMAN Firmware Support:
 -----------------------------------
 
@@ -2603,7 +2822,7 @@ locked as (mis-) used as memory, etc.
 	cause you grief during the initial boot! It is frequently not
 	used.
 
-	CFG_SYS_INIT_RAM_ADDR should be somewhere that won't interfere
+	CONFIG_SYS_INIT_RAM_ADDR should be somewhere that won't interfere
 	with your processor/board/system design. The default value
 	you will find in any recent u-boot distribution in
 	walnut.h should work for you. I'd set it to a value larger

api/Kconfig

@@ -5,28 +5,4 @@ config API
 	help
 	  This option enables the U-Boot API. See api/README for more information.
 
-config SYS_MMC_MAX_DEVICE
-	int  "Maximum number of MMC devices exposed via the API"
-	depends on API
-	default 1
-
 endmenu
-
-config STANDALONE_LOAD_ADDR
-	hex "Address in memory to link standalone applications to"
-	default 0xffffffff80200000 if MIPS && 64BIT
-	default 0x8c000000 if SH
-	default 0x82000000 if ARC
-	default 0x80f00000 if MICROBLAZE
-	default 0x80300000 if ARCH_OMAP2PLUS || FSL_LSCH2 || FSL_LSCH3
-	default 0x80200000 if MIPS && 32BIT
-	default 0x0c100000 if ARM
-	default 0x02000000 if NIOS2
-	default 0x00040000 if PPC || X86
-	default 0x00020000 if M68K
-	default 0x0 if RISCV
-	default SYS_LOAD_ADDR
-	help
-	  This option defines a board specific value for the address where
-	  standalone program gets loaded, thus overwriting the architecture
-	  dependent default settings.

api/api_storage.c

@@ -44,6 +44,10 @@ struct stor_spec {
 
 static struct stor_spec specs[ENUM_MAX] = { { 0, 0, 0, 0, NULL }, };
 
+#ifndef CONFIG_SYS_MMC_MAX_DEVICE
+#define CONFIG_SYS_MMC_MAX_DEVICE	1
+#endif
+
 void dev_stor_init(void)
 {
 #if defined(CONFIG_IDE)

arch/Kconfig

@@ -111,8 +111,9 @@ config RISCV
 	select SUPPORT_OF_CONTROL
 	select OF_CONTROL
 	select DM
-	imply SPL_SEPARATE_BSS if SPL
+	select SPL_SEPARATE_BSS if SPL
 	imply DM_SERIAL
+	imply DM_ETH
 	imply DM_EVENT
 	imply DM_MMC
 	imply DM_SPI
@@ -145,7 +146,6 @@ config SANDBOX
 	select DM_SPI
 	select DM_SPI_FLASH
 	select GZIP_COMPRESSED
-	select IO_TRACE
 	select LZO
 	select OF_BOARD_SETUP
 	select PCI_ENDPOINT
@@ -240,6 +240,7 @@ config X86
 	imply CMD_SF
 	imply CMD_SF_TEST
 	imply CMD_ZBOOT
+	imply DM_ETH
 	imply DM_EVENT
 	imply DM_GPIO
 	imply DM_KEYBOARD
@@ -380,15 +381,9 @@ config SYS_IMMR
 	  Address for the Internal Memory-Mapped Registers (IMMR) window used
 	  to configure the features of many Freescale / NXP SoCs.
 
-config MONITOR_IS_IN_RAM
-	bool "U-Boot is loaded in to RAM by a pre-loader"
-	depends on M68K || NIOS2
-
-menu "Skipping low level initialization functions"
-	depends on ARM || MIPS || RISCV
-
 config SKIP_LOWLEVEL_INIT
-	bool "Skip calls to certain low level initialization functions"
+	bool "Skip the calls to certain low level initialization functions"
+	depends on ARM || MIPS || RISCV
 	help
 	  If enabled, then certain low level initializations (like setting up
 	  the memory controller) are omitted and/or U-Boot does not relocate
@@ -398,8 +393,8 @@ config SKIP_LOWLEVEL_INIT
 	  debugger which performs these initializations itself.
 
 config SPL_SKIP_LOWLEVEL_INIT
-	bool "Skip calls to certain low level initialization functions in SPL"
+	bool "Skip the calls to certain low level initialization functions"
-	depends on SPL
+	depends on SPL && (ARM || MIPS || RISCV)
 	help
 	  If enabled, then certain low level initializations (like setting up
 	  the memory controller) are omitted and/or U-Boot does not relocate
@@ -409,7 +404,7 @@ config SPL_SKIP_LOWLEVEL_INIT
 	  debugger which performs these initializations itself.
 
 config TPL_SKIP_LOWLEVEL_INIT
-	bool "Skip calls to certain low level initialization functions in TPL"
+	bool "Skip the calls to certain low level initialization functions"
 	depends on SPL && ARM
 	help
 	  If enabled, then certain low level initializations (like setting up
@@ -420,7 +415,7 @@ config TPL_SKIP_LOWLEVEL_INIT
 	  debugger which performs these initializations itself.
 
 config SKIP_LOWLEVEL_INIT_ONLY
-	bool "Skip call to lowlevel_init during early boot ONLY"
+	bool "Skip the call to lowlevel_init during early boot ONLY"
 	depends on ARM
 	help
 	  This allows just the call to lowlevel_init() to be skipped. The
@@ -428,7 +423,7 @@ config SKIP_LOWLEVEL_INIT_ONLY
 	  performed.
 
 config SPL_SKIP_LOWLEVEL_INIT_ONLY
-	bool "Skip call to lowlevel_init during early SPL boot ONLY"
+	bool "Skip the call to lowlevel_init during early boot ONLY"
 	depends on SPL && ARM
 	help
 	  This allows just the call to lowlevel_init() to be skipped. The
@@ -436,39 +431,13 @@ config SPL_SKIP_LOWLEVEL_INIT_ONLY
 	  performed.
 
 config TPL_SKIP_LOWLEVEL_INIT_ONLY
-	bool "Skip call to lowlevel_init during early TPL boot ONLY"
+	bool "Skip the call to lowlevel_init during early boot ONLY"
 	depends on TPL && ARM
 	help
 	  This allows just the call to lowlevel_init() to be skipped. The
 	  normal CP15 init (such as enabling the instruction cache) is still
 	  performed.
 
-endmenu
-
-config SYS_HAS_NONCACHED_MEMORY
-	bool "Enable reserving a non-cached memory area for drivers"
-	depends on (ARM || MIPS) && (RTL8169 || MEDIATEK_ETH)
-	help
-	  This is useful for drivers that would otherwise require a lot of
-	  explicit cache maintenance. For some drivers it's also impossible to
-	  properly maintain the cache. For example if the regions that need to
-	  be flushed are not a multiple of the cache-line size, *and* padding
-	  cannot be allocated between the regions to align them (i.e.  if the
-	  HW requires a contiguous array of regions, and the size of each
-	  region is not cache-aligned), then a flush of one region may result
-	  in overwriting data that hardware has written to another region in
-	  the same cache-line. This can happen for example in network drivers
-	  where descriptors for buffers are typically smaller than the CPU
-	  cache-line (e.g.  16 bytes vs. 32 or 64 bytes).
-
-config SYS_NONCACHED_MEMORY
-	hex "Size in bytes of the non-cached memory area"
-	depends on SYS_HAS_NONCACHED_MEMORY
-	default 0x100000
-	help
-	  Size of non-cached memory area. This area of memory will be typically
-	  located right below the malloc() area and mapped uncached in the MMU.
-
 source "arch/arc/Kconfig"
 source "arch/arm/Kconfig"
 source "arch/m68k/Kconfig"
@@ -489,6 +458,7 @@ source "arch/Kconfig.nxp"
 endif
 
 source "board/keymile/Kconfig"
+source "board/sunxi/Kconfig"
 
 if MIPS || MICROBLAZE
 

arch/Kconfig.nxp

@@ -1,12 +1,5 @@
-menu "Functionality shared between NXP SoCs"
-
-config FSL_TRUST_ARCH_v1
-	bool
-
 config NXP_ESBC
 	bool "NXP ESBC (secure boot) functionality"
-	select FSL_TRUST_ARCH_v1 if ARCH_P3041 || ARCH_P4080 || \
-		ARCH_P5040 || ARCH_P2041
 	help
 	  Enable Freescale Secure Boot feature. Normally selected by defconfig.
 	  If unsure, do not change.
@@ -17,7 +10,6 @@ menu "Chain of trust / secure boot options"
 config CHAIN_OF_TRUST
 	select FSL_CAAM
 	select ARCH_MISC_INIT
-	select FSL_ISBC_KEY_EXT if (ARM || FSL_CORENET) && !SYS_RAMBOOT
 	select FSL_SEC_MON
 	select SPL_BOARD_INIT if (ARM && SPL)
 	select SPL_HASH if (ARM && SPL)
@@ -49,17 +41,6 @@ config ESBC_ADDR_64BIT
 	help
 	  For Layerscape based platforms, ESBC image Address in Header is 64bit.
 
-config FSL_ISBC_KEY_EXT
-	bool
-	help
-	  The key used for verification of next level images is picked up from
-	  an Extension Table which has been verified by the ISBC (Internal
-	  Secure boot Code) in boot ROM of the SoC.  The feature is only
-	  applicable in case of NOR boot and is not applicable in case of
-	  RAMBOOT (NAND, SD, SPI).  For Layerscape, this feature is available
-	  for all device if IE Table is copied to XIP memory Also, for
-	  Layerscape, ISBC doesn't verify this table.
-
 config SYS_FSL_SFP_BE
 	def_bool y
 	depends on PPC || FSL_LSCH2 || ARCH_LS1021A
@@ -144,6 +125,8 @@ config KEY_REVOCATION
 
 endmenu
 
+comment "Other functionality shared between NXP SoCs"
+
 config DEEP_SLEEP
 	bool "Enable SoC deep sleep feature"
 	depends on ARCH_T1024 || ARCH_T1040 || ARCH_T1042 || ARCH_LS1021A
@@ -268,8 +251,3 @@ config QIXIS_I2C_ACCESS
 config HAS_FSL_DR_USB
 	def_bool y
 	depends on USB_EHCI_HCD && PPC
-
-config SYS_DPAA_FMAN
-	bool
-
-endmenu

arch/arc/config.mk

@@ -21,3 +21,6 @@ PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections -fno-common
 
 # Needed for relocation
 LDFLAGS_FINAL += -pie --gc-sections
+
+# Load address for standalone apps
+CONFIG_STANDALONE_LOAD_ADDR ?= 0x82000000

arch/arc/lib/cache.c

@@ -476,9 +476,9 @@ static void __slc_rgn_op(unsigned long paddr, unsigned long sz, const int op)
 static void arc_ioc_setup(void)
 {
 	/* IOC Aperture start is equal to DDR start */
-	unsigned int ap_base = CFG_SYS_SDRAM_BASE;
+	unsigned int ap_base = CONFIG_SYS_SDRAM_BASE;
 	/* IOC Aperture size is equal to DDR size */
-	long ap_size = CFG_SYS_SDRAM_SIZE;
+	long ap_size = CONFIG_SYS_SDRAM_SIZE;
 
 	/* Unsupported configuration. See [ NOTE 2 ] for more details. */
 	if (!slc_exists())

arch/arc/lib/cpu.c

@@ -20,7 +20,7 @@ int arch_cpu_init(void)
 	timer_init();
 
 	gd->cpu_clk = get_board_sys_clk();
-	gd->ram_size = CFG_SYS_SDRAM_SIZE;
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
 
 	cache_init();
 

arch/arm/Kconfig

@@ -413,6 +413,52 @@ config ARM_SMCCC
 	  This should be enabled if U-Boot needs to communicate with system
 	  firmware (for example, PSCI) according to SMCCC.
 
+config SEMIHOSTING
+	bool "Support ARM semihosting"
+	help
+	  Semihosting is a method for a target to communicate with a host
+	  debugger. It uses special instructions which the debugger will trap
+	  on and interpret. This allows U-Boot to read/write files, print to
+	  the console, and execute arbitrary commands on the host system.
+
+	  Enabling this option will add support for reading and writing files
+	  on the host system. If you don't have a debugger attached then trying
+	  to do this will likely cause U-Boot to hang. Say 'n' if you are unsure.
+
+config SEMIHOSTING_FALLBACK
+	bool "Recover gracefully when semihosting fails"
+	depends on SEMIHOSTING && ARM64
+	default y
+	help
+	  Normally, if U-Boot makes a semihosting call and no debugger is
+	  attached, then it will panic due to a synchronous abort
+	  exception. This config adds an exception handler which will allow
+	  U-Boot to recover. Say 'y' if unsure.
+
+config SPL_SEMIHOSTING
+	bool "Support ARM semihosting in SPL"
+	depends on SPL
+	help
+	  Semihosting is a method for a target to communicate with a host
+	  debugger. It uses special instructions which the debugger will trap
+	  on and interpret. This allows U-Boot to read/write files, print to
+	  the console, and execute arbitrary commands on the host system.
+
+	  Enabling this option will add support for reading and writing files
+	  on the host system. If you don't have a debugger attached then trying
+	  to do this will likely cause U-Boot to hang. Say 'n' if you are unsure.
+
+config SPL_SEMIHOSTING_FALLBACK
+	bool "Recover gracefully when semihosting fails in SPL"
+	depends on SPL_SEMIHOSTING && ARM64
+	select ARMV8_SPL_EXCEPTION_VECTORS
+	default y
+	help
+	  Normally, if U-Boot makes a semihosting call and no debugger is
+	  attached, then it will panic due to a synchronous abort
+	  exception. This config adds an exception handler which will allow
+	  U-Boot to recover. Say 'y' if unsure.
+
 config SYS_THUMB_BUILD
 	bool "Build U-Boot using the Thumb instruction set"
 	depends on !ARM64
@@ -553,9 +599,6 @@ config ARM64_SUPPORT_AARCH32
 	help
 	  This ARM64 system supports AArch32 execution state.
 
-config IPROC
-	bool
-
 config S5P
 	def_bool y if ARCH_EXYNOS || ARCH_S5PC1XX
 
@@ -589,6 +632,7 @@ config ARCH_KIRKWOOD
 config ARCH_MVEBU
 	bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)"
 	select DM
+	select DM_ETH
 	select DM_SERIAL
 	select DM_SPI
 	select DM_SPI_FLASH
@@ -596,7 +640,7 @@ config ARCH_MVEBU
 	select SPL_DM_SPI if SPL
 	select SPL_DM_SPI_FLASH if SPL
 	select SPL_TIMER if SPL
-	select TIMER if !ARM64
+	select TIMER
 	select OF_CONTROL
 	select OF_SEPARATE
 	select SPI
@@ -661,7 +705,6 @@ config TARGET_BCMCYGNUS
 	bool "Support bcmcygnus"
 	select CPU_V7A
 	select GPIO_EXTRA_HEADER
-	select IPROC
 	imply BCM_SF2_ETH
 	imply BCM_SF2_ETH_GMAC
 	imply CMD_HASH
@@ -693,6 +736,7 @@ config ARCH_EXYNOS
 	select DM
 	select DM_GPIO
 	select DM_I2C
+	select DM_ETH
 	select DM_KEYBOARD
 	select DM_SERIAL
 	select DM_SPI
@@ -723,9 +767,8 @@ config ARCH_HIGHBANK
 	select CLK
 	select CLK_CCF
 	select AHCI
+	select DM_ETH
 	select PHYS_64BIT
-	select TIMER
-	select SP804_TIMER
 	imply OF_HAS_PRIOR_STAGE
 
 config ARCH_INTEGRATOR
@@ -919,7 +962,6 @@ config ARCH_MX7
 	select CPU_V7A
 	select GPIO_EXTRA_HEADER
 	select MACH_IMX
-	select MXC_GPT_HCLK
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_COMPAT_4
 	select SYS_FSL_SEC_LE
@@ -933,7 +975,6 @@ config ARCH_MX6
 	select CPU_V7A
 	select GPIO_EXTRA_HEADER
 	select MACH_IMX
-	select MXC_GPT_HCLK
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_COMPAT_4
 	select SYS_FSL_SEC_LE
@@ -998,6 +1039,7 @@ config ARCH_APPLE
 config ARCH_OWL
 	bool "Actions Semi OWL SoCs"
 	select DM
+	select DM_ETH
 	select DM_SERIAL
 	select GPIO_EXTRA_HEADER
 	select OWL_SERIAL
@@ -1091,59 +1133,17 @@ config ARCH_SOCFPGA
 
 config ARCH_SUNXI
 	bool "Support sunxi (Allwinner) SoCs"
-	select BINMAN
+	select BOARD_SUNXI
-	select CMD_GPIO
-	select CMD_MMC if MMC
-	select CMD_USB if DISTRO_DEFAULTS && USB_HOST
-	select CLK
-	select DM
-	select DM_GPIO
-	select DM_I2C if I2C
-	select DM_SPI if SPI
-	select DM_SPI_FLASH if SPI
-	select DM_KEYBOARD
-	select DM_MMC if MMC
-	select DM_SCSI if SCSI
-	select DM_SERIAL
 	select GPIO_EXTRA_HEADER
-	select OF_BOARD_SETUP
 	select OF_CONTROL
 	select OF_SEPARATE
-	select PINCTRL
+	select SPECIFY_CONSOLE_INDEX if SERIAL
-	select SPECIFY_CONSOLE_INDEX
-	select SPL_SEPARATE_BSS if SPL
 	select SPL_STACK_R if SPL
 	select SPL_SYS_MALLOC_SIMPLE if SPL
 	select SPL_SYS_THUMB_BUILD if !ARM64
-	select SUNXI_GPIO
-	select SYS_NS16550
 	select SYS_THUMB_BUILD if !ARM64
-	select USB if DISTRO_DEFAULTS
-	select USB_KEYBOARD if DISTRO_DEFAULTS && USB_HOST
-	select USB_STORAGE if DISTRO_DEFAULTS && USB_HOST
 	select SPL_USE_TINY_PRINTF
-	select USE_PREBOOT
+	imply SPL_LOAD_FIT
-	select SYS_RELOC_GD_ENV_ADDR
-	imply BOARD_LATE_INIT
-	imply CMD_DM
-	imply CMD_GPT
-	imply CMD_UBI if MTD_RAW_NAND
-	imply DISTRO_DEFAULTS
-	imply FAT_WRITE
-	imply FIT
-	imply OF_LIBFDT_OVERLAY
-	imply PRE_CONSOLE_BUFFER
-	imply SPL_GPIO
-	imply SPL_LIBCOMMON_SUPPORT
-	imply SPL_LIBGENERIC_SUPPORT
-	imply SPL_MMC if MMC
-	imply SPL_POWER
-	imply SPL_SERIAL
-	imply SYSRESET
-	imply SYSRESET_WATCHDOG
-	imply SYSRESET_WATCHDOG_AUTO
-	imply USB_GADGET
-	imply WDT
 
 config ARCH_U8500
 	bool "ST-Ericsson U8500 Series"
@@ -1175,6 +1175,7 @@ config ARCH_VERSAL
 	select ARM64
 	select CLK
 	select DM
+	select DM_ETH if NET
 	select DM_MMC if MMC
 	select DM_SERIAL
 	select GICV3
@@ -1184,10 +1185,11 @@ config ARCH_VERSAL
 	imply ENV_VARS_UBOOT_RUNTIME_CONFIG
 
 config ARCH_VERSAL_NET
-	bool "Support Xilinx Versal NET Platform"
+	bool "Support Xilinx Keystone Platform"
 	select ARM64
 	select CLK
 	select DM
+	select DM_ETH if NET
 	select DM_MMC if MMC
 	select DM_SERIAL
 	select OF_CONTROL
@@ -1198,7 +1200,6 @@ config ARCH_VF610
 	bool "Freescale Vybrid"
 	select CPU_V7A
 	select GPIO_EXTRA_HEADER
-	select IOMUX_SHARE_CONF_REG
 	select MACH_IMX
 	select SYS_FSL_ERRATUM_ESDHC111
 	imply CMD_MTDPARTS
@@ -1212,6 +1213,7 @@ config ARCH_ZYNQ
 	select CPU_V7A
 	select DEBUG_UART_BOARD_INIT if SPL && DEBUG_UART
 	select DM
+	select DM_ETH if NET
 	select DM_MMC if MMC
 	select DM_SERIAL
 	select DM_SPI
@@ -1241,6 +1243,7 @@ config ARCH_ZYNQMP_R5
 	select CLK
 	select CPU_V7R
 	select DM
+	select DM_ETH if NET
 	select DM_MMC if MMC
 	select DM_SERIAL
 	select OF_CONTROL
@@ -1253,7 +1256,8 @@ config ARCH_ZYNQMP
 	select CLK
 	select DM
 	select DEBUG_UART_BOARD_INIT if SPL && DEBUG_UART
-	imply DM_MAILBOX
+	select DM_ETH if NET
+	select DM_MAILBOX
 	select DM_MMC if MMC
 	select DM_SERIAL
 	select DM_SPI if SPI
@@ -1270,7 +1274,7 @@ config ARCH_ZYNQMP
 	imply SPL_FIRMWARE if SPL
 	select SPL_SEPARATE_BSS if SPL
 	select SUPPORT_SPL
-	imply ZYNQMP_IPI if DM_MAILBOX
+	select ZYNQMP_IPI
 	select SOC_DEVICE
 	imply BOARD_LATE_INIT
 	imply CMD_DM
@@ -1603,7 +1607,6 @@ config TARGET_LS1021AQDS
 	select CPU_V7_HAS_NONSEC
 	select CPU_V7_HAS_VIRT
 	select LS1_DEEP_SLEEP
-	select PEN_ADDR_BIG_ENDIAN
 	select SUPPORT_SPL
 	select SYS_FSL_DDR
 	select FSL_DDR_INTERACTIVE
@@ -1622,7 +1625,6 @@ config TARGET_LS1021ATWR
 	select CPU_V7_HAS_NONSEC
 	select CPU_V7_HAS_VIRT
 	select LS1_DEEP_SLEEP
-	select PEN_ADDR_BIG_ENDIAN
 	select SUPPORT_SPL
 	select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
 	select GPIO_EXTRA_HEADER
@@ -1687,7 +1689,6 @@ config TARGET_LS1021AIOT
 	select CPU_V7A
 	select CPU_V7_HAS_NONSEC
 	select CPU_V7_HAS_VIRT
-	select PEN_ADDR_BIG_ENDIAN
 	select SUPPORT_SPL
 	select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
 	select GPIO_EXTRA_HEADER
@@ -1802,6 +1803,7 @@ config TARGET_SL28
 	select DM_I2C
 	select DM_MMC
 	select DM_SPI_FLASH
+	select DM_ETH
 	select DM_MDIO
 	select PCI
 	select DM_RNG
@@ -1838,6 +1840,7 @@ config ARCH_UNIPHIER
 	bool "Socionext UniPhier SoCs"
 	select BOARD_LATE_INIT
 	select DM
+	select DM_ETH
 	select DM_GPIO
 	select DM_I2C
 	select DM_MMC
@@ -2023,6 +2026,7 @@ config TARGET_POMELO
 	select SCSI
 	select DM_SCSI
 	select DM_SERIAL
+	select DM_ETH if NET
 	imply CMD_PCI
 	help
 	   Support for pomelo platform.
@@ -2292,7 +2296,6 @@ source "board/hisilicon/poplar/Kconfig"
 source "board/isee/igep003x/Kconfig"
 source "board/kontron/sl28/Kconfig"
 source "board/myir/mys_6ulx/Kconfig"
-source "board/samsung/common/Kconfig"
 source "board/siemens/common/Kconfig"
 source "board/seeed/npi_imx6ull/Kconfig"
 source "board/socionext/developerbox/Kconfig"

arch/arm/config.mk

@@ -3,6 +3,14 @@
 # (C) Copyright 2000-2002
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 
+ifndef CONFIG_STANDALONE_LOAD_ADDR
+ifneq ($(CONFIG_ARCH_OMAP2PLUS),)
+CONFIG_STANDALONE_LOAD_ADDR = 0x80300000
+else
+CONFIG_STANDALONE_LOAD_ADDR = 0xc100000
+endif
+endif
+
 CFLAGS_NON_EFI := -fno-pic -ffixed-r9 -ffunction-sections -fdata-sections \
 		  -fstack-protector-strong
 CFLAGS_EFI := -fpic -fshort-wchar

arch/arm/cpu/arm1176/start.S

@@ -18,7 +18,7 @@
 #include <linux/linkage.h>
 
 #ifndef CONFIG_SYS_PHY_UBOOT_BASE
-#define CONFIG_SYS_PHY_UBOOT_BASE	CFG_SYS_UBOOT_BASE
+#define CONFIG_SYS_PHY_UBOOT_BASE	CONFIG_SYS_UBOOT_BASE
 #endif
 
 /*

arch/arm/cpu/arm920t/imx/Makefile

@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	+= generic.o
+obj-y	+= speed.o
+obj-y	+= timer.o

arch/arm/cpu/arm920t/imx/generic.c

@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  arch/arm/mach-imx/generic.c
+ *
+ *  author: Sascha Hauer
+ *  Created: april 20th, 2004
+ *  Copyright: Synertronixx GmbH
+ *
+ *  Common code for i.MX machines
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_IMX
+
+#include <asm/arch/imx-regs.h>
+
+void imx_gpio_mode(int gpio_mode)
+{
+	unsigned int pin = gpio_mode & GPIO_PIN_MASK;
+	unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> 5;
+	unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> 10;
+	unsigned int tmp;
+
+	/* Pullup enable */
+	if(gpio_mode & GPIO_PUEN)
+		PUEN(port) |= (1<<pin);
+	else
+		PUEN(port) &= ~(1<<pin);
+
+	/* Data direction */
+	if(gpio_mode & GPIO_OUT)
+		DDIR(port) |= 1<<pin;
+	else
+		DDIR(port) &= ~(1<<pin);
+
+	/* Primary / alternate function */
+	if(gpio_mode & GPIO_AF)
+		GPR(port) |= (1<<pin);
+	else
+		GPR(port) &= ~(1<<pin);
+
+	/* use as gpio? */
+	if( ocr == 3 )
+		GIUS(port) |= (1<<pin);
+	else
+		GIUS(port) &= ~(1<<pin);
+
+	/* Output / input configuration */
+	/* FIXME: I'm not very sure about OCR and ICONF, someone
+	 * should have a look over it
+	 */
+	if(pin<16) {
+		tmp = OCR1(port);
+		tmp &= ~( 3<<(pin*2));
+		tmp |= (ocr << (pin*2));
+		OCR1(port) = tmp;
+
+		if( gpio_mode &	GPIO_AOUT )
+			ICONFA1(port) &= ~( 3<<(pin*2));
+		if( gpio_mode &	GPIO_BOUT )
+			ICONFB1(port) &= ~( 3<<(pin*2));
+	} else {
+		tmp = OCR2(port);
+		tmp &= ~( 3<<((pin-16)*2));
+		tmp |= (ocr << ((pin-16)*2));
+		OCR2(port) = tmp;
+
+		if( gpio_mode &	GPIO_AOUT )
+			ICONFA2(port) &= ~( 3<<((pin-16)*2));
+		if( gpio_mode &	GPIO_BOUT )
+			ICONFB2(port) &= ~( 3<<((pin-16)*2));
+	}
+}
+
+#endif /* CONFIG_IMX */

arch/arm/cpu/arm920t/imx/speed.c

@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *
+ * (c) 2004 Sascha Hauer <sascha@saschahauer.de>
+ */
+
+
+#include <common.h>
+#if defined (CONFIG_IMX)
+#include <clock_legacy.h>
+
+#include <asm/arch/imx-regs.h>
+
+/* ------------------------------------------------------------------------- */
+/* NOTE: This describes the proper use of this file.
+ *
+ * get_board_sys_clk() should be defined as the input frequency of the PLL.
+ * SH FIXME: 16780000 in our case
+ * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
+ * the specified bus in HZ.
+ */
+/* ------------------------------------------------------------------------- */
+
+ulong get_systemPLLCLK(void)
+{
+	/* FIXME: We assume System_SEL = 0 here */
+	u32 spctl0 = SPCTL0;
+	u32 mfi = (spctl0 >> 10) & 0xf;
+	u32 mfn = spctl0 & 0x3f;
+	u32 mfd = (spctl0 >> 16) & 0x3f;
+	u32 pd =  (spctl0 >> 26) & 0xf;
+
+	mfi = mfi<=5 ? 5 : mfi;
+
+	return (2*(CONFIG_SYSPLL_CLK_FREQ>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1);
+}
+
+ulong get_mcuPLLCLK(void)
+{
+	/* FIXME: We assume System_SEL = 0 here */
+	u32 mpctl0 = MPCTL0;
+	u32 mfi = (mpctl0 >> 10) & 0xf;
+	u32 mfn = mpctl0 & 0x3f;
+	u32 mfd = (mpctl0 >> 16) & 0x3f;
+	u32 pd =  (mpctl0 >> 26) & 0xf;
+
+	mfi = mfi<=5 ? 5 : mfi;
+
+	return (2*(get_board_sys_clk()>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1);
+}
+
+ulong get_FCLK(void)
+{
+	return (( CSCR>>15)&1) ? get_mcuPLLCLK()>>1 : get_mcuPLLCLK();
+}
+
+/* return HCLK frequency */
+ulong get_HCLK(void)
+{
+	u32 bclkdiv = (( CSCR >> 10 ) & 0xf) + 1;
+	printf("bclkdiv: %d\n", bclkdiv);
+	return get_systemPLLCLK() / bclkdiv;
+}
+
+/* return BCLK frequency */
+ulong get_BCLK(void)
+{
+	return get_HCLK();
+}
+
+ulong get_PERCLK1(void)
+{
+	return get_systemPLLCLK() / (((PCDR) & 0xf)+1);
+}
+
+ulong get_PERCLK2(void)
+{
+	return get_systemPLLCLK() / (((PCDR>>4) & 0xf)+1);
+}
+
+ulong get_PERCLK3(void)
+{
+	return get_systemPLLCLK() / (((PCDR>>16) & 0x7f)+1);
+}
+
+#endif /* defined (CONFIG_IMX) */

arch/arm/cpu/arm920t/imx/timer.c

@@ -0,0 +1,100 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <time.h>
+#if defined (CONFIG_IMX)
+
+#include <asm/arch/imx-regs.h>
+#include <linux/delay.h>
+
+int timer_init (void)
+{
+	int i;
+	/* setup GP Timer 1 */
+	TCTL1 = TCTL_SWR;
+	for ( i=0; i<100; i++) TCTL1 = 0; /* We have no udelay by now */
+	TPRER1 = get_PERCLK1() / 1000000; /* 1 MHz */
+	TCTL1 |= TCTL_FRR | (1<<1); /* Freerun Mode, PERCLK1 input */
+
+	/* Reset the timer */
+	TCTL1 &= ~TCTL_TEN;
+	TCTL1 |= TCTL_TEN; /* Enable timer */
+
+	return (0);
+}
+
+/*
+ * timer without interrupts
+ */
+static ulong get_timer_masked (void)
+{
+	return TCN1;
+}
+
+ulong get_timer (ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+void __udelay(unsigned long usec)
+{
+	ulong endtime = get_timer_masked() + usec;
+	signed long diff;
+
+	do {
+		ulong now = get_timer_masked ();
+		diff = endtime - now;
+	} while (diff >= 0);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	return CONFIG_SYS_HZ;
+}
+
+/*
+ * Reset the cpu by setting up the watchdog timer and let him time out
+ */
+void reset_cpu(void)
+{
+	/* Disable watchdog and set Time-Out field to 0 */
+	WCR = 0x00000000;
+
+	/* Write Service Sequence */
+	WSR = 0x00005555;
+	WSR = 0x0000AAAA;
+
+	/* Enable watchdog */
+	WCR = 0x00000001;
+
+	while (1);
+	/*NOTREACHED*/
+}
+
+#endif /* defined (CONFIG_IMX) */

arch/arm/cpu/arm926ejs/Makefile

@@ -12,6 +12,7 @@ extra-y	:=
 endif
 endif
 
+obj-$(CONFIG_MX27) += mx27/
 obj-$(if $(filter mxs,$(SOC)),y) += mxs/
 obj-$(if $(filter spear,$(SOC)),y) += spear/
 obj-$(CONFIG_ARCH_SUNXI) += sunxi/

arch/arm/cpu/arm926ejs/mx27/Makefile

@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+
+obj-y	+= generic.o timer.o reset.o relocate.o

arch/arm/cpu/arm926ejs/mx27/generic.c

@@ -0,0 +1,378 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  Copyright (c) 2008 Eric Jarrige <eric.jarrige@armadeus.org>
+ *  Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
+ */
+
+#include <common.h>
+#include <div64.h>
+#include <net.h>
+#include <netdev.h>
+#include <vsprintf.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/mach-imx/sys_proto.h>
+#ifdef CONFIG_MMC_MXC
+#include <asm/arch/mxcmmc.h>
+#endif
+
+/*
+ *  get the system pll clock in Hz
+ *
+ *                  mfi + mfn / (mfd +1)
+ *  f = 2 * f_ref * --------------------
+ *                        pd + 1
+ */
+static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
+{
+	unsigned int mfi = (pll >> 10) & 0xf;
+	unsigned int mfn = pll & 0x3ff;
+	unsigned int mfd = (pll >> 16) & 0x3ff;
+	unsigned int pd =  (pll >> 26) & 0xf;
+
+	mfi = mfi <= 5 ? 5 : mfi;
+
+	return lldiv(2 * (u64)f_ref * (mfi * (mfd + 1) + mfn),
+			(mfd + 1) * (pd + 1));
+}
+
+static ulong clk_in_32k(void)
+{
+	return 1024 * CONFIG_MX27_CLK32;
+}
+
+static ulong clk_in_26m(void)
+{
+	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
+
+	if (readl(&pll->cscr) & CSCR_OSC26M_DIV1P5) {
+		/* divide by 1.5 */
+		return 26000000 * 2 / 3;
+	} else {
+		return 26000000;
+	}
+}
+
+static ulong imx_get_mpllclk(void)
+{
+	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
+	ulong cscr = readl(&pll->cscr);
+	ulong fref;
+
+	if (cscr & CSCR_MCU_SEL)
+		fref = clk_in_26m();
+	else
+		fref = clk_in_32k();
+
+	return imx_decode_pll(readl(&pll->mpctl0), fref);
+}
+
+static ulong imx_get_armclk(void)
+{
+	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
+	ulong cscr = readl(&pll->cscr);
+	ulong fref = imx_get_mpllclk();
+	ulong div;
+
+	if (!(cscr & CSCR_ARM_SRC_MPLL))
+		fref = lldiv((fref * 2), 3);
+
+	div = ((cscr >> 12) & 0x3) + 1;
+
+	return lldiv(fref, div);
+}
+
+static ulong imx_get_ahbclk(void)
+{
+	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
+	ulong cscr = readl(&pll->cscr);
+	ulong fref = imx_get_mpllclk();
+	ulong div;
+
+	div = ((cscr >> 8) & 0x3) + 1;
+
+	return lldiv(fref * 2, 3 * div);
+}
+
+static __attribute__((unused)) ulong imx_get_spllclk(void)
+{
+	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
+	ulong cscr = readl(&pll->cscr);
+	ulong fref;
+
+	if (cscr & CSCR_SP_SEL)
+		fref = clk_in_26m();
+	else
+		fref = clk_in_32k();
+
+	return imx_decode_pll(readl(&pll->spctl0), fref);
+}
+
+static ulong imx_decode_perclk(ulong div)
+{
+	return lldiv((imx_get_mpllclk() * 2), (div * 3));
+}
+
+static ulong imx_get_perclk1(void)
+{
+	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
+
+	return imx_decode_perclk((readl(&pll->pcdr1) & 0x3f) + 1);
+}
+
+static ulong imx_get_perclk2(void)
+{
+	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
+
+	return imx_decode_perclk(((readl(&pll->pcdr1) >> 8) & 0x3f) + 1);
+}
+
+static __attribute__((unused)) ulong imx_get_perclk3(void)
+{
+	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
+
+	return imx_decode_perclk(((readl(&pll->pcdr1) >> 16) & 0x3f) + 1);
+}
+
+static __attribute__((unused)) ulong imx_get_perclk4(void)
+{
+	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
+
+	return imx_decode_perclk(((readl(&pll->pcdr1) >> 24) & 0x3f) + 1);
+}
+
+unsigned int mxc_get_clock(enum mxc_clock clk)
+{
+	switch (clk) {
+	case MXC_ARM_CLK:
+		return imx_get_armclk();
+	case MXC_I2C_CLK:
+		return imx_get_ahbclk()/2;
+	case MXC_UART_CLK:
+		return imx_get_perclk1();
+	case MXC_FEC_CLK:
+		return imx_get_ahbclk();
+	case MXC_ESDHC_CLK:
+		return imx_get_perclk2();
+	}
+	return -1;
+}
+
+
+u32 get_cpu_rev(void)
+{
+	return MXC_CPU_MX27 << 12;
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo (void)
+{
+	char buf[32];
+
+	printf("CPU:   Freescale i.MX27 at %s MHz\n\n",
+			strmhz(buf, imx_get_mpllclk()));
+	return 0;
+}
+#endif
+
+int cpu_eth_init(struct bd_info *bis)
+{
+#if defined(CONFIG_FEC_MXC)
+	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
+
+	/* enable FEC clock */
+	writel(readl(&pll->pccr1) | PCCR1_HCLK_FEC, &pll->pccr1);
+	writel(readl(&pll->pccr0) | PCCR0_FEC_EN, &pll->pccr0);
+	return fecmxc_initialize(bis);
+#else
+	return 0;
+#endif
+}
+
+/*
+ * Initializes on-chip MMC controllers.
+ * to override, implement board_mmc_init()
+ */
+int cpu_mmc_init(struct bd_info *bis)
+{
+#ifdef CONFIG_MMC_MXC
+	return mxc_mmc_init(bis);
+#else
+	return 0;
+#endif
+}
+
+void imx_gpio_mode(int gpio_mode)
+{
+	struct gpio_port_regs *regs = (struct gpio_port_regs *)IMX_GPIO_BASE;
+	unsigned int pin = gpio_mode & GPIO_PIN_MASK;
+	unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
+	unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT;
+	unsigned int aout = (gpio_mode & GPIO_AOUT_MASK) >> GPIO_AOUT_SHIFT;
+	unsigned int bout = (gpio_mode & GPIO_BOUT_MASK) >> GPIO_BOUT_SHIFT;
+	unsigned int tmp;
+
+	/* Pullup enable */
+	if (gpio_mode & GPIO_PUEN) {
+		writel(readl(&regs->port[port].puen) | (1 << pin),
+				&regs->port[port].puen);
+	} else {
+		writel(readl(&regs->port[port].puen) & ~(1 << pin),
+				&regs->port[port].puen);
+	}
+
+	/* Data direction */
+	if (gpio_mode & GPIO_OUT) {
+		writel(readl(&regs->port[port].gpio_dir) | 1 << pin,
+				&regs->port[port].gpio_dir);
+	} else {
+		writel(readl(&regs->port[port].gpio_dir) & ~(1 << pin),
+				&regs->port[port].gpio_dir);
+	}
+
+	/* Primary / alternate function */
+	if (gpio_mode & GPIO_AF) {
+		writel(readl(&regs->port[port].gpr) | (1 << pin),
+				&regs->port[port].gpr);
+	} else {
+		writel(readl(&regs->port[port].gpr) & ~(1 << pin),
+				&regs->port[port].gpr);
+	}
+
+	/* use as gpio? */
+	if (!(gpio_mode & (GPIO_PF | GPIO_AF))) {
+		writel(readl(&regs->port[port].gius) | (1 << pin),
+				&regs->port[port].gius);
+	} else {
+		writel(readl(&regs->port[port].gius) & ~(1 << pin),
+				&regs->port[port].gius);
+	}
+
+	/* Output / input configuration */
+	if (pin < 16) {
+		tmp = readl(&regs->port[port].ocr1);
+		tmp &= ~(3 << (pin * 2));
+		tmp |= (ocr << (pin * 2));
+		writel(tmp, &regs->port[port].ocr1);
+
+		writel(readl(&regs->port[port].iconfa1) & ~(3 << (pin * 2)),
+				&regs->port[port].iconfa1);
+		writel(readl(&regs->port[port].iconfa1) | aout << (pin * 2),
+				&regs->port[port].iconfa1);
+		writel(readl(&regs->port[port].iconfb1) & ~(3 << (pin * 2)),
+				&regs->port[port].iconfb1);
+		writel(readl(&regs->port[port].iconfb1) | bout << (pin * 2),
+				&regs->port[port].iconfb1);
+	} else {
+		pin -= 16;
+
+		tmp = readl(&regs->port[port].ocr2);
+		tmp &= ~(3 << (pin * 2));
+		tmp |= (ocr << (pin * 2));
+		writel(tmp, &regs->port[port].ocr2);
+
+		writel(readl(&regs->port[port].iconfa2) & ~(3 << (pin * 2)),
+				&regs->port[port].iconfa2);
+		writel(readl(&regs->port[port].iconfa2) | aout << (pin * 2),
+				&regs->port[port].iconfa2);
+		writel(readl(&regs->port[port].iconfb2) & ~(3 << (pin * 2)),
+				&regs->port[port].iconfb2);
+		writel(readl(&regs->port[port].iconfb2) | bout << (pin * 2),
+				&regs->port[port].iconfb2);
+	}
+}
+
+#ifdef CONFIG_MXC_UART
+void mx27_uart1_init_pins(void)
+{
+	int i;
+	unsigned int mode[] = {
+		PE12_PF_UART1_TXD,
+		PE13_PF_UART1_RXD,
+	};
+
+	for (i = 0; i < ARRAY_SIZE(mode); i++)
+		imx_gpio_mode(mode[i]);
+
+}
+#endif /* CONFIG_MXC_UART */
+
+#ifdef CONFIG_FEC_MXC
+void mx27_fec_init_pins(void)
+{
+	int i;
+	unsigned int mode[] = {
+		PD0_AIN_FEC_TXD0,
+		PD1_AIN_FEC_TXD1,
+		PD2_AIN_FEC_TXD2,
+		PD3_AIN_FEC_TXD3,
+		PD4_AOUT_FEC_RX_ER,
+		PD5_AOUT_FEC_RXD1,
+		PD6_AOUT_FEC_RXD2,
+		PD7_AOUT_FEC_RXD3,
+		PD8_AF_FEC_MDIO,
+		PD9_AIN_FEC_MDC | GPIO_PUEN,
+		PD10_AOUT_FEC_CRS,
+		PD11_AOUT_FEC_TX_CLK,
+		PD12_AOUT_FEC_RXD0,
+		PD13_AOUT_FEC_RX_DV,
+		PD14_AOUT_FEC_CLR,
+		PD15_AOUT_FEC_COL,
+		PD16_AIN_FEC_TX_ER,
+		PF23_AIN_FEC_TX_EN,
+	};
+
+	for (i = 0; i < ARRAY_SIZE(mode); i++)
+		imx_gpio_mode(mode[i]);
+}
+
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
+{
+	int i;
+	struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
+	struct fuse_bank *bank = &iim->bank[0];
+	struct fuse_bank0_regs *fuse =
+			(struct fuse_bank0_regs *)bank->fuse_regs;
+
+	for (i = 0; i < 6; i++)
+		mac[6 - 1 - i] = readl(&fuse->mac_addr[i]) & 0xff;
+}
+#endif /* CONFIG_FEC_MXC */
+
+#ifdef CONFIG_MMC_MXC
+void mx27_sd1_init_pins(void)
+{
+	int i;
+	unsigned int mode[] = {
+		PE18_PF_SD1_D0,
+		PE19_PF_SD1_D1,
+		PE20_PF_SD1_D2,
+		PE21_PF_SD1_D3,
+		PE22_PF_SD1_CMD,
+		PE23_PF_SD1_CLK,
+	};
+
+	for (i = 0; i < ARRAY_SIZE(mode); i++)
+		imx_gpio_mode(mode[i]);
+
+}
+
+void mx27_sd2_init_pins(void)
+{
+	int i;
+	unsigned int mode[] = {
+		PB4_PF_SD2_D0,
+		PB5_PF_SD2_D1,
+		PB6_PF_SD2_D2,
+		PB7_PF_SD2_D3,
+		PB8_PF_SD2_CMD,
+		PB9_PF_SD2_CLK,
+	};
+
+	for (i = 0; i < ARRAY_SIZE(mode); i++)
+		imx_gpio_mode(mode[i]);
+
+}
+#endif /* CONFIG_MMC_MXC */

arch/arm/cpu/arm926ejs/mx27/relocate.S

@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  relocate - i.MX27-specific vector relocation
+ *
+ *  Copyright (c) 2013  Albert ARIBAUD <albert.u.boot@aribaud.net>
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <linux/linkage.h>
+
+/*
+ * The i.MX27 SoC is very specific with respect to exceptions: it
+ * does not provide RAM at the high vectors address (0xFFFF0000),
+ * thus only the low address (0x00000000) is useable; but that is
+ * in ROM. Therefore, vectors cannot be changed at all.
+ *
+ * However, these ROM-based vectors actually just perform indirect
+ * calls through pointers located in RAM at SoC-specific addresses,
+ * as follows:
+ *
+ * Offset      Exception              Use by ROM code
+ * 0x00000000  reset                  indirect branch to [0x00000014]
+ * 0x00000004  undefined instruction  indirect branch to [0xfffffef0]
+ * 0x00000008  software interrupt     indirect branch to [0xfffffef4]
+ * 0x0000000c  prefetch abort         indirect branch to [0xfffffef8]
+ * 0x00000010  data abort             indirect branch to [0xfffffefc]
+ * 0x00000014  (reserved in ARMv5)    vector to ROM reset: 0xc0000000
+ * 0x00000018  IRQ                    indirect branch to [0xffffff00]
+ * 0x0000001c  FIQ                    indirect branch to [0xffffff04]
+ *
+ * In order to initialize exceptions on i.MX27, we must copy U-Boot's
+ * indirect (not exception!) vector table into 0xfffffef0..0xffffff04
+ * taking care not to copy vectors number 5 (reserved exception).
+ */
+
+	.section	.text.relocate_vectors,"ax",%progbits
+
+ENTRY(relocate_vectors)
+
+	ldr	r0, [r9, #GD_RELOCADDR]	/* r0 = gd->relocaddr */
+	ldr	r1, =32			/* size of vector table */
+	add	r0, r0, r1		/* skip to indirect table */
+	ldr	r1, =0xFFFFFEF0		/* i.MX27 indirect table */
+	ldmia	r0!, {r2-r8}		/* load indirect vectors 1..7 */
+	stmia	r1!, {r2-r5, r7,r8}	/* write all but vector 5 */
+
+	bx	lr
+
+ENDPROC(relocate_vectors)

arch/arm/cpu/arm926ejs/mx27/reset.c

@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * (C) Copyright 2009
+ * Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+
+/*
+ * Reset the cpu by setting up the watchdog timer and let it time out
+ */
+void reset_cpu(void)
+{
+	struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE;
+	/* Disable watchdog and set Time-Out field to 0 */
+	writew(0x0000, &regs->wcr);
+
+	/* Write Service Sequence */
+	writew(0x5555, &regs->wsr);
+	writew(0xAAAA, &regs->wsr);
+
+	/* Enable watchdog */
+	writew(WCR_WDE, &regs->wcr);
+
+	while (1);
+	/*NOTREACHED*/
+}

arch/arm/cpu/arm926ejs/mx27/timer.c

@@ -0,0 +1,166 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * (C) Copyright 2009
+ * Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
+ */
+
+#include <common.h>
+#include <div64.h>
+#include <init.h>
+#include <time.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/ptrace.h>
+#include <linux/delay.h>
+
+/* General purpose timers bitfields */
+#define GPTCR_SWR		(1 << 15)	/* Software reset	*/
+#define GPTCR_FRR		(1 << 8)	/* Freerun / restart	*/
+#define GPTCR_CLKSOURCE_32	(4 << 1)	/* Clock source		*/
+#define GPTCR_TEN		1		/* Timer enable		*/
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define timestamp	(gd->arch.tbl)
+#define lastinc		(gd->arch.lastinc)
+
+/*
+ * "time" is measured in 1 / CONFIG_SYS_HZ seconds,
+ * "tick" is internal timer period
+ */
+#ifdef CONFIG_MX27_TIMER_HIGH_PRECISION
+/* ~0.4% error - measured with stop-watch on 100s boot-delay */
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+	tick *= CONFIG_SYS_HZ;
+	do_div(tick, CONFIG_MX27_CLK32);
+	return tick;
+}
+
+static inline unsigned long long time_to_tick(unsigned long long time)
+{
+	time *= CONFIG_MX27_CLK32;
+	do_div(time, CONFIG_SYS_HZ);
+	return time;
+}
+
+static inline unsigned long long us_to_tick(unsigned long long us)
+{
+	us = us * CONFIG_MX27_CLK32 + 999999;
+	do_div(us, 1000000);
+	return us;
+}
+#else
+/* ~2% error */
+#define TICK_PER_TIME	((CONFIG_MX27_CLK32 + CONFIG_SYS_HZ / 2) / \
+		CONFIG_SYS_HZ)
+#define US_PER_TICK	(1000000 / CONFIG_MX27_CLK32)
+
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+	do_div(tick, TICK_PER_TIME);
+	return tick;
+}
+
+static inline unsigned long long time_to_tick(unsigned long long time)
+{
+	return time * TICK_PER_TIME;
+}
+
+static inline unsigned long long us_to_tick(unsigned long long us)
+{
+	us += US_PER_TICK - 1;
+	do_div(us, US_PER_TICK);
+	return us;
+}
+#endif
+
+/* nothing really to do with interrupts, just starts up a counter. */
+/* The 32768Hz 32-bit timer overruns in 131072 seconds */
+int timer_init(void)
+{
+	int i;
+	struct gpt_regs *regs = (struct gpt_regs *)IMX_TIM1_BASE;
+	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
+
+	/* setup GP Timer 1 */
+	writel(GPTCR_SWR, &regs->gpt_tctl);
+
+	writel(readl(&pll->pccr0) | PCCR0_GPT1_EN, &pll->pccr0);
+	writel(readl(&pll->pccr1) | PCCR1_PERCLK1_EN, &pll->pccr1);
+
+	for (i = 0; i < 100; i++)
+		writel(0, &regs->gpt_tctl); /* We have no udelay by now */
+	writel(0, &regs->gpt_tprer); /* 32Khz */
+	/* Freerun Mode, PERCLK1 input */
+	writel(readl(&regs->gpt_tctl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR,
+			&regs->gpt_tctl);
+	writel(readl(&regs->gpt_tctl) | GPTCR_TEN, &regs->gpt_tctl);
+
+	return 0;
+}
+
+unsigned long long get_ticks(void)
+{
+	struct gpt_regs *regs = (struct gpt_regs *)IMX_TIM1_BASE;
+	ulong now = readl(&regs->gpt_tcn); /* current tick value */
+
+	if (now >= lastinc) {
+		/*
+		 * normal mode (non roll)
+		 * move stamp forward with absolut diff ticks
+		 */
+		timestamp += (now - lastinc);
+	} else {
+		/* we have rollover of incrementer */
+		timestamp += (0xFFFFFFFF - lastinc) + now;
+	}
+	lastinc = now;
+	return timestamp;
+}
+
+static ulong get_timer_masked(void)
+{
+	/*
+	 * get_ticks() returns a long long (64 bit), it wraps in
+	 * 2^64 / CONFIG_MX27_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
+	 * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
+	 * 5 * 10^6 days - long enough.
+	 */
+	return tick_to_time(get_ticks());
+}
+
+ulong get_timer(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+/* delay x useconds AND preserve advance timstamp value */
+void __udelay(unsigned long usec)
+{
+	unsigned long long tmp;
+	ulong tmo;
+
+	tmo = us_to_tick(usec);
+	tmp = get_ticks() + tmo;	/* get current timestamp */
+
+	while (get_ticks() < tmp)	/* loop till event */
+		 /*NOP*/;
+}
+
+ulong get_tbclk(void)
+{
+	return CONFIG_MX27_CLK32;
+}

arch/arm/cpu/arm926ejs/start.S

@@ -95,7 +95,7 @@ flush_dcache:
 	mrc	p15, 0, r0, c1, c0, 0
 	bic	r0, r0, #0x00000300	/* clear bits 9:8 (---- --RS) */
 	bic	r0, r0, #0x00000087	/* clear bits 7, 2:0 (B--- -CAM) */
-#ifdef CFG_SYS_EXCEPTION_VECTORS_HIGH
+#ifdef CONFIG_SYS_EXCEPTION_VECTORS_HIGH
 	orr	r0, r0, #0x00002000	/* set bit 13 (--V- ----) */
 #else
 	bic	r0, r0, #0x00002000	/* clear bit 13 (--V- ----) */

arch/arm/cpu/armv7/Kconfig

@@ -75,11 +75,15 @@ config ARMV7_PSCI
 choice
 	prompt "Supported PSCI version"
 	depends on ARMV7_PSCI
+	default ARMV7_PSCI_1_1 if MACH_SUN8I_A33 || MACH_SUN8I_H3
 	default ARMV7_PSCI_0_1 if ARCH_SUNXI
 	default ARMV7_PSCI_1_0
 	help
 	  Select the supported PSCI version.
 
+config ARMV7_PSCI_1_1
+	bool "PSCI V1.1"
+
 config ARMV7_PSCI_1_0
 	bool "PSCI V1.0"
 

arch/arm/cpu/armv7/arch_timer.c

@@ -14,7 +14,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifndef CFG_SYS_HZ_CLOCK
+#ifndef CONFIG_SYS_HZ_CLOCK
 static inline u32 read_cntfrq(void)
 {
 	u32 frq;
@@ -29,8 +29,8 @@ int timer_init(void)
 	gd->arch.tbl = 0;
 	gd->arch.tbu = 0;
 
-#ifdef CFG_SYS_HZ_CLOCK
+#ifdef CONFIG_SYS_HZ_CLOCK
-	gd->arch.timer_rate_hz = CFG_SYS_HZ_CLOCK;
+	gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK;
 #else
 	gd->arch.timer_rate_hz = read_cntfrq();
 #endif

arch/arm/cpu/armv7/ls102xa/Kconfig

@@ -1,8 +1,6 @@
 config ARCH_LS1021A
 	bool
-	select FSL_DEVICE_DISABLE
 	select FSL_IFC if !QSPI_BOOT && !SD_BOOT_QSPI
-	select LS102XA_STREAM_ID
 	select SYS_FSL_DDR_BE if SYS_FSL_DDR
 	select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
 	select SYS_FSL_IFC_BE
@@ -32,15 +30,9 @@ config ARCH_LS1021A
 menu "LS102xA architecture"
 	depends on ARCH_LS1021A
 
-config FSL_DEVICE_DISABLE
-	bool
-
 config LS1_DEEP_SLEEP
 	bool "Deep sleep"
 
-config LS102XA_STREAM_ID
-	bool
-
 config MAX_CPUS
 	int "Maximum number of CPUs permitted for LS102xA"
 	default 2
@@ -51,9 +43,6 @@ config MAX_CPUS
 	  cores, count the reserved ports. This will allocate enough memory
 	  in spin table to properly handle all cores.
 
-config PEN_ADDR_BIG_ENDIAN
-	bool
-
 config SYS_CCI400_OFFSET
 	hex "Offset for CCI400 base"
 	depends on SYS_FSL_HAS_CCI400

arch/arm/cpu/armv7/ls102xa/clock.c

@@ -15,8 +15,8 @@ DECLARE_GLOBAL_DATA_PTR;
 
 void get_sys_info(struct sys_info *sys_info)
 {
-	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
-	struct ccsr_clk *clk = (void *)(CFG_SYS_FSL_LS1_CLK_ADDR);
+	struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_LS1_CLK_ADDR);
 	unsigned int cpu;
 	const u8 core_cplx_pll[6] = {
 		[0] = 0,	/* CC1 PPL / 1 */

arch/arm/cpu/armv7/ls102xa/cpu.c

@@ -168,18 +168,18 @@ static void mmu_setup(void)
 	/* Level 1 has 512 entries */
 	for (i = 0; i < 512; i++) {
 		/* Mapping for PCIe 1 */
-		if (va_start >= CFG_SYS_PCIE1_VIRT_ADDR &&
+		if (va_start >= CONFIG_SYS_PCIE1_VIRT_ADDR &&
-		    va_start < (CFG_SYS_PCIE1_VIRT_ADDR +
+		    va_start < (CONFIG_SYS_PCIE1_VIRT_ADDR +
-				 CFG_SYS_PCIE_MMAP_SIZE))
+				 CONFIG_SYS_PCIE_MMAP_SIZE))
 			set_pgsection(level1_table, i,
-				      CFG_SYS_PCIE1_PHYS_BASE + va_start,
+				      CONFIG_SYS_PCIE1_PHYS_BASE + va_start,
 				      MT_DEVICE_MEM);
 		/* Mapping for PCIe 2 */
-		else if (va_start >= CFG_SYS_PCIE2_VIRT_ADDR &&
+		else if (va_start >= CONFIG_SYS_PCIE2_VIRT_ADDR &&
-			 va_start < (CFG_SYS_PCIE2_VIRT_ADDR +
+			 va_start < (CONFIG_SYS_PCIE2_VIRT_ADDR +
-				     CFG_SYS_PCIE_MMAP_SIZE))
+				     CONFIG_SYS_PCIE_MMAP_SIZE))
 			set_pgsection(level1_table, i,
-				      CFG_SYS_PCIE2_PHYS_BASE + va_start,
+				      CONFIG_SYS_PCIE2_PHYS_BASE + va_start,
 				      MT_DEVICE_MEM);
 		else
 			set_pgsection(level1_table, i,
@@ -228,7 +228,7 @@ void enable_caches(void)
 
 uint get_svr(void)
 {
-	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 
 	return in_be32(&gur->svr);
 }
@@ -237,7 +237,7 @@ uint get_svr(void)
 int print_cpuinfo(void)
 {
 	char buf1[32], buf2[32];
-	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 	unsigned int svr, major, minor, ver, i;
 
 	svr = in_be32(&gur->svr);
@@ -302,12 +302,21 @@ int cpu_mmc_init(struct bd_info *bis)
 }
 #endif
 
+int cpu_eth_init(struct bd_info *bis)
+{
+#if defined(CONFIG_TSEC_ENET) && !defined(CONFIG_DM_ETH)
+	tsec_standard_init(bis);
+#endif
+
+	return 0;
+}
+
 int arch_cpu_init(void)
 {
-	void *epu_base = (void *)(CFG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
+	void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
 	void *rcpm2_base =
-		(void *)(CFG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET);
+		(void *)(CONFIG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET);
-	struct ccsr_scfg *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
+	struct ccsr_scfg *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
 	u32 state;
 
 	icache_enable();
@@ -346,7 +355,7 @@ int arch_cpu_init(void)
 /* Set the address at which the secondary core starts from.*/
 void smp_set_core_boot_addr(unsigned long addr, int corenr)
 {
-	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 
 	out_be32(&gur->scratchrw[0], addr);
 }
@@ -354,7 +363,7 @@ void smp_set_core_boot_addr(unsigned long addr, int corenr)
 /* Release the secondary core from holdoff state and kick it */
 void smp_kick_all_cpus(void)
 {
-	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 
 	out_be32(&gur->brrl, 0x2);
 

arch/arm/cpu/armv7/ls102xa/fdt.c

@@ -92,7 +92,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
 	int off;
 	int val;
 	const char *sysclk_path;
-	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 	unsigned int svr;
 	svr = in_be32(&gur->svr);
 
@@ -105,7 +105,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
 	else {
 		ccsr_sec_t __iomem *sec;
 
-		sec = (void __iomem *)CFG_SYS_FSL_SEC_ADDR;
+		sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
 		fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
 	}
 #endif
@@ -125,7 +125,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
 
 #ifdef CONFIG_SYS_NS16550
 	do_fixup_by_compat_u32(blob, "fsl,16550-FIFO64",
-			       "clock-frequency", CFG_SYS_NS16550_CLK, 1);
+			       "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
 #endif
 
 	sysclk_path = fdt_get_alias(blob, "sysclk");
@@ -183,7 +183,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
 
 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 	off = fdt_node_offset_by_compat_reg(blob, FSL_IFC_COMPAT,
-					    CFG_SYS_IFC_ADDR);
+					    CONFIG_SYS_IFC_ADDR);
 	fdt_set_node_status(blob, off, FDT_STATUS_DISABLED);
 #else
 	off = fdt_node_offset_by_compat_reg(blob, FSL_QSPI_COMPAT,

arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c

@@ -39,7 +39,7 @@ int is_serdes_configured(enum srds_prtcl device)
 
 int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
 {
-	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 	u32 cfg = in_be32(&gur->rcwsr[4]);
 	int i;
 
@@ -74,7 +74,7 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
 
 u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
 {
-	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 	u64 serdes_prtcl_map = 0;
 	u32 cfg;
 	int lane;
@@ -103,14 +103,14 @@ void fsl_serdes_init(void)
 #ifdef CONFIG_SYS_FSL_SRDS_1
 	if (!(serdes1_prtcl_map & (1ULL << NONE)))
 		serdes1_prtcl_map = serdes_init(FSL_SRDS_1,
-					CFG_SYS_FSL_SERDES_ADDR,
+					CONFIG_SYS_FSL_SERDES_ADDR,
 					RCWSR4_SRDS1_PRTCL_MASK,
 					RCWSR4_SRDS1_PRTCL_SHIFT);
 #endif
 #ifdef CONFIG_SYS_FSL_SRDS_2
 	if (!(serdes2_prtcl_map & (1ULL << NONE)))
 		serdes2_prtcl_map = serdes_init(FSL_SRDS_2,
-					CFG_SYS_FSL_SERDES_ADDR +
+					CONFIG_SYS_FSL_SERDES_ADDR +
 					FSL_SRDS_2 * 0x1000,
 					RCWSR4_SRDS2_PRTCL_MASK,
 					RCWSR4_SRDS2_PRTCL_SHIFT);

arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c

@@ -29,9 +29,9 @@
  */
 static void __secure ls1_save_ddr_head(void)
 {
-	const char *src = (const char *)CFG_SYS_SDRAM_BASE;
+	const char *src = (const char *)CONFIG_SYS_SDRAM_BASE;
 	char *dest = (char *)(OCRAM_BASE_S_ADDR + OCRAM_S_SIZE - DDR_RESV_LEN);
-	struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
+	struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
 	int i;
 
 	out_le32(&scfg->sparecr[2], dest);
@@ -42,7 +42,7 @@ static void __secure ls1_save_ddr_head(void)
 
 static void __secure ls1_fsm_setup(void)
 {
-	void *dcsr_epu_base = (void *)(CFG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
+	void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
 	void *dcsr_rcpm_base = (void *)SYS_FSL_DCSR_RCPM_ADDR;
 
 	out_be32(dcsr_rcpm_base + DCSR_RCPM_CSTTACR0, 0x00001001);
@@ -57,8 +57,8 @@ static void __secure ls1_fsm_setup(void)
 
 static void __secure ls1_deepsleep_irq_cfg(void)
 {
-	struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
+	struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
-	struct ccsr_rcpm __iomem *rcpm = (void *)CFG_SYS_FSL_RCPM_ADDR;
+	struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR;
 	u32 ippdexpcr0, ippdexpcr1, pmcintecr = 0;
 
 	/* Mask interrupts from GIC */
@@ -118,10 +118,10 @@ static void __secure ls1_delay(unsigned int loop)
 
 static void __secure ls1_start_fsm(void)
 {
-	void *dcsr_epu_base = (void *)(CFG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
+	void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
 	void *ccsr_gic_base = (void *)SYS_FSL_GIC_ADDR;
-	struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
+	struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
-	struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
+	struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
 
 	/* Set HRSTCR */
 	setbits_be32(&scfg->hrstcr, 0x80000000);
@@ -155,9 +155,9 @@ static void __secure ls1_start_fsm(void)
 
 static void __secure ls1_deep_sleep(u32 entry_point)
 {
-	struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
+	struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
-	struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
+	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
-	struct ccsr_rcpm __iomem *rcpm = (void *)CFG_SYS_FSL_RCPM_ADDR;
+	struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR;
 #ifdef QIXIS_BASE
 	u32 tmp;
 	void *qixis_base = (void *)QIXIS_BASE;
@@ -213,8 +213,8 @@ static void __secure ls1_deep_sleep(u32 entry_point)
 #else
 static void __secure ls1_sleep(void)
 {
-	struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
+	struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
-	struct ccsr_rcpm __iomem *rcpm = (void *)CFG_SYS_FSL_RCPM_ADDR;
+	struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR;
 
 #ifdef QIXIS_BASE
 	u32 tmp;

arch/arm/cpu/armv7/ls102xa/psci.S

@@ -129,8 +129,8 @@ psci_cpu_on:
 	mov	r1, r4
 
 	@ Get DCFG base address
-	movw	r4, #(CFG_SYS_FSL_GUTS_ADDR & 0xffff)
+	movw	r4, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff)
-	movt	r4, #(CFG_SYS_FSL_GUTS_ADDR >> 16)
+	movt	r4, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16)
 
 	@ Detect target CPU state
 	ldr	r2, [r4, #DCFG_CCSR_BRR]
@@ -141,8 +141,8 @@ psci_cpu_on:
 
 	@ Reset target CPU
 	@ Get SCFG base address
-	movw	r0, #(CFG_SYS_FSL_SCFG_ADDR & 0xffff)
+	movw	r0, #(CONFIG_SYS_FSL_SCFG_ADDR & 0xffff)
-	movt	r0, #(CFG_SYS_FSL_SCFG_ADDR >> 16)
+	movt	r0, #(CONFIG_SYS_FSL_SCFG_ADDR >> 16)
 
 	@ Enable CORE Soft Reset
 	movw	r5, #0
@@ -216,8 +216,8 @@ psci_affinity_info:
 	mov	r1, r4
 
 	@ Get RCPM base address
-	movw	r4, #(CFG_SYS_FSL_RCPM_ADDR & 0xffff)
+	movw	r4, #(CONFIG_SYS_FSL_RCPM_ADDR & 0xffff)
-	movt	r4, #(CFG_SYS_FSL_RCPM_ADDR >> 16)
+	movt	r4, #(CONFIG_SYS_FSL_RCPM_ADDR >> 16)
 
 	mov	r0, #PSCI_AFFINITY_LEVEL_ON
 
@@ -236,8 +236,8 @@ out_affinity_info:
 .globl	psci_system_reset
 psci_system_reset:
 	@ Get DCFG base address
-	movw	r1, #(CFG_SYS_FSL_GUTS_ADDR & 0xffff)
+	movw	r1, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff)
-	movt	r1, #(CFG_SYS_FSL_GUTS_ADDR >> 16)
+	movt	r1, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16)
 
 	mov	r2, #DCFG_CCSR_RSTCR_RESET_REQ
 	rev	r2, r2

arch/arm/cpu/armv7/ls102xa/soc.c

@@ -54,7 +54,7 @@ struct smmu_stream_id dev_stream_id[] = {
 
 unsigned int get_soc_major_rev(void)
 {
-	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 	unsigned int svr, major;
 
 	svr = in_be32(&gur->svr);
@@ -113,7 +113,7 @@ static void erratum_a008850_early(void)
 	/* part 1 of 2 */
 	struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
 						CONFIG_SYS_CCI400_OFFSET);
-	struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
+	struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
 
 	/* disables propagation of barrier transactions to DDRC from CCI400 */
 	out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
@@ -129,7 +129,7 @@ void erratum_a008850_post(void)
 	/* part 2 of 2 */
 	struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
 						CONFIG_SYS_CCI400_OFFSET);
-	struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
+	struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
 	u32 tmp;
 
 	/* enable propagation of barrier transactions to DDRC from CCI400 */
@@ -161,7 +161,7 @@ void erratum_a010315(void)
 
 int arch_soc_init(void)
 {
-	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
+	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
 					CONFIG_SYS_CCI400_OFFSET);
 	unsigned int major;

arch/arm/cpu/armv7/nonsec_virt.S

@@ -112,8 +112,8 @@ ENTRY(_do_nonsec_entry)
 ENDPROC(_do_nonsec_entry)
 
 .macro get_cbar_addr	addr
-#ifdef CFG_ARM_GIC_BASE_ADDRESS
+#ifdef CONFIG_ARM_GIC_BASE_ADDRESS
-	ldr	\addr, =CFG_ARM_GIC_BASE_ADDRESS
+	ldr	\addr, =CONFIG_ARM_GIC_BASE_ADDRESS
 #else
 	mrc	p15, 4, \addr, c15, c0, 0	@ read CBAR
 	bfc	\addr, #0, #15			@ clear reserved bits
@@ -205,11 +205,11 @@ ENTRY(_nonsec_init)
 	bx	lr
 ENDPROC(_nonsec_init)
 
-#ifdef CFG_SMP_PEN_ADDR
+#ifdef CONFIG_SMP_PEN_ADDR
 /* void __weak smp_waitloop(unsigned previous_address); */
-WEAK(smp_waitloop)
+ENTRY(smp_waitloop)
 	wfi
-	ldr	r1, =CFG_SMP_PEN_ADDR	@ load start address
+	ldr	r1, =CONFIG_SMP_PEN_ADDR	@ load start address
 	ldr	r1, [r1]
 #ifdef CONFIG_PEN_ADDR_BIG_ENDIAN
 	rev	r1, r1
@@ -219,6 +219,7 @@ WEAK(smp_waitloop)
 	mov	r0, r1
 	b	_do_nonsec_entry
 ENDPROC(smp_waitloop)
+.weak smp_waitloop
 #endif
 
 	.popsection

arch/arm/cpu/armv7/psci.S

@@ -36,32 +36,34 @@ _psci_vectors:
 	b	default_psci_vector	@ irq
 	b	psci_fiq_enter		@ fiq
 
-WEAK(psci_fiq_enter)
+ENTRY(psci_fiq_enter)
 	movs	pc, lr
 ENDPROC(psci_fiq_enter)
+.weak psci_fiq_enter
 
-WEAK(default_psci_vector)
+ENTRY(default_psci_vector)
 	movs	pc, lr
 ENDPROC(default_psci_vector)
+.weak default_psci_vector
 
-WEAK(psci_version)
+ENTRY(psci_version)
-WEAK(psci_cpu_suspend)
+ENTRY(psci_cpu_suspend)
-WEAK(psci_cpu_off)
+ENTRY(psci_cpu_off)
-WEAK(psci_cpu_on)
+ENTRY(psci_cpu_on)
-WEAK(psci_affinity_info)
+ENTRY(psci_affinity_info)
-WEAK(psci_migrate)
+ENTRY(psci_migrate)
-WEAK(psci_migrate_info_type)
+ENTRY(psci_migrate_info_type)
-WEAK(psci_migrate_info_up_cpu)
+ENTRY(psci_migrate_info_up_cpu)
-WEAK(psci_system_off)
+ENTRY(psci_system_off)
-WEAK(psci_system_reset)
+ENTRY(psci_system_reset)
-WEAK(psci_features)
+ENTRY(psci_features)
-WEAK(psci_cpu_freeze)
+ENTRY(psci_cpu_freeze)
-WEAK(psci_cpu_default_suspend)
+ENTRY(psci_cpu_default_suspend)
-WEAK(psci_node_hw_state)
+ENTRY(psci_node_hw_state)
-WEAK(psci_system_suspend)
+ENTRY(psci_system_suspend)
-WEAK(psci_set_suspend_mode)
+ENTRY(psci_set_suspend_mode)
-WEAK(psi_stat_residency)
+ENTRY(psi_stat_residency)
-WEAK(psci_stat_count)
+ENTRY(psci_stat_count)
 	mov	r0, #ARM_PSCI_RET_NI	@ Return -1 (Not Implemented)
 	mov	pc, lr
 ENDPROC(psci_stat_count)
@@ -82,6 +84,24 @@ ENDPROC(psci_cpu_on)
 ENDPROC(psci_cpu_off)
 ENDPROC(psci_cpu_suspend)
 ENDPROC(psci_version)
+.weak psci_version
+.weak psci_cpu_suspend
+.weak psci_cpu_off
+.weak psci_cpu_on
+.weak psci_affinity_info
+.weak psci_migrate
+.weak psci_migrate_info_type
+.weak psci_migrate_info_up_cpu
+.weak psci_system_off
+.weak psci_system_reset
+.weak psci_features
+.weak psci_cpu_freeze
+.weak psci_cpu_default_suspend
+.weak psci_node_hw_state
+.weak psci_system_suspend
+.weak psci_set_suspend_mode
+.weak psi_stat_residency
+.weak psci_stat_count
 
 _psci_table:
 	.word	ARM_PSCI_FN_CPU_SUSPEND
@@ -159,11 +179,12 @@ _smc_psci:
 	movs	pc, lr			@ Return to the kernel
 
 @ Requires dense and single-cluster CPU ID space
-WEAK(psci_get_cpu_id)
+ENTRY(psci_get_cpu_id)
 	mrc	p15, 0, r0, c0, c0, 5	/* read MPIDR */
 	and	r0, r0, #0xff		/* return CPU ID in cluster */
 	bx	lr
 ENDPROC(psci_get_cpu_id)
+.weak psci_get_cpu_id
 
 /* Imported from Linux kernel */
 ENTRY(psci_v7_flush_dcache_all)
@@ -215,7 +236,7 @@ finished:
 	bx	lr
 ENDPROC(psci_v7_flush_dcache_all)
 
-WEAK(psci_disable_smp)
+ENTRY(psci_disable_smp)
 	mrc	p15, 0, r0, c1, c0, 1		@ ACTLR
 	bic	r0, r0, #(1 << 6)		@ Clear SMP bit
 	mcr	p15, 0, r0, c1, c0, 1		@ ACTLR
@@ -223,14 +244,16 @@ WEAK(psci_disable_smp)
 	dsb
 	bx	lr
 ENDPROC(psci_disable_smp)
+.weak psci_disable_smp
 
-WEAK(psci_enable_smp)
+ENTRY(psci_enable_smp)
 	mrc	p15, 0, r0, c1, c0, 1		@ ACTLR
 	orr	r0, r0, #(1 << 6)		@ Set SMP bit
 	mcr	p15, 0, r0, c1, c0, 1		@ ACTLR
 	isb
 	bx	lr
 ENDPROC(psci_enable_smp)
+.weak psci_enable_smp
 
 ENTRY(psci_cpu_off_common)
 	push	{lr}
@@ -293,13 +316,15 @@ ENTRY(psci_stack_setup)
 	bx	r6
 ENDPROC(psci_stack_setup)
 
-WEAK(psci_arch_init)
+ENTRY(psci_arch_init)
 	mov	pc, lr
 ENDPROC(psci_arch_init)
+.weak psci_arch_init
 
-WEAK(psci_arch_cpu_entry)
+ENTRY(psci_arch_cpu_entry)
 	mov	pc, lr
 ENDPROC(psci_arch_cpu_entry)
+.weak psci_arch_cpu_entry
 
 ENTRY(psci_cpu_entry)
 	bl	psci_enable_smp

arch/arm/cpu/armv7/s5p-common/pwm.c

@@ -7,11 +7,12 @@
 
 #include <common.h>
 #include <errno.h>
+#include <pwm.h>
 #include <asm/io.h>
 #include <asm/arch/pwm.h>
 #include <asm/arch/clk.h>
 
-int s5p_pwm_enable(int pwm_id)
+int pwm_enable(int pwm_id)
 {
 	const struct s5p_timer *pwm =
 #if defined(CONFIG_ARCH_NEXELL)
@@ -29,7 +30,7 @@ int s5p_pwm_enable(int pwm_id)
 	return 0;
 }
 
-void s5p_pwm_disable(int pwm_id)
+void pwm_disable(int pwm_id)
 {
 	const struct s5p_timer *pwm =
 #if defined(CONFIG_ARCH_NEXELL)
@@ -91,7 +92,7 @@ static unsigned long pwm_calc_tin(int pwm_id, unsigned long freq)
 
 #define NS_IN_SEC 1000000000UL
 
-int s5p_pwm_config(int pwm_id, int duty_ns, int period_ns)
+int pwm_config(int pwm_id, int duty_ns, int period_ns)
 {
 	const struct s5p_timer *pwm =
 #if defined(CONFIG_ARCH_NEXELL)
@@ -156,7 +157,7 @@ int s5p_pwm_config(int pwm_id, int duty_ns, int period_ns)
 	return 0;
 }
 
-int s5p_pwm_init(int pwm_id, int div, int invert)
+int pwm_init(int pwm_id, int div, int invert)
 {
 	u32 val;
 	const struct s5p_timer *pwm =
@@ -218,7 +219,7 @@ int s5p_pwm_init(int pwm_id, int div, int invert)
 		val |= TCON_INVERTER(pwm_id);
 	writel(val, &pwm->tcon);
 
-	s5p_pwm_enable(pwm_id);
+	pwm_enable(pwm_id);
 
 	return 0;
 }

arch/arm/cpu/armv7/s5p-common/timer.c

@@ -16,6 +16,10 @@
 #include <asm/arch/clk.h>
 #include <linux/delay.h>
 
+/* Use the old PWM interface for now */
+#undef CONFIG_DM_PWM
+#include <pwm.h>
+
 DECLARE_GLOBAL_DATA_PTR;
 
 unsigned long get_current_tick(void);
@@ -45,9 +49,9 @@ static unsigned long timer_get_us_down(void)
 int timer_init(void)
 {
 	/* PWM Timer 4 */
-	s5p_pwm_init(4, MUX_DIV_4, 0);
+	pwm_init(4, MUX_DIV_4, 0);
-	s5p_pwm_config(4, 100000, 100000);
+	pwm_config(4, 100000, 100000);
-	s5p_pwm_enable(4);
+	pwm_enable(4);
 
 	/* Use this as the current monotonic time in us */
 	gd->arch.timer_reset_value = 0;

arch/arm/cpu/armv7/s5p4418/cpu.c

@@ -13,8 +13,10 @@
 #include <asm/io.h>
 #include <asm/arch/nexell.h>
 #include <asm/arch/clk.h>
+#include <asm/arch/reset.h>
 #include <asm/arch/tieoff.h>
 #include <cpu_func.h>
+#include <linux/delay.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -43,12 +45,39 @@ static void cpu_soc_init(void)
 	nx_tieoff_set(NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_L2RET1N_1, 1);
 }
 
+#ifdef CONFIG_PL011_SERIAL
+static void serial_device_init(void)
+{
+	char dev[10];
+	int id;
+
+	sprintf(dev, "nx-uart.%d", CONFIG_CONS_INDEX);
+	id = RESET_ID_UART0 + CONFIG_CONS_INDEX;
+
+	struct clk *clk = clk_get((const char *)dev);
+
+	/* reset control: Low active ___|---   */
+	nx_rstcon_setrst(id, RSTCON_ASSERT);
+	udelay(10);
+	nx_rstcon_setrst(id, RSTCON_NEGATE);
+	udelay(10);
+
+	/* set clock   */
+	clk_disable(clk);
+	clk_set_rate(clk, CONFIG_PL011_CLOCK);
+	clk_enable(clk);
+}
+#endif
+
 int arch_cpu_init(void)
 {
 	flush_dcache_all();
 	cpu_soc_init();
 	clk_init();
 
+	if (IS_ENABLED(CONFIG_PL011_SERIAL))
+		serial_device_init();
+
 	return 0;
 }
 

arch/arm/cpu/armv7/start.S

@@ -151,14 +151,16 @@ ENDPROC(c_runtime_cpu_setup)
  * Don't save anything to stack even if compiled with -O0
  *
  *************************************************************************/
-WEAK(save_boot_params)
+ENTRY(save_boot_params)
 	b	save_boot_params_ret		@ back to my caller
 ENDPROC(save_boot_params)
+	.weak	save_boot_params
 
 #ifdef CONFIG_ARMV7_LPAE
-WEAK(switch_to_hypervisor)
+ENTRY(switch_to_hypervisor)
 	b	switch_to_hypervisor_ret
 ENDPROC(switch_to_hypervisor)
+	.weak	switch_to_hypervisor
 #endif
 
 /*************************************************************************

arch/arm/cpu/armv7/stv0991/timer.c

@@ -18,7 +18,7 @@ static struct stv0991_cgu_regs *const stv0991_cgu_regs = \
 				(struct stv0991_cgu_regs *) (CGU_BASE_ADDR);
 
 #define READ_TIMER()	(readl(&gpt1_regs_ptr->cnt) & GPT_FREE_RUNNING)
-#define GPT_RESOLUTION	(CFG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)
+#define GPT_RESOLUTION	(CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -67,7 +67,7 @@ void __udelay(unsigned long usec)
 {
 	ulong tmo;
 	ulong start = get_timer_masked();
-	ulong tenudelcnt = CFG_SYS_HZ_CLOCK / (1000 * 100);
+	ulong tenudelcnt = CONFIG_SYS_HZ_CLOCK / (1000 * 100);
 	ulong rndoff;
 
 	rndoff = (usec % 10) ? 1 : 0;

arch/arm/cpu/armv7/sunxi/Makefile

@@ -13,8 +13,12 @@ obj-$(CONFIG_MACH_SUN6I)	+= sram.o
 obj-$(CONFIG_MACH_SUN8I)	+= sram.o
 
 ifndef CONFIG_SPL_BUILD
+ifneq ($(CONFIG_MACH_SUN8I_A33)$(CONFIG_MACH_SUN8I_H3),)
+obj-$(CONFIG_ARMV7_PSCI)	+= psci-scpi.o
+else
 obj-$(CONFIG_ARMV7_PSCI)	+= psci.o
 endif
+endif
 
 ifdef CONFIG_SPL_BUILD
 obj-y	+= fel_utils.o

arch/arm/cpu/armv7/sunxi/psci-scpi.c

@@ -0,0 +1,455 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
+ * Copyright (C) 2018-2021 Samuel Holland <samuel@sholland.org>
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/cpucfg.h>
+#include <asm/armv7.h>
+#include <asm/gic.h>
+#include <asm/io.h>
+#include <asm/psci.h>
+#include <asm/secure.h>
+#include <asm/system.h>
+
+#define	GICD_BASE		(SUNXI_GIC400_BASE + GIC_DIST_OFFSET)
+#define	GICC_BASE		(SUNXI_GIC400_BASE + GIC_CPU_OFFSET_A15)
+
+#define HW_ON			0
+#define HW_OFF			1
+#define HW_STANDBY		2
+
+#define MPIDR_AFFLVL0(mpidr)	(mpidr & 0xf)
+#define MPIDR_AFFLVL1(mpidr)	(mpidr >> 8 & 0xf)
+
+#if defined(CONFIG_MACH_SUN8I_H3)
+#define SCPI_SHMEM_BASE		0x0004be00
+#else
+#define SCPI_SHMEM_BASE		0x00053e00
+#endif
+#define SCPI_SHMEM		((struct scpi_shmem *)SCPI_SHMEM_BASE)
+
+#define SCPI_RX_CHANNEL		1
+#define SCPI_TX_CHANNEL		0
+#define SCPI_VIRTUAL_CHANNEL	BIT(0)
+
+#define SCPI_MESSAGE_SIZE	0x100
+#define SCPI_PAYLOAD_SIZE	(SCPI_MESSAGE_SIZE - sizeof(struct scpi_header))
+
+#define SUNXI_MSGBOX_BASE	0x01c17000
+#define REMOTE_IRQ_STAT_REG	(SUNXI_MSGBOX_BASE + 0x0050)
+#define LOCAL_IRQ_STAT_REG	(SUNXI_MSGBOX_BASE + 0x0070)
+#define MSG_STAT_REG(n)		(SUNXI_MSGBOX_BASE + 0x0140 + 0x4 * (n))
+#define MSG_DATA_REG(n)		(SUNXI_MSGBOX_BASE + 0x0180 + 0x4 * (n))
+
+#define RX_IRQ(n)		BIT(0 + 2 * (n))
+#define TX_IRQ(n)		BIT(1 + 2 * (n))
+
+enum {
+	CORE_POWER_LEVEL		= 0,
+	CLUSTER_POWER_LEVEL		= 1,
+	CSS_POWER_LEVEL			= 2,
+};
+
+enum {
+	SCPI_CMD_SCP_READY		= 0x01,
+	SCPI_CMD_SET_CSS_POWER_STATE	= 0x03,
+	SCPI_CMD_GET_CSS_POWER_STATE	= 0x04,
+	SCPI_CMD_SET_SYS_POWER_STATE	= 0x05,
+};
+
+enum {
+	SCPI_E_OK			= 0,
+	SCPI_E_PARAM			= 1,
+	SCPI_E_ALIGN			= 2,
+	SCPI_E_SIZE			= 3,
+	SCPI_E_HANDLER			= 4,
+	SCPI_E_ACCESS			= 5,
+	SCPI_E_RANGE			= 6,
+	SCPI_E_TIMEOUT			= 7,
+	SCPI_E_NOMEM			= 8,
+	SCPI_E_PWRSTATE			= 9,
+	SCPI_E_SUPPORT			= 10,
+	SCPI_E_DEVICE			= 11,
+	SCPI_E_BUSY			= 12,
+	SCPI_E_OS			= 13,
+	SCPI_E_DATA			= 14,
+	SCPI_E_STATE			= 15,
+};
+
+enum {
+	SCPI_POWER_ON			= 0x00,
+	SCPI_POWER_RETENTION		= 0x01,
+	SCPI_POWER_OFF			= 0x03,
+};
+
+enum {
+	SCPI_SYSTEM_SHUTDOWN		= 0x00,
+	SCPI_SYSTEM_REBOOT		= 0x01,
+	SCPI_SYSTEM_RESET		= 0x02,
+};
+
+struct scpi_header {
+	u8			command;
+	u8			sender;
+	u16			size;
+	u32			status;
+};
+
+struct scpi_message {
+	struct scpi_header	header;
+	u8			payload[SCPI_PAYLOAD_SIZE];
+};
+
+struct scpi_shmem {
+	struct scpi_message	rx;
+	struct scpi_message	tx;
+};
+
+static bool __secure_data gic_dist_init;
+
+static u32 __secure_data lock;
+
+static inline u32 __secure read_mpidr(void)
+{
+	u32 val;
+
+	asm volatile ("mrc p15, 0, %0, c0, c0, 5" : "=r" (val));
+
+	return val;
+}
+
+static void __secure scpi_begin_command(void)
+{
+	u32 mpidr = read_mpidr();
+
+	do {
+		while (readl(&lock));
+		writel(mpidr, &lock);
+		dsb();
+	} while (readl(&lock) != mpidr);
+	while (readl(REMOTE_IRQ_STAT_REG) & RX_IRQ(SCPI_TX_CHANNEL));
+}
+
+static void __secure scpi_send_command(void)
+{
+	writel(SCPI_VIRTUAL_CHANNEL, MSG_DATA_REG(SCPI_TX_CHANNEL));
+}
+
+static void __secure scpi_wait_response(void)
+{
+	while (!readl(MSG_STAT_REG(SCPI_RX_CHANNEL)));
+}
+
+static void __secure scpi_end_command(void)
+{
+	while (readl(MSG_STAT_REG(SCPI_RX_CHANNEL)))
+		readl(MSG_DATA_REG(SCPI_RX_CHANNEL));
+	writel(RX_IRQ(SCPI_RX_CHANNEL), LOCAL_IRQ_STAT_REG);
+	writel(0, &lock);
+}
+
+static void __secure scpi_set_css_power_state(u32 target_cpu, u32 core_state,
+					      u32 cluster_state, u32 css_state)
+{
+	struct scpi_shmem *shmem = SCPI_SHMEM;
+
+	scpi_begin_command();
+
+	shmem->tx.header.command = SCPI_CMD_SET_CSS_POWER_STATE;
+	shmem->tx.header.size = 4;
+
+	shmem->tx.payload[0] = target_cpu    >> 4 | target_cpu;
+	shmem->tx.payload[1] = cluster_state << 4 | core_state;
+	shmem->tx.payload[2] = css_state;
+	shmem->tx.payload[3] = 0;
+
+	scpi_send_command();
+	scpi_end_command();
+}
+
+static s32 __secure scpi_get_css_power_state(u32 target_cpu, u8 *core_states,
+					     u8 *cluster_state)
+{
+	struct scpi_shmem *shmem = SCPI_SHMEM;
+	u32 cluster = MPIDR_AFFLVL1(target_cpu);
+	u32 offset;
+	s32 ret;
+
+	scpi_begin_command();
+
+	shmem->tx.header.command = SCPI_CMD_GET_CSS_POWER_STATE;
+	shmem->tx.header.size = 0;
+
+	scpi_send_command();
+	scpi_wait_response();
+
+	for (offset = 0; offset < shmem->rx.header.size; offset += 2) {
+		if ((shmem->rx.payload[offset] & 0xf) == cluster) {
+			*cluster_state = shmem->rx.payload[offset+0] >> 4;
+			*core_states   = shmem->rx.payload[offset+1];
+
+			break;
+		}
+	}
+
+	ret = shmem->rx.header.status;
+
+	scpi_end_command();
+
+	return ret;
+}
+
+static s32 __secure scpi_set_sys_power_state(u32 sys_state)
+{
+	struct scpi_shmem *shmem = SCPI_SHMEM;
+	s32 ret;
+
+	scpi_begin_command();
+
+	shmem->tx.header.command = SCPI_CMD_SET_SYS_POWER_STATE;
+	shmem->tx.header.size = 1;
+
+	shmem->tx.payload[0] = sys_state;
+
+	scpi_send_command();
+	scpi_wait_response();
+
+	ret = shmem->rx.header.status;
+
+	scpi_end_command();
+
+	return ret;
+}
+
+void psci_enable_smp(void);
+
+static s32 __secure psci_suspend_common(u32 pc, u32 context_id, u32 core_state,
+					u32 cluster_state, u32 css_state)
+
+{
+	u32 target_cpu = read_mpidr();
+
+	if (core_state == SCPI_POWER_OFF)
+		psci_save(MPIDR_AFFLVL0(target_cpu), pc, context_id);
+	if (css_state == SCPI_POWER_OFF)
+		gic_dist_init = true;
+
+	scpi_set_css_power_state(target_cpu, core_state,
+				 cluster_state, css_state);
+
+	psci_cpu_off_common();
+
+	wfi();
+
+	psci_enable_smp();
+
+	return ARM_PSCI_RET_SUCCESS;
+}
+
+u32 __secure psci_version(void)
+{
+	return ARM_PSCI_VER_1_1;
+}
+
+s32 __secure psci_cpu_suspend(u32 __always_unused function_id,
+			      u32 power_state, u32 pc, u32 context_id)
+{
+	return psci_suspend_common(pc, context_id,
+				   power_state >> 0 & 0xf,
+				   power_state >> 4 & 0xf,
+				   power_state >> 8 & 0xf);
+}
+
+s32 __secure psci_cpu_off(void)
+{
+	u32 pc = 0, context_id = 0;
+
+	return psci_suspend_common(pc, context_id, SCPI_POWER_OFF,
+				   SCPI_POWER_OFF, SCPI_POWER_ON);
+}
+
+s32 __secure psci_cpu_on(u32 __always_unused function_id,
+			 u32 target_cpu, u32 pc, u32 context_id)
+{
+	psci_save(MPIDR_AFFLVL0(target_cpu), pc, context_id);
+
+	scpi_set_css_power_state(target_cpu, SCPI_POWER_ON,
+				 SCPI_POWER_ON, SCPI_POWER_ON);
+
+	return ARM_PSCI_RET_SUCCESS;
+}
+
+s32 __secure psci_affinity_info(u32 function_id,
+				u32 target_cpu, u32 power_level)
+{
+	if (power_level != CORE_POWER_LEVEL)
+		return ARM_PSCI_RET_INVAL;
+
+	/* This happens to have the same HW_ON/HW_OFF encoding. */
+	return psci_node_hw_state(function_id, target_cpu, power_level);
+}
+
+void __secure psci_system_off(void)
+{
+	scpi_set_sys_power_state(SCPI_SYSTEM_SHUTDOWN);
+
+	/* Wait to be turned off. */
+	for (;;) wfi();
+}
+
+void __secure psci_system_reset(void)
+{
+	scpi_set_sys_power_state(SCPI_SYSTEM_REBOOT);
+
+	/* Wait to be turned off. */
+	for (;;) wfi();
+}
+
+s32 __secure psci_features(u32 __always_unused function_id,
+			   u32 psci_fid)
+{
+	switch (psci_fid) {
+	case ARM_PSCI_0_2_FN_PSCI_VERSION:
+	case ARM_PSCI_0_2_FN_CPU_SUSPEND:
+	case ARM_PSCI_0_2_FN_CPU_OFF:
+	case ARM_PSCI_0_2_FN_CPU_ON:
+	case ARM_PSCI_0_2_FN_AFFINITY_INFO:
+	case ARM_PSCI_0_2_FN_SYSTEM_OFF:
+	case ARM_PSCI_0_2_FN_SYSTEM_RESET:
+	case ARM_PSCI_1_0_FN_PSCI_FEATURES:
+	case ARM_PSCI_1_0_FN_CPU_DEFAULT_SUSPEND:
+	case ARM_PSCI_1_0_FN_NODE_HW_STATE:
+	case ARM_PSCI_1_0_FN_SYSTEM_SUSPEND:
+	case ARM_PSCI_1_1_FN_SYSTEM_RESET2:
+		return ARM_PSCI_RET_SUCCESS;
+	default:
+		return ARM_PSCI_RET_NI;
+	}
+}
+
+s32 __secure psci_cpu_default_suspend(u32 __always_unused function_id,
+				      u32 pc, u32 context_id)
+{
+	return psci_suspend_common(pc, context_id, SCPI_POWER_OFF,
+				   SCPI_POWER_OFF, SCPI_POWER_RETENTION);
+}
+
+s32 __secure psci_node_hw_state(u32 __always_unused function_id,
+				u32 target_cpu, u32 power_level)
+{
+	u32 core = MPIDR_AFFLVL0(target_cpu);
+	u8 core_states, cluster_state;
+
+	if (power_level >= CSS_POWER_LEVEL)
+		return HW_ON;
+	if (scpi_get_css_power_state(target_cpu, &core_states, &cluster_state))
+		return ARM_PSCI_RET_NI;
+	if (power_level == CLUSTER_POWER_LEVEL) {
+		if (cluster_state == SCPI_POWER_ON)
+			return HW_ON;
+		if (cluster_state < SCPI_POWER_OFF)
+			return HW_STANDBY;
+		return HW_OFF;
+	}
+
+	return (core_states & BIT(core)) ? HW_ON : HW_OFF;
+}
+
+s32 __secure psci_system_suspend(u32 __always_unused function_id,
+				 u32 pc, u32 context_id)
+{
+	return psci_suspend_common(pc, context_id, SCPI_POWER_OFF,
+				   SCPI_POWER_OFF, SCPI_POWER_OFF);
+}
+
+s32 __secure psci_system_reset2(u32 __always_unused function_id,
+				u32 reset_type, u32 cookie)
+{
+	s32 ret;
+
+	if (reset_type)
+		return ARM_PSCI_RET_INVAL;
+
+	ret = scpi_set_sys_power_state(SCPI_SYSTEM_RESET);
+	if (ret)
+		return ARM_PSCI_RET_INVAL;
+
+	/* Wait to be turned off. */
+	for (;;) wfi();
+}
+
+/*
+ * R40 is different from other single cluster SoCs. The secondary core
+ * entry address register is in the SRAM controller address range.
+ */
+#define SUN8I_R40_SRAMC_SOFT_ENTRY_REG0		(0xbc)
+
+#ifdef CONFIG_MACH_SUN8I_R40
+/* secondary core entry address is programmed differently on R40 */
+static void __secure sunxi_set_entry_address(void *entry)
+{
+	writel((u32)entry,
+	       SUNXI_SRAMC_BASE + SUN8I_R40_SRAMC_SOFT_ENTRY_REG0);
+}
+#else
+static void __secure sunxi_set_entry_address(void *entry)
+{
+	struct sunxi_cpucfg_reg *cpucfg =
+		(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
+
+	writel((u32)entry, &cpucfg->priv0);
+
+#ifdef CONFIG_MACH_SUN8I_H3
+	/* Redirect CPU 0 to the secure monitor via the resume shim. */
+	writel(0x16aaefe8, &cpucfg->super_standy_flag);
+	writel(0xaa16efe8, &cpucfg->super_standy_flag);
+	writel(SUNXI_RESUME_BASE, &cpucfg->priv1);
+#endif
+}
+#endif
+
+void __secure psci_arch_init(void)
+{
+	static bool __secure_data one_time_init = true;
+
+	if (one_time_init) {
+		/* Set secondary core power-on PC. */
+		sunxi_set_entry_address(psci_cpu_entry);
+
+		/* Wait for the SCP firmware to boot. */
+		scpi_begin_command();
+		scpi_wait_response();
+		scpi_end_command();
+
+		one_time_init = false;
+	}
+
+	/*
+	 * Copied from arch/arm/cpu/armv7/virt-v7.c
+	 * See also gic_resume() in arch/arm/mach-imx/mx7/psci-mx7.c
+	 */
+	if (gic_dist_init) {
+		u32 i, itlinesnr;
+
+		/* enable the GIC distributor */
+		writel(readl(GICD_BASE + GICD_CTLR) | 0x03, GICD_BASE + GICD_CTLR);
+
+		/* TYPER[4:0] contains an encoded number of available interrupts */
+		itlinesnr = readl(GICD_BASE + GICD_TYPER) & 0x1f;
+
+		/* set all bits in the GIC group registers to one to allow access
+		 * from non-secure state. The first 32 interrupts are private per
+		 * CPU and will be set later when enabling the GIC for each core
+		 */
+		for (i = 1; i <= itlinesnr; i++)
+			writel((unsigned)-1, GICD_BASE + GICD_IGROUPRn + 4 * i);
+
+		gic_dist_init = false;
+	}
+
+	/* Be cool with non-secure. */
+	writel(0xff, GICC_BASE + GICC_PMR);
+}

arch/arm/cpu/armv7/sunxi/psci.c

@@ -10,6 +10,7 @@
 #include <common.h>
 #include <asm/cache.h>
 
+#include <asm/arch/clock.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/cpucfg.h>
 #include <asm/arch/prcm.h>
@@ -38,6 +39,15 @@
 #define SUN8I_R40_PWR_CLAMP(cpu)		(0x120 + (cpu) * 0x4)
 #define SUN8I_R40_SRAMC_SOFT_ENTRY_REG0		(0xbc)
 
+static inline u32 __secure cp15_read_mpidr(void)
+{
+	u32 val;
+
+	asm volatile ("mrc p15, 0, %0, c0, c0, 5" : "=r" (val));
+
+	return val;
+}
+
 static void __secure cp15_write_cntp_tval(u32 tval)
 {
 	asm volatile ("mcr p15, 0, %0, c14, c2, 0" : : "r" (tval));
@@ -132,6 +142,13 @@ static void __secure sunxi_set_entry_address(void *entry)
 		(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
 
 	writel((u32)entry, &cpucfg->priv0);
+
+#ifdef CONFIG_MACH_SUN8I_H3
+	/* Redirect CPU 0 to the secure monitor via the resume shim. */
+	writel(0x16aaefe8, &cpucfg->super_standy_flag);
+	writel(0xaa16efe8, &cpucfg->super_standy_flag);
+	writel(SUNXI_RESUME_BASE, &cpucfg->priv1);
+#endif
 }
 #endif
 
@@ -246,9 +263,12 @@ out:
 int __secure psci_cpu_on(u32 __always_unused unused, u32 mpidr, u32 pc,
 			 u32 context_id)
 {
+	struct sunxi_ccm_reg *ccu = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 	struct sunxi_cpucfg_reg *cpucfg =
 		(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
 	u32 cpu = (mpidr & 0x3);
+	u32 cpu_clk;
+	u32 bus_clk;
 
 	/* store target PC and context id */
 	psci_save(cpu, pc, context_id);
@@ -265,12 +285,32 @@ int __secure psci_cpu_on(u32 __always_unused unused, u32 mpidr, u32 pc,
 	/* Lock CPU (Disable external debug access) */
 	clrbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
 
+	if (IS_ENABLED(CONFIG_MACH_SUN8I_H3) && cpu == 0) {
+		/* Save registers that will be clobbered by the BROM. */
+		cpu_clk = readl(&ccu->cpu_axi_cfg);
+		bus_clk = readl(&ccu->ahb1_apb1_div);
+
+		/* Bypass PLL_PERIPH0 so AHB1 frequency does not spike. */
+		setbits_le32(&ccu->pll6_cfg, BIT(25));
+	}
+
 	/* Power up target CPU */
 	sunxi_cpu_set_power(cpu, true);
 
 	/* De-assert reset on target CPU */
 	writel(BIT(1) | BIT(0), &cpucfg->cpu[cpu].rst);
 
+	if (IS_ENABLED(CONFIG_MACH_SUN8I_H3) && cpu == 0) {
+		/* Spin until the BROM has clobbered the clock registers. */
+		while (readl(&ccu->ahb1_apb1_div) != 0x00001100);
+
+		/* Restore the registers and turn off PLL_PERIPH0 bypass. */
+		writel(cpu_clk, &ccu->cpu_axi_cfg);
+		writel(bus_clk, &ccu->ahb1_apb1_div);
+
+		clrbits_le32(&ccu->pll6_cfg, BIT(25));
+	}
+
 	/* Unlock CPU (Disable external debug access) */
 	setbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
 
@@ -281,9 +321,14 @@ s32 __secure psci_cpu_off(void)
 {
 	psci_cpu_off_common();
 
+	if (cp15_read_mpidr() & 3) {
 		/* Ask CPU0 via SGI15 to pull the rug... */
 		writel(BIT(16) | 15, GICD_BASE + GICD_SGIR);
 		dsb();
+	} else {
+		/* Unmask FIQs to service SGI15. */
+		asm volatile ("cpsie f");
+	}
 
 	/* Wait to be turned off */
 	while (1)

arch/arm/cpu/armv7/virt-v7.c

@@ -26,8 +26,8 @@ static unsigned int read_id_pfr1(void)
 
 static unsigned long get_gicd_base_address(void)
 {
-#ifdef CFG_ARM_GIC_BASE_ADDRESS
+#ifdef CONFIG_ARM_GIC_BASE_ADDRESS
-	return CFG_ARM_GIC_BASE_ADDRESS + GIC_DIST_OFFSET;
+	return CONFIG_ARM_GIC_BASE_ADDRESS + GIC_DIST_OFFSET;
 #else
 	unsigned periphbase;
 

arch/arm/cpu/armv7m/systick-timer.c

@@ -18,7 +18,7 @@
  * The number of reference clock ticks that correspond to 10ms is normally
  * defined in the SysTick Calibration register's TENMS field. However, on some
  * devices this is wrong, so this driver allows the clock rate to be defined
- * using CFG_SYS_HZ_CLOCK.
+ * using CONFIG_SYS_HZ_CLOCK.
  */
 
 #include <common.h>
@@ -76,10 +76,10 @@ int timer_init(void)
 
 	/*
 	 * If the TENMS field is inexact or wrong, specify the clock rate using
-	 * CFG_SYS_HZ_CLOCK.
+	 * CONFIG_SYS_HZ_CLOCK.
 	 */
-#if defined(CFG_SYS_HZ_CLOCK)
+#if defined(CONFIG_SYS_HZ_CLOCK)
-	gd->arch.timer_rate_hz = CFG_SYS_HZ_CLOCK;
+	gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK;
 #else
 	gd->arch.timer_rate_hz = (cal & SYSTICK_CAL_TENMS_MASK) * 100;
 #endif

arch/arm/cpu/armv8/fsl-layerscape/Kconfig

@@ -29,7 +29,6 @@ config ARCH_LS1028A
 	select ESBC_HDR_LS if CHAIN_OF_TRUST
 	select FSL_LAYERSCAPE
 	select FSL_LSCH3
-	select FSL_TZASC_400
 	select GICV3
 	select NXP_LSCH3_2
 	select SYS_FSL_HAS_CCI400
@@ -70,7 +69,6 @@ config ARCH_LS1043A
 	select GICV2
 	select HAS_FSL_XHCI_USB if USB_HOST
 	select SKIP_LOWLEVEL_INIT
-	select SYS_DPAA_FMAN
 	select SYS_FSL_SRDS_1
 	select SYS_HAS_SERDES
 	select SYS_FSL_DDR
@@ -108,7 +106,6 @@ config ARCH_LS1046A
 	select GICV2
 	select HAS_FSL_XHCI_USB if USB_HOST
 	select SKIP_LOWLEVEL_INIT
-	select SYS_DPAA_FMAN
 	select SYS_FSL_SRDS_1
 	select SYS_HAS_SERDES
 	select SYS_FSL_DDR

arch/arm/cpu/armv8/fsl-layerscape/cpu.c

@@ -96,11 +96,11 @@ static struct mm_region early_map[] = {
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
-	{ CFG_SYS_FSL_OCRAM_BASE, CFG_SYS_FSL_OCRAM_BASE,
+	{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
 	  SYS_FSL_OCRAM_SPACE_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 	},
-	{ CFG_SYS_FSL_QSPI_BASE1, CFG_SYS_FSL_QSPI_BASE1,
+	{ CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
 	  CONFIG_SYS_FSL_QSPI_SIZE1,
 	  PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE},
 #ifdef CONFIG_FSL_IFC
@@ -114,7 +114,7 @@ static struct mm_region early_map[] = {
 	  CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 	},
-	{ CFG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
+	{ CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
 	  CONFIG_SYS_FSL_IFC_SIZE1,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 	},
@@ -130,9 +130,9 @@ static struct mm_region early_map[] = {
 	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 	},
 #ifdef CONFIG_FSL_IFC
-	/* Map IFC region #2 up to CFG_SYS_FLASH_BASE for NAND boot */
+	/* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
 	{ CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
-	  CFG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
+	  CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 	},
 #endif
@@ -159,7 +159,7 @@ static struct mm_region early_map[] = {
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
-	{ CFG_SYS_FSL_OCRAM_BASE, CFG_SYS_FSL_OCRAM_BASE,
+	{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
 	  SYS_FSL_OCRAM_SPACE_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 	},
@@ -168,7 +168,7 @@ static struct mm_region early_map[] = {
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
-	{ CFG_SYS_FSL_QSPI_BASE, CFG_SYS_FSL_QSPI_BASE,
+	{ CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
 	  CONFIG_SYS_FSL_QSPI_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 	},
@@ -204,7 +204,7 @@ static struct mm_region final_map[] = {
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
-	{ CFG_SYS_FSL_OCRAM_BASE, CFG_SYS_FSL_OCRAM_BASE,
+	{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
 	  SYS_FSL_OCRAM_SPACE_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 	},
@@ -213,12 +213,12 @@ static struct mm_region final_map[] = {
 	  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 	},
-	{ CFG_SYS_FSL_QSPI_BASE1, CFG_SYS_FSL_QSPI_BASE1,
+	{ CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
 	  CONFIG_SYS_FSL_QSPI_SIZE1,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
-	{ CFG_SYS_FSL_QSPI_BASE2, CFG_SYS_FSL_QSPI_BASE2,
+	{ CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
 	  CONFIG_SYS_FSL_QSPI_SIZE2,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
@@ -257,26 +257,26 @@ static struct mm_region final_map[] = {
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
-	{ CFG_SYS_PCIE1_PHYS_ADDR, CFG_SYS_PCIE1_PHYS_ADDR,
+	{ CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
-	  CFG_SYS_PCIE1_PHYS_SIZE,
+	  CONFIG_SYS_PCIE1_PHYS_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
-	{ CFG_SYS_PCIE2_PHYS_ADDR, CFG_SYS_PCIE2_PHYS_ADDR,
+	{ CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
-	  CFG_SYS_PCIE2_PHYS_SIZE,
+	  CONFIG_SYS_PCIE2_PHYS_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
-#ifdef CFG_SYS_PCIE3_PHYS_ADDR
+#ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
-	{ CFG_SYS_PCIE3_PHYS_ADDR, CFG_SYS_PCIE3_PHYS_ADDR,
+	{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
-	  CFG_SYS_PCIE3_PHYS_SIZE,
+	  CONFIG_SYS_PCIE3_PHYS_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
 #endif
-#ifdef CFG_SYS_PCIE4_PHYS_ADDR
+#ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
-	{ CFG_SYS_PCIE4_PHYS_ADDR, CFG_SYS_PCIE4_PHYS_ADDR,
+	{ CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
-	  CFG_SYS_PCIE4_PHYS_SIZE,
+	  CONFIG_SYS_PCIE4_PHYS_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
@@ -333,7 +333,7 @@ static struct mm_region final_map[] = {
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
-	{ CFG_SYS_FSL_OCRAM_BASE, CFG_SYS_FSL_OCRAM_BASE,
+	{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
 	  SYS_FSL_OCRAM_SPACE_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 	},
@@ -342,7 +342,7 @@ static struct mm_region final_map[] = {
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
-	{ CFG_SYS_FSL_QSPI_BASE, CFG_SYS_FSL_QSPI_BASE,
+	{ CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
 	  CONFIG_SYS_FSL_QSPI_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
@@ -368,19 +368,19 @@ static struct mm_region final_map[] = {
 	  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 	},
-	{ CFG_SYS_PCIE1_PHYS_ADDR, CFG_SYS_PCIE1_PHYS_ADDR,
+	{ CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
-	  CFG_SYS_PCIE1_PHYS_SIZE,
+	  CONFIG_SYS_PCIE1_PHYS_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
-	{ CFG_SYS_PCIE2_PHYS_ADDR, CFG_SYS_PCIE2_PHYS_ADDR,
+	{ CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
-	  CFG_SYS_PCIE2_PHYS_SIZE,
+	  CONFIG_SYS_PCIE2_PHYS_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
-#ifdef CFG_SYS_PCIE3_PHYS_ADDR
+#ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
-	{ CFG_SYS_PCIE3_PHYS_ADDR, CFG_SYS_PCIE3_PHYS_ADDR,
+	{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
-	  CFG_SYS_PCIE3_PHYS_SIZE,
+	  CONFIG_SYS_PCIE3_PHYS_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
@@ -391,7 +391,7 @@ static struct mm_region final_map[] = {
 	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 	},
 #endif
-#ifdef CFG_SYS_MEM_RESERVE_SECURE
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
 	{},	/* space holder for secure mem */
 #endif
 	{},
@@ -401,7 +401,7 @@ struct mm_region *mem_map = early_map;
 
 void cpu_name(char *name)
 {
-	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 	unsigned int i, svr, ver;
 
 	svr = gur_in32(&gur->svr);
@@ -430,7 +430,7 @@ void cpu_name(char *name)
 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 /*
  * To start MMU before DDR is available, we create MMU table in SRAM.
- * The base address of SRAM is CFG_SYS_FSL_OCRAM_BASE. We use three
+ * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
  * levels of translation tables here to cover 40-bit address space.
  * We use 4KB granule size, with 40 bits physical address, T0SZ=24
  * Address above EARLY_PGTABLE_SIZE (0x5000) is free for other purpose.
@@ -443,9 +443,9 @@ static inline void early_mmu_setup(void)
 
 	/* global data is already setup, no allocation yet */
 	if (el == 3)
-		gd->arch.tlb_addr = CFG_SYS_FSL_OCRAM_BASE;
+		gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE;
 	else
-		gd->arch.tlb_addr = CFG_SYS_DDR_SDRAM_BASE;
+		gd->arch.tlb_addr = CONFIG_SYS_DDR_SDRAM_BASE;
 	gd->arch.tlb_fillptr = gd->arch.tlb_addr;
 	gd->arch.tlb_size = EARLY_PGTABLE_SIZE;
 
@@ -466,7 +466,7 @@ static void fix_pcie_mmu_map(void)
 #ifdef CONFIG_ARCH_LS2080A
 	unsigned int i;
 	u32 svr, ver;
-	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 
 	svr = gur_in32(&gur->svr);
 	ver = SVR_SOC_VER(svr);
@@ -477,25 +477,25 @@ static void fix_pcie_mmu_map(void)
 	    (ver == SVR_LS2081A) || (ver == SVR_LS2041A)) {
 		for (i = 0; i < ARRAY_SIZE(final_map); i++) {
 			switch (final_map[i].phys) {
-			case CFG_SYS_PCIE1_PHYS_ADDR:
+			case CONFIG_SYS_PCIE1_PHYS_ADDR:
 				final_map[i].phys = 0x2000000000ULL;
 				final_map[i].virt = 0x2000000000ULL;
 				final_map[i].size = 0x800000000ULL;
 				break;
-			case CFG_SYS_PCIE2_PHYS_ADDR:
+			case CONFIG_SYS_PCIE2_PHYS_ADDR:
 				final_map[i].phys = 0x2800000000ULL;
 				final_map[i].virt = 0x2800000000ULL;
 				final_map[i].size = 0x800000000ULL;
 				break;
-#ifdef CFG_SYS_PCIE3_PHYS_ADDR
+#ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
-			case CFG_SYS_PCIE3_PHYS_ADDR:
+			case CONFIG_SYS_PCIE3_PHYS_ADDR:
 				final_map[i].phys = 0x3000000000ULL;
 				final_map[i].virt = 0x3000000000ULL;
 				final_map[i].size = 0x800000000ULL;
 				break;
 #endif
-#ifdef CFG_SYS_PCIE4_PHYS_ADDR
+#ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
-			case CFG_SYS_PCIE4_PHYS_ADDR:
+			case CONFIG_SYS_PCIE4_PHYS_ADDR:
 				final_map[i].phys = 0x3800000000ULL;
 				final_map[i].virt = 0x3800000000ULL;
 				final_map[i].size = 0x800000000ULL;
@@ -568,7 +568,7 @@ static inline void final_mmu_setup(void)
 		}
 	}
 
-#ifdef CFG_SYS_MEM_RESERVE_SECURE
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
 	if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
 		if (el == 3) {
 			/*
@@ -580,7 +580,7 @@ static inline void final_mmu_setup(void)
 			gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff;
 			final_map[index].virt = gd->arch.secure_ram & ~0x3;
 			final_map[index].phys = final_map[index].virt;
-			final_map[index].size = CFG_SYS_MEM_RESERVE_SECURE;
+			final_map[index].size = CONFIG_SYS_MEM_RESERVE_SECURE;
 			final_map[index].attrs = PTE_BLOCK_OUTER_SHARE;
 			gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED;
 			tlb_addr_save = gd->arch.tlb_addr;
@@ -775,7 +775,7 @@ enum boot_src get_boot_src(void)
 #if defined(CONFIG_FSL_LSCH3)
 	u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
 #elif defined(CONFIG_FSL_LSCH2)
-	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 #endif
 
 	if (current_el() == 2) {
@@ -863,7 +863,7 @@ enum env_location arch_env_get_location(enum env_operation op, int prio)
 
 u32 initiator_type(u32 cluster, int init_id)
 {
-	struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 	u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
 	u32 type = 0;
 
@@ -876,7 +876,7 @@ u32 initiator_type(u32 cluster, int init_id)
 
 u32 cpu_pos_mask(void)
 {
-	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 	int i = 0;
 	u32 cluster, type, mask = 0;
 
@@ -897,7 +897,7 @@ u32 cpu_pos_mask(void)
 
 u32 cpu_mask(void)
 {
-	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 	int i = 0, count = 0;
 	u32 cluster, type, mask = 0;
 
@@ -930,7 +930,7 @@ int cpu_numcores(void)
 int fsl_qoriq_core_to_cluster(unsigned int core)
 {
 	struct ccsr_gur __iomem *gur =
-		(void __iomem *)(CFG_SYS_FSL_GUTS_ADDR);
+		(void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
 	int i = 0, count = 0;
 	u32 cluster;
 
@@ -954,7 +954,7 @@ int fsl_qoriq_core_to_cluster(unsigned int core)
 u32 fsl_qoriq_core_to_type(unsigned int core)
 {
 	struct ccsr_gur __iomem *gur =
-		(void __iomem *)(CFG_SYS_FSL_GUTS_ADDR);
+		(void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
 	int i = 0, count = 0;
 	u32 cluster, type;
 
@@ -979,7 +979,7 @@ u32 fsl_qoriq_core_to_type(unsigned int core)
 #ifndef CONFIG_FSL_LSCH3
 uint get_svr(void)
 {
-	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 
 	return gur_in32(&gur->svr);
 }
@@ -988,7 +988,7 @@ uint get_svr(void)
 #ifdef CONFIG_DISPLAY_CPUINFO
 int print_cpuinfo(void)
 {
-	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 	struct sys_info sysinfo;
 	char buf[32];
 	unsigned int i, core;
@@ -1057,6 +1057,9 @@ int cpu_eth_init(struct bd_info *bis)
 
 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
 	error = fsl_mc_ldpaa_init(bis);
+#endif
+#ifdef CONFIG_FMAN_ENET
+	fm_standard_init(bis);
 #endif
 	return error;
 }
@@ -1176,9 +1179,9 @@ int arch_early_init_r(void)
 
 int timer_init(void)
 {
-	u32 __iomem *cntcr = (u32 *)CFG_SYS_FSL_TIMER_ADDR;
+	u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
 #ifdef CONFIG_FSL_LSCH3
-	u32 __iomem *cltbenr = (u32 *)CFG_SYS_FSL_PMU_CLTBENR;
+	u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
 #endif
 #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
 	defined(CONFIG_ARCH_LS1028A)
@@ -1227,7 +1230,7 @@ int timer_init(void)
 }
 
 #if !CONFIG_IS_ENABLED(SYSRESET)
-__efi_runtime_data u32 __iomem *rstcr = (u32 *)CFG_SYS_FSL_RST_ADDR;
+__efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
 
 void __efi_runtime reset_cpu(void)
 {
@@ -1308,22 +1311,22 @@ phys_size_t get_effective_memsize(void)
 	 * allocated from first region. If the memory extends to  the second
 	 * region (or the third region if applicable), Management Complex (MC)
 	 * memory should be put into the highest region, i.e. the end of DDR
-	 * memory. CFG_MAX_MEM_MAPPED is set to the size of first region so
+	 * memory. CONFIG_MAX_MEM_MAPPED is set to the size of first region so
 	 * U-Boot doesn't relocate itself into higher address. Should DDR be
 	 * configured to skip the first region, this function needs to be
 	 * adjusted.
 	 */
-	if (gd->ram_size > CFG_MAX_MEM_MAPPED) {
+	if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
-		ea_size = CFG_MAX_MEM_MAPPED;
+		ea_size = CONFIG_MAX_MEM_MAPPED;
 		rem = gd->ram_size - ea_size;
 	} else {
 		ea_size = gd->ram_size;
 	}
 
-#ifdef CFG_SYS_MEM_RESERVE_SECURE
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
 	/* Check if we have enough space for secure memory */
-	if (ea_size > CFG_SYS_MEM_RESERVE_SECURE)
+	if (ea_size > CONFIG_SYS_MEM_RESERVE_SECURE)
-		ea_size -= CFG_SYS_MEM_RESERVE_SECURE;
+		ea_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
 	else
 		printf("Error: No enough space for secure memory.\n");
 #endif
@@ -1430,7 +1433,7 @@ int dram_init_banksize(void)
 	 * gd->arch.secure_ram should be done to avoid running it repeatedly.
 	 */
 
-#ifdef CFG_SYS_MEM_RESERVE_SECURE
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
 	if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
 		debug("No need to run again, skip %s\n", __func__);
 
@@ -1438,12 +1441,12 @@ int dram_init_banksize(void)
 	}
 #endif
 
-	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
-	if (gd->ram_size > CFG_SYS_DDR_BLOCK1_SIZE) {
+	if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
-		gd->bd->bi_dram[0].size = CFG_SYS_DDR_BLOCK1_SIZE;
+		gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
-		gd->bd->bi_dram[1].start = CFG_SYS_DDR_BLOCK2_BASE;
+		gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
 		gd->bd->bi_dram[1].size = gd->ram_size -
-					  CFG_SYS_DDR_BLOCK1_SIZE;
+					  CONFIG_SYS_DDR_BLOCK1_SIZE;
 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
 		if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) {
 			gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE;
@@ -1455,17 +1458,17 @@ int dram_init_banksize(void)
 	} else {
 		gd->bd->bi_dram[0].size = gd->ram_size;
 	}
-#ifdef CFG_SYS_MEM_RESERVE_SECURE
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
 	if (gd->bd->bi_dram[0].size >
-				CFG_SYS_MEM_RESERVE_SECURE) {
+				CONFIG_SYS_MEM_RESERVE_SECURE) {
 		gd->bd->bi_dram[0].size -=
-				CFG_SYS_MEM_RESERVE_SECURE;
+				CONFIG_SYS_MEM_RESERVE_SECURE;
 		gd->arch.secure_ram = gd->bd->bi_dram[0].start +
 				      gd->bd->bi_dram[0].size;
 		gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-		gd->ram_size -= CFG_SYS_MEM_RESERVE_SECURE;
+		gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
 	}
-#endif	/* CFG_SYS_MEM_RESERVE_SECURE */
+#endif	/* CONFIG_SYS_MEM_RESERVE_SECURE */
 
 #if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
 	/* Assign memory for MC */
@@ -1517,7 +1520,7 @@ int dram_init_banksize(void)
 	}
 #endif
 
-#ifdef CFG_SYS_MEM_RESERVE_SECURE
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
 	debug("%s is called. gd->ram_size is reduced to %lu\n",
 	      __func__, (ulong)gd->ram_size);
 #endif
@@ -1568,7 +1571,7 @@ void update_early_mmu_table(void)
 
 	if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) {
 		mmu_change_region_attr(
-					CFG_SYS_SDRAM_BASE,
+					CONFIG_SYS_SDRAM_BASE,
 					gd->ram_size,
 					PTE_BLOCK_MEMTYPE(MT_NORMAL)	|
 					PTE_BLOCK_OUTER_SHARE		|
@@ -1576,8 +1579,8 @@ void update_early_mmu_table(void)
 					PTE_TYPE_VALID);
 	} else {
 		mmu_change_region_attr(
-					CFG_SYS_SDRAM_BASE,
+					CONFIG_SYS_SDRAM_BASE,
-					CFG_SYS_DDR_BLOCK1_SIZE,
+					CONFIG_SYS_DDR_BLOCK1_SIZE,
 					PTE_BLOCK_MEMTYPE(MT_NORMAL)	|
 					PTE_BLOCK_OUTER_SHARE		|
 					PTE_BLOCK_NS			|
@@ -1586,10 +1589,10 @@ void update_early_mmu_table(void)
 #ifndef CONFIG_SYS_DDR_BLOCK2_SIZE
 #error "Missing CONFIG_SYS_DDR_BLOCK2_SIZE"
 #endif
-		if (gd->ram_size - CFG_SYS_DDR_BLOCK1_SIZE >
+		if (gd->ram_size - CONFIG_SYS_DDR_BLOCK1_SIZE >
 		    CONFIG_SYS_DDR_BLOCK2_SIZE) {
 			mmu_change_region_attr(
-					CFG_SYS_DDR_BLOCK2_BASE,
+					CONFIG_SYS_DDR_BLOCK2_BASE,
 					CONFIG_SYS_DDR_BLOCK2_SIZE,
 					PTE_BLOCK_MEMTYPE(MT_NORMAL)	|
 					PTE_BLOCK_OUTER_SHARE		|
@@ -1598,7 +1601,7 @@ void update_early_mmu_table(void)
 			mmu_change_region_attr(
 					CONFIG_SYS_DDR_BLOCK3_BASE,
 					gd->ram_size -
-					CFG_SYS_DDR_BLOCK1_SIZE -
+					CONFIG_SYS_DDR_BLOCK1_SIZE -
 					CONFIG_SYS_DDR_BLOCK2_SIZE,
 					PTE_BLOCK_MEMTYPE(MT_NORMAL)	|
 					PTE_BLOCK_OUTER_SHARE		|
@@ -1608,9 +1611,9 @@ void update_early_mmu_table(void)
 #endif
 		{
 			mmu_change_region_attr(
-					CFG_SYS_DDR_BLOCK2_BASE,
+					CONFIG_SYS_DDR_BLOCK2_BASE,
 					gd->ram_size -
-					CFG_SYS_DDR_BLOCK1_SIZE,
+					CONFIG_SYS_DDR_BLOCK1_SIZE,
 					PTE_BLOCK_MEMTYPE(MT_NORMAL)	|
 					PTE_BLOCK_OUTER_SHARE		|
 					PTE_BLOCK_NS			|

arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3

@@ -116,10 +116,10 @@ Flash Layout
 Environment Variables
 =====================
 mcboottimeout:	MC boot timeout in milliseconds. If this variable is not defined
-		the value CFG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed.
+		the value CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed.
 
 mcmemsize:	MC DRAM block size in hex. If this variable is not defined, the value
-		CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed.
+		CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed.
 
 mcinitcmd:	This environment variable is defined to initiate MC and DPL deployment
 		from the location where it is stored(NOR, NAND, SD, SATA, USB)during

arch/arm/cpu/armv8/fsl-layerscape/fdt.c

@@ -171,9 +171,9 @@ static void fdt_fixup_gic(void *blob)
 {
 	int offset, err;
 	u64 reg[8];
-	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 	unsigned int val;
-	struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
+	struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
 	int align_64k = 0;
 
 	val = gur_in32(&gur->svr);
@@ -355,7 +355,7 @@ static int _fdt_fixup_pci_msi(void *blob, const char *name, int rev)
 
 static void fdt_fixup_msi(void *blob)
 {
-	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 	unsigned int rev;
 
 	rev = gur_in32(&gur->svr);
@@ -620,7 +620,7 @@ void fdt_fixup_pfe_firmware(void *blob)
 
 void ft_cpu_setup(void *blob, struct bd_info *bd)
 {
-	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 	unsigned int svr = gur_in32(&gur->svr);
 
 	/* delete crypto node if not on an E-processor */
@@ -635,7 +635,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
 		fdt_fixup_kaslr(blob);
 #endif
 
-		sec = (void __iomem *)CFG_SYS_FSL_SEC_ADDR;
+		sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
 		fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
 	}
 #endif
@@ -646,7 +646,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
 
 #ifdef CONFIG_SYS_NS16550
 	do_fixup_by_compat_u32(blob, "fsl,ns16550",
-			       "clock-frequency", CFG_SYS_NS16550_CLK, 1);
+			       "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
 #endif
 
 	do_fixup_by_path_u32(blob, "/sysclk", "clock-frequency",

arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c

@@ -40,7 +40,7 @@ int is_serdes_configured(enum srds_prtcl device)
 
 int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
 {
-	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 	u32 cfg = gur_in32(&gur->rcwsr[4]);
 	int i;
 
@@ -76,7 +76,7 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
 
 int get_serdes_protocol(void)
 {
-	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 	u32 cfg = gur_in32(&gur->rcwsr[4]) &
 			  FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
 	cfg >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
@@ -101,7 +101,7 @@ const char *serdes_clock_to_string(u32 clock)
 void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
 		 u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
 {
-	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 	u32 cfg;
 	int lane;
 
@@ -142,7 +142,7 @@ __weak int set_serdes_volt(int svdd)
 
 int setup_serdes_volt(u32 svdd)
 {
-	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 	struct ccsr_serdes *serdes1_base;
 #ifdef CONFIG_SYS_FSL_SRDS_2
 	struct ccsr_serdes *serdes2_base;
@@ -168,7 +168,7 @@ int setup_serdes_volt(u32 svdd)
 	if (svdd_cur == svdd_tar)
 		return 0;
 
-	serdes1_base = (void *)CFG_SYS_FSL_SERDES_ADDR;
+	serdes1_base = (void *)CONFIG_SYS_FSL_SERDES_ADDR;
 #ifdef CONFIG_SYS_FSL_SRDS_2
 	serdes2_base = (void *)serdes1_base + 0x10000;
 #endif
@@ -406,14 +406,14 @@ void fsl_serdes_init(void)
 {
 #ifdef CONFIG_SYS_FSL_SRDS_1
 	serdes_init(FSL_SRDS_1,
-		    CFG_SYS_FSL_SERDES_ADDR,
+		    CONFIG_SYS_FSL_SERDES_ADDR,
 		    FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK,
 		    FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT,
 		    serdes1_prtcl_map);
 #endif
 #ifdef CONFIG_SYS_FSL_SRDS_2
 	serdes_init(FSL_SRDS_2,
-		    CFG_SYS_FSL_SERDES_ADDR,
+		    CONFIG_SYS_FSL_SERDES_ADDR,
 		    FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK,
 		    FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT,
 		    serdes2_prtcl_map);

arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c

@@ -20,12 +20,16 @@ DECLARE_GLOBAL_DATA_PTR;
 
 void get_sys_info(struct sys_info *sys_info)
 {
-	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 /* rcw_tmp is needed to get FMAN clock, or to get cluster group A
  * mux 2 clock for LS1043A/LS1046A.
  */
-	__maybe_unused u32 rcw_tmp;
+#if defined(CONFIG_SYS_DPAA_FMAN) || \
-	struct ccsr_clk *clk = (void *)(CFG_SYS_FSL_CLK_ADDR);
+	    defined(CONFIG_ARCH_LS1046A) || \
+	    defined(CONFIG_ARCH_LS1043A)
+	u32 rcw_tmp;
+#endif
+	struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
 	unsigned int cpu;
 	const u8 core_cplx_pll[8] = {
 		[0] = 0,	/* CC1 PPL / 1 */
@@ -92,7 +96,7 @@ void get_sys_info(struct sys_info *sys_info)
 
 #define HWA_CGA_M1_CLK_SEL	0xe0000000
 #define HWA_CGA_M1_CLK_SHIFT	29
-#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD)
+#ifdef CONFIG_SYS_DPAA_FMAN
 	rcw_tmp = in_be32(&gur->rcwsr[7]);
 	switch ((rcw_tmp & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT) {
 	case 2:

arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c

@@ -86,7 +86,7 @@ int is_serdes_configured(enum srds_prtcl device)
 
 int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
 {
-	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 	u32 cfg = 0;
 	int i;
 
@@ -134,7 +134,7 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
 void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask,
 		 u32 sd_prctl_shift, u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
 {
-	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 	u32 cfg;
 	int lane;
 
@@ -399,18 +399,18 @@ static void do_pll_lock(u32 cfg,
 
 int setup_serdes_volt(u32 svdd)
 {
-	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 	struct ccsr_serdes __iomem *serdes1_base =
-			(void *)CFG_SYS_FSL_LSCH3_SERDES_ADDR;
+			(void *)CONFIG_SYS_FSL_LSCH3_SERDES_ADDR;
 	u32 cfg_rcwsrds1 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]);
 #ifdef CONFIG_SYS_FSL_SRDS_2
 	struct ccsr_serdes __iomem *serdes2_base =
-			(void *)(CFG_SYS_FSL_LSCH3_SERDES_ADDR + 0x10000);
+			(void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x10000);
 	u32 cfg_rcwsrds2 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]);
 #endif
 #ifdef CONFIG_SYS_NXP_SRDS_3
 	struct ccsr_serdes __iomem *serdes3_base =
-			(void *)(CFG_SYS_FSL_LSCH3_SERDES_ADDR + 0x20000);
+			(void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x20000);
 	u32 cfg_rcwsrds3 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS3_REGSR - 1]);
 #endif
 	u32 cfg_tmp;
@@ -585,7 +585,7 @@ void fsl_serdes_init(void)
 
 #ifdef CONFIG_SYS_FSL_SRDS_1
 	serdes_init(FSL_SRDS_1,
-		    CFG_SYS_FSL_LSCH3_SERDES_ADDR,
+		    CONFIG_SYS_FSL_LSCH3_SERDES_ADDR,
 		    FSL_CHASSIS3_SRDS1_REGSR,
 		    FSL_CHASSIS3_SRDS1_PRTCL_MASK,
 		    FSL_CHASSIS3_SRDS1_PRTCL_SHIFT,
@@ -593,7 +593,7 @@ void fsl_serdes_init(void)
 #endif
 #ifdef CONFIG_SYS_FSL_SRDS_2
 	serdes_init(FSL_SRDS_2,
-		    CFG_SYS_FSL_LSCH3_SERDES_ADDR + FSL_SRDS_2 * 0x10000,
+		    CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + FSL_SRDS_2 * 0x10000,
 		    FSL_CHASSIS3_SRDS2_REGSR,
 		    FSL_CHASSIS3_SRDS2_PRTCL_MASK,
 		    FSL_CHASSIS3_SRDS2_PRTCL_SHIFT,
@@ -601,7 +601,7 @@ void fsl_serdes_init(void)
 #endif
 #ifdef CONFIG_SYS_NXP_SRDS_3
 	serdes_init(NXP_SRDS_3,
-		    CFG_SYS_FSL_LSCH3_SERDES_ADDR + NXP_SRDS_3 * 0x10000,
+		    CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + NXP_SRDS_3 * 0x10000,
 		    FSL_CHASSIS3_SRDS3_REGSR,
 		    FSL_CHASSIS3_SRDS3_PRTCL_MASK,
 		    FSL_CHASSIS3_SRDS3_PRTCL_SHIFT,
@@ -611,7 +611,7 @@ void fsl_serdes_init(void)
 
 int serdes_set_env(int sd, int rcwsr, int sd_prctl_mask, int sd_prctl_shift)
 {
-	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 	char scfg[16], snum[16];
 	int cfgr = 0;
 	u32 cfg;

arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c

@@ -23,13 +23,13 @@ DECLARE_GLOBAL_DATA_PTR;
 
 void get_sys_info(struct sys_info *sys_info)
 {
-	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 	struct ccsr_clk_cluster_group __iomem *clk_grp[2] = {
-		(void *)(CFG_SYS_FSL_CH3_CLK_GRPA_ADDR),
+		(void *)(CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR),
-		(void *)(CFG_SYS_FSL_CH3_CLK_GRPB_ADDR)
+		(void *)(CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR)
 	};
 	struct ccsr_clk_ctrl __iomem *clk_ctrl =
-		(void *)(CFG_SYS_FSL_CH3_CLK_CTRL_ADDR);
+		(void *)(CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR);
 	unsigned int cpu;
 	const u8 core_cplx_pll[16] = {
 		[0] = 0,	/* CC1 PPL / 1 */
@@ -68,7 +68,7 @@ void get_sys_info(struct sys_info *sys_info)
 	uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
 	uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
 	unsigned long sysclk = get_board_sys_clk();
-	int cc_group[12] = CFG_SYS_FSL_CLUSTER_CLOCKS;
+	int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
 	u32 c_pll_sel, cplx_pll;
 	void *offset;
 

arch/arm/cpu/armv8/fsl-layerscape/icid.c

@@ -27,7 +27,7 @@ static void set_icid(struct icid_id_table *tbl, int size)
 void set_fman_icids(struct fman_icid_id_table *tbl, int size)
 {
 	int i;
-	ccsr_fman_t *fm = (void *)CFG_SYS_FSL_FM1_ADDR;
+	ccsr_fman_t *fm = (void *)CONFIG_SYS_FSL_FM1_ADDR;
 
 	for (i = 0; i < size; i++) {
 		out_be32(&fm->fm_bmi_common.fmbm_ppid[tbl[i].port_id - 1],
@@ -41,7 +41,7 @@ void set_icids(void)
 	/* setup general icid offsets */
 	set_icid(icid_tbl, icid_tbl_sz);
 
-#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD)
+#ifdef CONFIG_SYS_DPAA_FMAN
 	set_fman_icids(fman_icid_tbl, fman_icid_tbl_sz);
 #endif
 }

arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S

@@ -325,8 +325,8 @@ ENDPROC(fsl_ocram_init)
 
 ENTRY(fsl_clear_ocram)
 /* Clear OCRAM */
-	ldr	x0, =CFG_SYS_FSL_OCRAM_BASE
+	ldr	x0, =CONFIG_SYS_FSL_OCRAM_BASE
-	ldr	x1, =(CFG_SYS_FSL_OCRAM_BASE + CFG_SYS_FSL_OCRAM_SIZE)
+	ldr	x1, =(CONFIG_SYS_FSL_OCRAM_BASE + CONFIG_SYS_FSL_OCRAM_SIZE)
 	mov	x2, #0
 clear_loop:
 	str	x2, [x0]

arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c

@@ -10,7 +10,7 @@
 #include <fsl_sec.h>
 
 #ifdef CONFIG_SYS_DPAA_QBMAN
-struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = {
+struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
 	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
 	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
 	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
@@ -59,7 +59,7 @@ struct icid_id_table icid_tbl[] = {
 
 int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
 
-#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD)
+#ifdef CONFIG_SYS_DPAA_FMAN
 struct fman_icid_id_table fman_icid_tbl[] = {
 	/* port id, icid */
 	SET_FMAN_ICID_ENTRY(0x02, FSL_DPAA1_STREAM_ID_END),

arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c

@@ -9,7 +9,7 @@
 #include <asm/arch-fsl-layerscape/fsl_portals.h>
 
 #ifdef CONFIG_SYS_DPAA_QBMAN
-struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = {
+struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
 	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
 	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
 	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
@@ -58,7 +58,7 @@ struct icid_id_table icid_tbl[] = {
 
 int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
 
-#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD)
+#ifdef CONFIG_SYS_DPAA_FMAN
 struct fman_icid_id_table fman_icid_tbl[] = {
 	/* port id, icid */
 	SET_FMAN_ICID_ENTRY(0x02, FSL_DPAA1_STREAM_ID_END),

arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c

@@ -53,7 +53,7 @@ static struct serdes_config *serdes_cfg_tbl[] = {
 
 bool soc_has_mac1(void)
 {
-	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 	unsigned int svr = gur_in32(&gur->svr);
 	unsigned int version = SVR_SOC_VER(svr);
 

arch/arm/cpu/armv8/fsl-layerscape/mp.c

@@ -48,8 +48,8 @@ void update_os_arch_secondary_cores(uint8_t os_arch)
 #ifdef CONFIG_FSL_LSCH3
 static void wake_secondary_core_n(int cluster, int core, int cluster_cores)
 {
-	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
-	struct ccsr_reset __iomem *rst = (void *)(CFG_SYS_FSL_RST_ADDR);
+	struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
 	u32 mpidr = 0;
 
 	mpidr = ((cluster << 8) | core);
@@ -73,13 +73,13 @@ static void wake_secondary_core_n(int cluster, int core, int cluster_cores)
 
 int fsl_layerscape_wake_seconday_cores(void)
 {
-	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 #ifdef CONFIG_FSL_LSCH3
-	struct ccsr_reset __iomem *rst = (void *)(CFG_SYS_FSL_RST_ADDR);
+	struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
 	u32 svr, ver, cluster, type;
 	int j = 0, cluster_cores = 0;
 #elif defined(CONFIG_FSL_LSCH2)
-	struct ccsr_scfg __iomem *scfg = (void *)(CFG_SYS_FSL_SCFG_ADDR);
+	struct ccsr_scfg __iomem *scfg = (void *)(CONFIG_SYS_FSL_SCFG_ADDR);
 #endif
 	u32 cores, cpu_up_mask = 1;
 	int i, timeout = 10;

arch/arm/cpu/armv8/fsl-layerscape/ppa.c

@@ -253,7 +253,7 @@ int ppa_init(void)
 #endif
 
 #ifdef CONFIG_FSL_LSCH3
-	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 	boot_loc_ptr_l = &gur->bootlocptrl;
 	boot_loc_ptr_h = &gur->bootlocptrh;
 
@@ -261,7 +261,7 @@ int ppa_init(void)
 	loadable_l = &gur->scratchrw[4];
 	loadable_h = &gur->scratchrw[5];
 #elif defined(CONFIG_FSL_LSCH2)
-	struct ccsr_scfg __iomem *scfg = (void *)(CFG_SYS_FSL_SCFG_ADDR);
+	struct ccsr_scfg __iomem *scfg = (void *)(CONFIG_SYS_FSL_SCFG_ADDR);
 	boot_loc_ptr_l = &scfg->scratchrw[1];
 	boot_loc_ptr_h = &scfg->scratchrw[0];
 

arch/arm/cpu/armv8/fsl-layerscape/soc.c

@@ -80,7 +80,7 @@ int ls_gic_rd_tables_init(void *blob)
 
 bool soc_has_dp_ddr(void)
 {
-	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 	u32 svr = gur_in32(&gur->svr);
 
 	/* LS2085A, LS2088A, LS2048A has DP_DDR */
@@ -94,7 +94,7 @@ bool soc_has_dp_ddr(void)
 
 bool soc_has_aiop(void)
 {
-	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 	u32 svr = gur_in32(&gur->svr);
 
 	/* LS2085A has AIOP */
@@ -249,13 +249,13 @@ static void erratum_a008336(void)
 #ifdef CONFIG_SYS_FSL_ERRATUM_A008336
 	u32 *eddrtqcr1;
 
-#ifdef CFG_SYS_FSL_DCSR_DDR_ADDR
+#ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR
-	eddrtqcr1 = (void *)CFG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
+	eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
 	if (fsl_ddr_get_version(0) == 0x50200)
 		out_le32(eddrtqcr1, 0x63b30002);
 #endif
-#ifdef CFG_SYS_FSL_DCSR_DDR2_ADDR
+#ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR
-	eddrtqcr1 = (void *)CFG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
+	eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
 	if (fsl_ddr_get_version(0) == 0x50200)
 		out_le32(eddrtqcr1, 0x63b30002);
 #endif
@@ -271,8 +271,8 @@ static void erratum_a008514(void)
 #ifdef CONFIG_SYS_FSL_ERRATUM_A008514
 	u32 *eddrtqcr1;
 
-#ifdef CFG_SYS_FSL_DCSR_DDR3_ADDR
+#ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR
-	eddrtqcr1 = (void *)CFG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
+	eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
 	out_le32(eddrtqcr1, 0x63b20002);
 #endif
 #endif
@@ -412,7 +412,7 @@ void fsl_lsch3_early_init_f(void)
 /* Get VDD in the unit mV from voltage ID */
 int get_core_volt_from_fuse(void)
 {
-	struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 	int vdd;
 	u32 fusesr;
 	u8 vid;
@@ -462,7 +462,7 @@ int get_core_volt_from_fuse(void)
 static void erratum_a009660(void)
 {
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009660
-	u32 *eddrtqcr1 = (void *)CFG_SYS_FSL_SCFG_ADDR + 0x20c;
+	u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c;
 	out_be32(eddrtqcr1, 0x63b20042);
 #endif
 }
@@ -473,7 +473,7 @@ static void erratum_a008850_early(void)
 	/* part 1 of 2 */
 	struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
 						CONFIG_SYS_CCI400_OFFSET);
-	struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
+	struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
 
 	/* Skip if running at lower exception level */
 	if (current_el() < 3)
@@ -493,7 +493,7 @@ void erratum_a008850_post(void)
 	/* part 2 of 2 */
 	struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
 						CONFIG_SYS_CCI400_OFFSET);
-	struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
+	struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
 	u32 tmp;
 
 	/* Skip if running at lower exception level */
@@ -526,21 +526,21 @@ void erratum_a010315(void)
 static void erratum_a010539(void)
 {
 #if defined(CONFIG_SYS_FSL_ERRATUM_A010539) && defined(CONFIG_QSPI_BOOT)
-	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 	u32 porsr1;
 
 	porsr1 = in_be32(&gur->porsr1);
 	porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK;
-	out_be32((void *)(CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
+	out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
 		 porsr1);
-	out_be32((void *)(CFG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff);
+	out_be32((void *)(CONFIG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff);
 #endif
 }
 
 /* Get VDD in the unit mV from voltage ID */
 int get_core_volt_from_fuse(void)
 {
-	struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 	int vdd;
 	u32 fusesr;
 	u8 vid;
@@ -588,7 +588,7 @@ static int setup_core_volt(u32 vdd)
 #ifdef CONFIG_SYS_FSL_DDR
 static void ddr_enable_0v9_volt(bool en)
 {
-	struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
+	struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
 	u32 tmp;
 
 	tmp = ddr_in32(&ddr->ddr_cdr1);
@@ -629,7 +629,7 @@ int setup_chip_volt(void)
 #ifdef CONFIG_FSL_PFE
 void init_pfe_scfg_dcfg_regs(void)
 {
-	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
+	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 	u32 ecccr2;
 
 	out_be32(&scfg->pfeasbcr,
@@ -643,8 +643,8 @@ void init_pfe_scfg_dcfg_regs(void)
 	out_be32(&scfg->rd_qos1, (unsigned int)(SCFG_RD_QOS1_PFE1_QOS
 		 | SCFG_RD_QOS1_PFE2_QOS));
 
-	ecccr2 = in_be32(CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2);
+	ecccr2 = in_be32(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2);
-	out_be32((void *)CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2,
+	out_be32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2,
 		 ecccr2 | (unsigned int)DISABLE_PFE_ECC);
 }
 #endif
@@ -653,7 +653,7 @@ void fsl_lsch2_early_init_f(void)
 {
 	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
 					CONFIG_SYS_CCI400_OFFSET);
-	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
+	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 #if defined(CONFIG_FSL_QSPI) && defined(CONFIG_TFABOOT)
 	enum boot_src src;
 #endif

arch/arm/cpu/armv8/fsl-layerscape/spl.c

@@ -116,7 +116,7 @@ void board_init_f(ulong dummy)
 #endif
 	dram_init();
 #ifdef CONFIG_SPL_FSL_LS_PPA
-#ifndef CFG_SYS_MEM_RESERVE_SECURE
+#ifndef CONFIG_SYS_MEM_RESERVE_SECURE
 #error Need secure RAM for PPA
 #endif
 	/*

arch/arm/cpu/armv8/fwcall.c

@@ -103,7 +103,7 @@ void __noreturn psci_system_reset2(u32 reset_level, u32 cookie)
 {
 	struct pt_regs regs;
 
-	regs.regs[0] = ARM_PSCI_0_2_FN64_SYSTEM_RESET2;
+	regs.regs[0] = ARM_PSCI_1_1_FN64_SYSTEM_RESET2;
 	regs.regs[1] = PSCI_RESET2_TYPE_VENDOR | reset_level;
 	regs.regs[2] = cookie;
 	if (use_smc_for_psci)

arch/arm/cpu/armv8/psci.S

@@ -12,10 +12,11 @@
 
 /* Default PSCI function, return -1, Not Implemented */
 #define PSCI_DEFAULT(__fn) \
-	WEAK(__fn); \
+	ENTRY(__fn); \
 	mov	w0, #ARM_PSCI_RET_NI; \
 	ret; \
 	ENDPROC(__fn); \
+	.weak __fn
 
 /* PSCI function and ID table definition*/
 #define PSCI_TABLE(__id, __fn) \
@@ -206,7 +207,7 @@ handle_smc64:
  * used for the return value, while in this PSCI environment, X0 usually holds
  * the SMC function identifier, so X0 should be saved by caller function.
  */
-WEAK(psci_get_cpu_id)
+ENTRY(psci_get_cpu_id)
 #ifdef CONFIG_ARMV8_PSCI_CPUS_PER_CLUSTER
 	mrs	x9, MPIDR_EL1
 	ubfx	x9, x9, #8, #8
@@ -220,6 +221,7 @@ WEAK(psci_get_cpu_id)
 	add	x0, x10, x9
 	ret
 ENDPROC(psci_get_cpu_id)
+.weak psci_get_cpu_id
 
 /* CPU ID input in x0, stack top output in x0*/
 LENTRY(psci_get_cpu_stack_top)
@@ -259,9 +261,10 @@ handle_sync:
  * Override this function if custom error handling is
  * needed for asynchronous aborts
  */
-WEAK(plat_error_handler)
+ENTRY(plat_error_handler)
 	ret
 ENDPROC(plat_error_handler)
+.weak plat_error_handler
 
 handle_error:
 	bl	psci_get_cpu_id
@@ -320,8 +323,9 @@ ENTRY(psci_setup_vectors)
 	ret
 ENDPROC(psci_setup_vectors)
 
-WEAK(psci_arch_init)
+ENTRY(psci_arch_init)
 	ret
 ENDPROC(psci_arch_init)
+.weak psci_arch_init
 
 .popsection

arch/arm/cpu/armv8/sec_firmware.c

@@ -198,7 +198,7 @@ static int sec_firmware_load_image(const void *sec_firmware_img,
 		goto out;
 	}
 
-#ifdef CFG_SYS_MEM_RESERVE_SECURE
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
 	/*
 	 * The SEC Firmware must be stored in secure memory.
 	 * Append SEC Firmware to secure mmu table.
@@ -211,7 +211,7 @@ static int sec_firmware_load_image(const void *sec_firmware_img,
 	sec_firmware_addr = (gd->arch.secure_ram & MEM_RESERVE_SECURE_ADDR_MASK) +
 			gd->arch.tlb_size;
 #else
-#error "The CFG_SYS_MEM_RESERVE_SECURE must be defined when enabled SEC Firmware support"
+#error "The CONFIG_SYS_MEM_RESERVE_SECURE must be defined when enabled SEC Firmware support"
 #endif
 
 	/* Align SEC Firmware base address to 4K */

arch/arm/dts/Makefile

@@ -278,8 +278,7 @@ dtb-$(CONFIG_ARCH_MVEBU) +=			\
 	cn9132-db-A.dtb				\
 	cn9132-db-B.dtb				\
 	cn9130-crb-A.dtb			\
-	cn9130-crb-B.dtb			\
+	cn9130-crb-B.dtb
-	ac5-98dx35xx-rd.dtb
 endif
 
 dtb-$(CONFIG_ARCH_SYNQUACER) += synquacer-sc2a11-developerbox.dtb
@@ -383,8 +382,6 @@ dtb-$(CONFIG_ARCH_VERSAL) += \
 	versal-mini.dtb \
 	versal-mini-emmc0.dtb \
 	versal-mini-emmc1.dtb \
-	versal-mini-ospi-single.dtb \
-	versal-mini-qspi-single.dtb \
 	xilinx-versal-virt.dtb
 dtb-$(CONFIG_ARCH_VERSAL_NET) += \
 	versal-net-mini.dtb \
@@ -644,6 +641,7 @@ dtb-$(CONFIG_MACH_SUN8I_A33) += \
 	sun8i-a33-et-q8-v1.6.dtb \
 	sun8i-a33-ga10h-v1.1.dtb \
 	sun8i-a33-inet-d978-rev2.dtb \
+	sun8i-a33-inet-u70b-rev1.dtb \
 	sun8i-a33-ippo-q8h-v1.2.dtb \
 	sun8i-a33-olinuxino.dtb \
 	sun8i-a33-q8-tablet.dtb \
@@ -981,7 +979,6 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
 	imx8mp-dhcom-pdk2.dtb \
 	imx8mp-evk.dtb \
 	imx8mp-icore-mx8mp-edimm2.2.dtb \
-	imx8mp-msc-sm2s.dtb \
 	imx8mp-phyboard-pollux-rdk.dtb \
 	imx8mp-venice.dtb \
 	imx8mp-venice-gw74xx.dtb \
@@ -1259,9 +1256,6 @@ dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb \
 dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-sk.dtb \
 			      k3-am625-r5-sk.dtb
 
-dtb-$(CONFIG_SOC_K3_AM625) += k3-am62a7-sk.dtb \
-			      k3-am62a7-r5-sk.dtb
-
 dtb-$(CONFIG_ARCH_MEDIATEK) += \
 	mt7622-rfb.dtb \
 	mt7623a-unielec-u7623-02-emmc.dtb \

arch/arm/dts/ac5-98dx25xx.dtsi

@@ -1,277 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Device Tree For AC5.
- *
- * Copyright (C) 2021 Marvell
- * Copyright (C) 2022 Allied Telesis Labs
- */
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-
-/ {
-	model = "Marvell AC5 SoC";
-	compatible = "marvell,ac5";
-	interrupt-parent = <&gic>;
-	#address-cells = <2>;
-	#size-cells = <2>;
-
-	cpus {
-		#address-cells = <2>;
-		#size-cells = <0>;
-
-		cpu-map {
-			cluster0 {
-				core0 {
-					cpu = <&cpu0>;
-				};
-				core1 {
-					cpu = <&cpu1>;
-				};
-			};
-		};
-
-		cpu0: cpu@0 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a55";
-			reg = <0x0 0x0>;
-			enable-method = "psci";
-			next-level-cache = <&l2>;
-		};
-
-		cpu1: cpu@1 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a55";
-			reg = <0x0 0x100>;
-			enable-method = "psci";
-			next-level-cache = <&l2>;
-		};
-
-		l2: l2-cache {
-			compatible = "cache";
-		};
-	};
-
-	psci {
-		compatible = "arm,psci-0.2";
-		method = "smc";
-	};
-
-	timer {
-		compatible = "arm,armv8-timer";
-		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	pmu {
-		compatible = "arm,armv8-pmuv3";
-		interrupts = <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	soc {
-		compatible = "simple-bus";
-		#address-cells = <2>;
-		#size-cells = <2>;
-		ranges;
-		dma-ranges;
-
-		internal-regs@7f000000 {
-			#address-cells = <1>;
-			#size-cells = <1>;
-			compatible = "simple-bus";
-			/* 16M internal register @ 0x7f00_0000 */
-			ranges = <0x0 0x0 0x7f000000 0x1000000>;
-			dma-coherent;
-
-			uart0: serial@12000 {
-				compatible = "snps,dw-apb-uart";
-				reg = <0x12000 0x100>;
-				reg-shift = <2>;
-				interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
-				reg-io-width = <1>;
-				clocks = <&cnm_clock>;
-				status = "okay";
-			};
-
-			uart1: serial@12100 {
-				compatible = "snps,dw-apb-uart";
-				reg = <0x12100 0x100>;
-				reg-shift = <2>;
-				reg-io-width = <1>;
-				clocks = <&cnm_clock>;
-				status = "disabled";
-			};
-
-			uart2: serial@12200 {
-				compatible = "snps,dw-apb-uart";
-				reg = <0x12200 0x100>;
-				reg-shift = <2>;
-				reg-io-width = <1>;
-				clocks = <&cnm_clock>;
-				status = "disabled";
-			};
-
-			uart3: serial@12300 {
-				compatible = "snps,dw-apb-uart";
-				reg = <0x12300 0x100>;
-				reg-shift = <2>;
-				reg-io-width = <1>;
-				clocks = <&cnm_clock>;
-				status = "disabled";
-			};
-
-			mdio: mdio@22004 {
-				#address-cells = <1>;
-				#size-cells = <0>;
-				compatible = "marvell,orion-mdio";
-				reg = <0x22004 0x4>;
-				clocks = <&cnm_clock>;
-			};
-
-			i2c0: i2c@11000 {
-				compatible = "marvell,mv78230-i2c";
-				reg = <0x11000 0x20>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				clocks = <&cnm_clock>;
-				clock-names = "core";
-				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
-				clock-frequency=<100000>;
-				status = "disabled";
-			};
-
-			i2c1: i2c@11100 {
-				compatible = "marvell,mv78230-i2c";
-				reg = <0x11100 0x20>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				clocks = <&cnm_clock>;
-				clock-names = "core";
-				interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
-				clock-frequency=<100000>;
-				status = "disabled";
-			};
-
-			gpio0: gpio@18100 {
-				compatible = "marvell,orion-gpio";
-				reg = <0x18100 0x40>;
-				ngpios = <32>;
-				gpio-controller;
-				#gpio-cells = <2>;
-				status = "okay";
-			};
-
-			gpio1: gpio@18140 {
-				reg = <0x18140 0x40>;
-				compatible = "marvell,orion-gpio";
-				ngpios = <14>;
-				gpio-controller;
-				#gpio-cells = <2>;
-				status = "okay";
-			};
-		};
-
-		/*
-		 * Dedicated section for devices behind 32bit controllers so we
-		 * can configure specific DMA mapping for them
-		 */
-		behind-32bit-controller@7f000000 {
-			compatible = "simple-bus";
-			#address-cells = <0x2>;
-			#size-cells = <0x2>;
-			ranges = <0x0 0x0 0x0 0x7f000000 0x0 0x1000000>;
-			/* Host phy ram starts at 0x200M */
-			dma-ranges = <0x0 0x0 0x2 0x0 0x1 0x0>;
-			dma-coherent;
-
-			eth0: ethernet@20000 {
-				compatible = "marvell,armada-ac5-neta";
-				reg = <0x0 0x20000 0x0 0x4000>;
-				interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&cnm_clock>;
-				phy-mode = "sgmii";
-				status = "disabled";
-			};
-
-			eth1: ethernet@24000 {
-				compatible = "marvell,armada-ac5-neta";
-				reg = <0x0 0x24000 0x0 0x4000>;
-				interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&cnm_clock>;
-				phy-mode = "sgmii";
-				status = "disabled";
-			};
-
-			usb0: usb@80000 {
-				compatible = "marvell,ac5-ehci";
-				reg = <0x0 0x80000 0x0 0x500>;
-				interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
-				status = "disabled";
-			};
-
-			usb1: usb@a0000 {
-				compatible = "marvell,ac5-ehci";
-				reg = <0x0 0xa0000 0x0 0x500>;
-				interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
-				status = "disabled";
-			};
-		};
-
-		pinctrl0: pinctrl@80020100 {
-			compatible = "marvell,mvebu-pinctrl";
-			reg = <0 0x80020100 0 0x20>;
-			pin-count = <46>;
-			max-func = <0xf>;
-			status = "okay";
-		};
-
-		spi0: spi@805a0000 {
-			compatible = "marvell,armada-3700-spi";
-			reg = <0x0 0x805a0000 0x0 0x50>;
-			#address-cells = <0x1>;
-			#size-cells = <0x0>;
-			clocks = <&spi_clock>;
-			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
-			num-cs = <1>;
-			status = "disabled";
-		};
-
-		spi1: spi@805a8000 {
-			compatible = "marvell,armada-3700-spi";
-			reg = <0x0 0x805a8000 0x0 0x50>;
-			#address-cells = <0x1>;
-			#size-cells = <0x0>;
-			clocks = <&spi_clock>;
-			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
-			num-cs = <1>;
-			status = "disabled";
-		};
-
-		gic: interrupt-controller@80600000 {
-			compatible = "arm,gic-v3";
-			#interrupt-cells = <3>;
-			interrupt-controller;
-			reg = <0x0 0x80600000 0x0 0x10000>, /* GICD */
-			      <0x0 0x80660000 0x0 0x40000>; /* GICR */
-			interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
-		};
-	};
-
-	clocks {
-		cnm_clock: cnm-clock {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <328000000>;
-		};
-
-		spi_clock: spi-clock {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <200000000>;
-		};
-	};
-};

arch/arm/dts/ac5-98dx35xx-rd.dts

@@ -1,129 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Device Tree For RD-AC5X.
- *
- * Copyright (C) 2021 Marvell
- * Copyright (C) 2022 Allied Telesis Labs
- */
-/*
- * Device Tree file for Marvell Alleycat 5X development board
- * This board file supports the B configuration of the board
- */
-
-/dts-v1/;
-
-#include "ac5-98dx35xx.dtsi"
-
-/ {
-	model = "Marvell RD-AC5X Board";
-	compatible = "marvell,rd-ac5x", "marvell,ac5x", "marvell,ac5";
-
-	aliases {
-		serial0 = &uart0;
-		spiflash0 = &spiflash0;
-		gpio0 = &gpio0;
-		gpio1 = &gpio1;
-		ethernet0 = &eth0;
-		ethernet1 = &eth1;
-		spi0 = &spi0;
-		i2c0 = &i2c0;
-		i2c1 = &i2c1;
-		usb0 = &usb0;
-		usb1 = &usb1;
-		pinctrl0 = &pinctrl0;
-		sar-reg0 = "/config-space/sar-reg";
-	};
-
-	usb1phy: usb-phy {
-		compatible = "usb-nop-xceiv";
-		#phy-cells = <0>;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-};
-
-&uart0 {
-	status = "okay";
-};
-
-&mdio {
-	phy0: ethernet-phy@0 {
-	      reg = <0>;
-	};
-};
-
-&i2c0 {
-	status = "okay";
-};
-
-&i2c1 {
-	status = "okay";
-};
-
-&eth0 {
-	status = "okay";
-	phy-handle = <&phy0>;
-};
-
-/* USB0 is a host USB */
-&usb0 {
-	status = "okay";
-};
-
-/* USB1 is a peripheral USB */
-&usb1 {
-	status = "okay";
-	phys = <&usb1phy>;
-	phy-names = "usb-phy";
-	dr_mode = "peripheral";
-};
-
-&spi0 {
-	status = "okay";
-
-	spiflash0: flash@0 {
-		compatible = "jedec,spi-nor";
-		spi-max-frequency = <50000000>;
-		spi-tx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */
-		spi-rx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */
-		reg = <0>;
-
-		#address-cells = <1>;
-		#size-cells = <1>;
-	};
-};
-
-&pinctrl0 {
-	/*
-	 * MPP Bus:     MPP#     mode#
-	 * eMMC          [0-11]   0x1
-	 * SPI[0]        [12-17]  0x1
-	 * TSEN_INT      [18]     0x1
-	 * DEV_INIT      [19]     0x1
-	 * SPI[1]        [20-23]  0x3
-	 * UART[1]       [24-25]  0x3
-	 * I2C[0]        [26-27]  0x1
-	 * XSMI[0]       [28-29]  0x1 // SCH use SMI[0], reversed due to CPSS problem
-	 * SMI[1]        [30-31]  0x2 // SCH use XSMI[1], reversed due to CPSS problem
-	 * UART[0]       [32-33]  0x1
-	 * OOB_SMI       [34-35]  0x1
-	 * PTP_CLK0_OUT  [36]     0x1
-	 * PTP_PULSE_OUT [37]     0x1
-	 * RCVR_CLK_OUT  [38]     0x1
-	 * GPIO(in/out)  [39]     0x0
-	 * GPIO(in/out)  [40]     0x0
-	 * PTP_REF_CLK   [41]     0x1
-	 * PTP_CLK0      [42]     0x1
-	 * LED0_CLK      [43]     0x1
-	 * LED0_STB      [44]     0x1
-	 * LED0_DATA     [45]     0x1
-	 */
-	/*	     0    1    2    3    4    5    6    7    8    9 */
-	pin-func = < 1    1    1    1    1    1    1    1    1    1
-		     1    1    1    1    1    1    1    1    1    1
-		     3    3    3    3    3    3    1    1    1    1
-		     2    2    1    1    1    1    1    1    1    0
-		     0    1    1    1    1    1    >;
-};

arch/arm/dts/ac5-98dx35xx.dtsi

@@ -1,17 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Device Tree For AC5X.
- *
- * Copyright (C) 2022 Allied Telesis Labs
- */
-
-#include "ac5-98dx25xx.dtsi"
-
-/ {
-	model = "Marvell AC5X SoC";
-	compatible = "marvell,ac5x", "marvell,ac5";
-};
-
-&cnm_clock {
-	clock-frequency = <325000000>;
-};

arch/arm/dts/am335x-evm-u-boot.dtsi

@@ -6,9 +6,9 @@
 #include "am33xx-u-boot.dtsi"
 
 &l4_per {
-	u-boot,dm-pre-reloc;
+
 	segment@300000 {
-		u-boot,dm-pre-reloc;
+
 		target-module@e000 {
 			u-boot,dm-pre-reloc;
 
@@ -26,29 +26,3 @@
 &usb0 {
 	dr_mode = "peripheral";
 };
-
-&i2c0 {
-	u-boot,dm-pre-reloc;
-};
-
-&l4_wkup {
-	u-boot,dm-pre-reloc;
-	segment@200000 {
-		u-boot,dm-pre-reloc;
-		target-module@9000 {
-			u-boot,dm-pre-reloc;
-		};
-	};
-};
-
-&uart0 {
-	u-boot,dm-pre-reloc;
-};
-
-&mmc1 {
-	u-boot,dm-pre-reloc;
-};
-
-&mmc2 {
-	u-boot,dm-pre-reloc;
-};

arch/arm/dts/am335x-sancloud-bbe-lite-u-boot.dtsi

@@ -1,44 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
- * Copyright (C) 2021 SanCloud Ltd
- */
-
-#include "am335x-sancloud-bbe-u-boot.dtsi"
-
-&l4_wkup {
-	segment@200000 {
-		target-module@0 {
-			u-boot,dm-pre-reloc;
-		};
-	};
-};
-
-&prcm {
-	u-boot,dm-pre-reloc;
-};
-
-&per_cm {
-	u-boot,dm-pre-reloc;
-};
-
-&l4ls_clkctrl {
-	u-boot,dm-pre-reloc;
-};
-
-&l4_per {
-	u-boot,dm-pre-reloc;
-	segment@0 {
-		u-boot,dm-pre-reloc;
-		target-module@30000 {
-			u-boot,dm-pre-reloc;
-		};
-	};
-};
-
-&spi0 {
-	u-boot,dm-pre-reloc;
-	channel@0 {
-		u-boot,dm-pre-reloc;
-	};
-};

arch/arm/dts/am335x-sancloud-bbe-lite.dts

@@ -41,7 +41,7 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		compatible = "micron,spi-authenta", "jedec,spi-nor";
+		compatible = "micron,spi-authenta";
 
 		reg = <0>;
 		spi-max-frequency = <16000000>;

arch/arm/dts/am335x-sancloud-bbe-u-boot.dtsi

@@ -1,6 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2022 SanCloud Ltd
- */
-
-#include "am335x-evm-u-boot.dtsi"

arch/arm/dts/armada-ap80x.dtsi

@@ -181,7 +181,7 @@
 				reg-io-width = <1>;
 				clocks = <&ap_syscon 3>;
 				status = "disabled";
-				clock-frequency = <200000000>;
+
 			};
 
 			watchdog: watchdog@610000 {

arch/arm/dts/at91-sam9x60_curiosity.dts

@@ -49,13 +49,6 @@
 						atmel,pins =
 							<AT91_PIOD 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
 					};
-
-					usb1 {
-						pinctrl_usb_default: usb_default {
-							atmel,pins = <AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
-									AT91_PIOD 18 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
-						};
-					};
 			};
 		};
 	};
@@ -96,17 +89,3 @@
 	phy-mode = "rmii";
 	status = "okay";
 };
-
-&usb1 {
-	num-ports = <3>;
-	atmel,vbus-gpio = <0
-			   &pioD 15 GPIO_ACTIVE_HIGH
-			   &pioD 18 GPIO_ACTIVE_HIGH>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_usb_default>;
-	status = "okay";
-};
-
-&usb2 {
-	status = "okay";
-};

arch/arm/dts/at91-sama5d27_wlsom1_ek.dts

@@ -143,32 +143,7 @@
 					pinmux = <PIN_PC9__GPIO>;
 					bias-pull-up;
 				};
-
-				pinctrl_usb_default: usb_default {
-					pinmux = <PIN_PA10__GPIO>;
-					bias-disable;
-				};
-
-				pinctrl_usba_vbus: usba_vbus {
-					pinmux = <PIN_PA16__GPIO>;
-					bias-disable;
 			};
 		};
 	};
 };
-};
-
-&usb1 {
-	num-ports = <3>;
-	atmel,vbus-gpio = <0
-			   &pioA PIN_PA10 GPIO_ACTIVE_HIGH
-			   0
-			  >;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_usb_default>;
-	status = "okay";
-};
-
-&usb2 {
-	status = "okay";
-};

arch/arm/dts/at91-sama5d2_icp.dts

@@ -154,29 +154,7 @@
 						 <PIN_PA13__SDMMC0_CD>;
 					bias-disable;
 				};
-
-				pinctrl_usb_default: usb_default {
-					pinmux = <PIN_PC17__GPIO>;
-					bias-disable;
-				};
-
-				pinctrl_usba_vbus: usba_vbus {
-					pinmux = <PIN_PD23__GPIO>;
-					bias-disable;
 			};
 		};
 	};
 };
-};
-
-&usb1 {
-	num-ports = <3>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_usb_default>;
-	status = "okay";
-};
-
-&usb2 {
-	phy_type = "hsic";
-	status = "okay";
-};

arch/arm/dts/at91-sama7g5ek-u-boot.dtsi

@@ -10,88 +10,13 @@
  *
  */
 
-#include "sama7g5-pinfunc.h"
-#include <dt-bindings/reset/sama7g5-reset.h>
-#include <dt-bindings/clock/at91.h>
-
 / {
 	chosen {
 		u-boot,dm-pre-reloc;
 	};
 
-	utmi {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		usb_phy0: phy@0 {
-			compatible = "microchip,sama7g5-usb-phy";
-			sfr-phandle = <&sfr>;
-			reg = <0>;
-			clocks = <&utmi_clk USB_UTMI1>;
-			clock-names = "utmi_clk";
-			status = "disabled";
-			#phy-cells = <0>;
-		};
-
-		usb_phy1: phy@1 {
-			compatible = "microchip,sama7g5-usb-phy";
-			sfr-phandle = <&sfr>;
-			reg = <1>;
-			clocks = <&utmi_clk USB_UTMI2>;
-			clock-names = "utmi_clk";
-			status = "disabled";
-			#phy-cells = <0>;
-		};
-
-		usb_phy2: phy@2 {
-			compatible = "microchip,sama7g5-usb-phy";
-			sfr-phandle = <&sfr>;
-			reg = <2>;
-			clocks = <&utmi_clk USB_UTMI3>;
-			clock-names = "utmi_clk";
-			status = "disabled";
-			#phy-cells = <0>;
-		};
-	};
-
-	utmi_clk: utmi-clk {
-		compatible = "microchip,sama7g5-utmi-clk";
-		sfr-phandle = <&sfr>;
-		#clock-cells = <1>;
-		clocks = <&pmc PMC_TYPE_CORE 27>;
-		clock-names = "utmi_clk";
-		resets = <&reset_controller SAMA7G5_RESET_USB_PHY1>,
-			 <&reset_controller SAMA7G5_RESET_USB_PHY2>,
-			 <&reset_controller SAMA7G5_RESET_USB_PHY3>;
-		reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
-	};
-
 	soc {
 		u-boot,dm-pre-reloc;
-
-		usb2: usb@400000 {
-			compatible = "microchip,sama7g5-ohci", "usb-ohci";
-			reg = <0x00400000 0x100000>;
-			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&pmc PMC_TYPE_PERIPHERAL 106>, <&utmi_clk USB_UTMI1>, <&usb_clk>;
-			clock-names = "ohci_clk", "hclk", "uhpck";
-			status = "disabled";
-		};
-
-		usb3: usb@500000 {
-			compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
-			reg = <0x00500000 0x100000>;
-			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&usb_clk>, <&pmc PMC_TYPE_PERIPHERAL 106>;
-			clock-names = "usb_clk", "ehci_clk";
-			status = "disabled";
-		};
-
-		sfr: sfr@e1624000 {
-			compatible = "microchip,sama7g5-sfr", "syscon";
-			reg = <0xe1624000 0x4000>;
-		};
 	};
 };
 
@@ -113,11 +38,6 @@
 
 &pioA {
 	u-boot,dm-pre-reloc;
-
-	pinctrl_usb_default: usb_default {
-		pinmux = <PIN_PC6__GPIO>;
-		bias-disable;
-	};
 };
 
 &pit64b0 {
@@ -140,31 +60,3 @@
 	u-boot,dm-pre-reloc;
 };
 
-&usb2 {
-	num-ports = <3>;
-	atmel,vbus-gpio = <0
-			   0
-			   &pioA PIN_PC6 GPIO_ACTIVE_HIGH
-			  >;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_usb_default>;
-	phys = <&usb_phy2>;
-	phy-names = "usb";
-	status = "okay";
-};
-
-&usb3 {
-	status = "okay";
-};
-
-&usb_phy0 {
-	status = "okay";
-};
-
-&usb_phy1 {
-	status = "okay";
-};
-
-&usb_phy2 {
-	status = "okay";
-};

arch/arm/dts/at91-sama7g5ek.dts

@@ -45,13 +45,13 @@
 		};
 	};
 
-	gpio-keys {
+	gpio_keys {
 		compatible = "gpio-keys";
 
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_key_gpio_default>;
 
-		button {
+		bp1 {
 			label = "PB_USER";
 			gpios = <&pioA PIN_PA12 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_PROG1>;
@@ -244,8 +244,8 @@
 			regulators {
 				vdd_3v3: VDD_IO {
 					regulator-name = "VDD_IO";
-					regulator-min-microvolt = <3300000>;
+					regulator-min-microvolt = <1200000>;
-					regulator-max-microvolt = <3300000>;
+					regulator-max-microvolt = <3700000>;
 					regulator-initial-mode = <2>;
 					regulator-allowed-modes = <2>, <4>;
 					regulator-always-on;
@@ -264,8 +264,8 @@
 
 				vddioddr: VDD_DDR {
 					regulator-name = "VDD_DDR";
-					regulator-min-microvolt = <1350000>;
+					regulator-min-microvolt = <1300000>;
-					regulator-max-microvolt = <1350000>;
+					regulator-max-microvolt = <1450000>;
 					regulator-initial-mode = <2>;
 					regulator-allowed-modes = <2>, <4>;
 					regulator-always-on;
@@ -285,8 +285,8 @@
 
 				vddcore: VDD_CORE {
 					regulator-name = "VDD_CORE";
-					regulator-min-microvolt = <1150000>;
+					regulator-min-microvolt = <1100000>;
-					regulator-max-microvolt = <1150000>;
+					regulator-max-microvolt = <1850000>;
 					regulator-initial-mode = <2>;
 					regulator-allowed-modes = <2>, <4>;
 					regulator-always-on;
@@ -306,7 +306,7 @@
 				vddcpu: VDD_OTHER {
 					regulator-name = "VDD_OTHER";
 					regulator-min-microvolt = <1050000>;
-					regulator-max-microvolt = <1250000>;
+					regulator-max-microvolt = <1850000>;
 					regulator-initial-mode = <2>;
 					regulator-allowed-modes = <2>, <4>;
 					regulator-ramp-delay = <3125>;
@@ -326,8 +326,8 @@
 
 				vldo1: LDO1 {
 					regulator-name = "LDO1";
-					regulator-min-microvolt = <1800000>;
+					regulator-min-microvolt = <1200000>;
-					regulator-max-microvolt = <1800000>;
+					regulator-max-microvolt = <3700000>;
 					regulator-always-on;
 
 					regulator-state-standby {
@@ -707,6 +707,7 @@
 		ck_cd_rstn_vddsel {
 			pinmux = <PIN_PA0__SDMMC0_CK>,
 				 <PIN_PA2__SDMMC0_RSTN>,
+				 <PIN_PA14__SDMMC0_CD>,
 				 <PIN_PA11__SDMMC0_DS>;
 			slew-rate = <0>;
 			bias-pull-up;

arch/arm/dts/axp22x.dtsi

@@ -67,6 +67,12 @@
 		status = "disabled";
 	};
 
+	axp_gpio: gpio {
+		compatible = "x-powers,axp221-gpio";
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
 	regulators {
 		/* Default work frequency for buck regulators */
 		x-powers,dcdc-freq = <3000>;

arch/arm/dts/axp809.dtsi

@@ -50,4 +50,11 @@
 	compatible = "x-powers,axp809";
 	interrupt-controller;
 	#interrupt-cells = <1>;
+
+	axp_gpio: gpio {
+		compatible = "x-powers,axp809-gpio",
+			     "x-powers,axp221-gpio";
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
 };

arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi

@@ -3,8 +3,6 @@
  * Copyright 2018, 2021 NXP
  */
 
-#include "imx8qm-u-boot.dtsi"
-
 &{/imx8qm-pm} {
 
 	u-boot,dm-spl;

arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi

@@ -3,8 +3,6 @@
  * Copyright 2019 Toradex AG
  */
 
-#include "imx8qxp-u-boot.dtsi"
-
 &{/imx8qx-pm} {
 
 	u-boot,dm-pre-proper;

arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi

@@ -3,8 +3,6 @@
  * Copyright 2018, 2021 NXP
  */
 
-#include "imx8qxp-u-boot.dtsi"
-
 &{/imx8qx-pm} {
 
 	u-boot,dm-spl;

arch/arm/dts/imx6dl-wandboard-revd1-u-boot.dtsi

@@ -1 +0,0 @@
-#include "imx6qdl-wandboard-u-boot.dtsi"

arch/arm/dts/imx6q-wandboard-revd1-u-boot.dtsi

@@ -1 +0,0 @@
-#include "imx6qdl-wandboard-u-boot.dtsi"

arch/arm/dts/imx6qdl-hummingboard2-emmc-som-v15-u-boot.dtsi

@@ -15,22 +15,6 @@
 	};
 };
 
-&soc {
-	u-boot,dm-pre-reloc;
-};
-
-&aips1 {
-	u-boot,dm-pre-reloc;
-};
-
-&pinctrl_microsom_uart1 {
-	u-boot,dm-pre-reloc;
-};
-
-&uart1 {
-	u-boot,dm-pre-reloc;
-};
-
 &gpio2 {
 	u-boot,dm-pre-reloc;
 };

arch/arm/dts/imx6qdl-wandboard-u-boot.dtsi

@@ -1,9 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-
-#include "imx6qdl-u-boot.dtsi"
-
-/ {
-	aliases {
-		mmc0 = &usdhc3;
-	};
-};

arch/arm/dts/imx6qp-wandboard-revd1-u-boot.dtsi

@@ -1 +0,0 @@
-#include "imx6qdl-wandboard-u-boot.dtsi"

arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi

@@ -13,10 +13,6 @@
 	};
 };
 
-&aips4 {
-	u-boot,dm-spl;
-};
-
 &reg_usdhc2_vmmc {
 	u-boot,off-on-delay-us = <20000>;
 };
@@ -81,24 +77,12 @@
 	u-boot,dm-spl;
 };
 
-&reg_usbotg1 {
-
-};
-
 &uart2 {
 	u-boot,dm-spl;
 };
 
-&usbmisc1 {
-	u-boot,dm-spl;
-};
-
 &usbotg1 {
-	u-boot,dm-spl;
+	dr_mode="host";
-};
-
-&usbphynop1 {
-	u-boot,dm-spl;
 };
 
 &usdhc2 {

arch/arm/dts/imx8mm-evk.dtsi

@@ -75,11 +75,6 @@
 		linux,autosuspend-period = <125>;
 	};
 
-	audio_codec_bt_sco: audio-codec-bt-sco {
-		compatible = "linux,bt-sco";
-		#sound-dai-cells = <1>;
-	};
-
 	wm8524: audio-codec {
 		#sound-dai-cells = <0>;
 		compatible = "wlf,wm8524";
@@ -88,25 +83,6 @@
 		wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
 	};
 
-	sound-bt-sco {
-		compatible = "simple-audio-card";
-		simple-audio-card,name = "bt-sco-audio";
-		simple-audio-card,format = "dsp_a";
-		simple-audio-card,bitclock-inversion;
-		simple-audio-card,frame-master = <&btcpu>;
-		simple-audio-card,bitclock-master = <&btcpu>;
-
-		btcpu: simple-audio-card,cpu {
-			sound-dai = <&sai2>;
-			dai-tdm-slot-num = <2>;
-			dai-tdm-slot-width = <16>;
-		};
-
-		simple-audio-card,codec {
-			sound-dai = <&audio_codec_bt_sco 1>;
-		};
-	};
-
 	sound-wm8524 {
 		compatible = "simple-audio-card";
 		simple-audio-card,name = "wm8524-audio";
@@ -370,16 +346,6 @@
 	status = "okay";
 };
 
-&sai2 {
-	#sound-dai-cells = <0>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_sai2>;
-	assigned-clocks = <&clk IMX8MM_CLK_SAI2>;
-	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
-	assigned-clock-rates = <24576000>;
-	status = "okay";
-};
-
 &sai3 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_sai3>;
@@ -528,15 +494,6 @@
 		>;
 	};
 
-	pinctrl_sai2: sai2grp {
-		fsl,pins = <
-			MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK      0xd6
-			MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC     0xd6
-			MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0    0xd6
-			MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0    0xd6
-		>;
-	};
-
 	pinctrl_sai3: sai3grp {
 		fsl,pins = <
 			MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6

arch/arm/dts/imx8mm-icore-mx8mm.dtsi

@@ -2,7 +2,7 @@
 /*
  * Copyright (c) 2018 NXP
  * Copyright (c) 2019 Engicam srl
- * Copyright (c) 2020 Amarula Solutions(India)
+ * Copyright (c) 2020 Amarula Solutons(India)
  */
 
 / {

arch/arm/dts/imx8mm-mx8menlo.dts

@@ -20,13 +20,13 @@
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_led>;
 
-		led-1 {
+		user1 {
 			label = "TestLed601";
 			gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "mmc0";
 		};
 
-		led-2 {
+		user2 {
 			label = "TestLed602";
 			gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "heartbeat";
@@ -152,11 +152,11 @@
 	 * CPLD_reset is RESET_SOFT in schematic
 	 */
 	gpio-line-names =
-		"CPLD_D[6]", "CPLD_int", "CPLD_reset", "",
+		"CPLD_D[1]", "CPLD_int", "CPLD_reset", "",
-		"", "CPLD_D[7]", "", "",
+		"", "CPLD_D[0]", "", "",
-		"", "", "", "CPLD_D[5]",
+		"", "", "", "CPLD_D[2]",
-		"CPLD_D[4]", "CPLD_D[3]", "CPLD_D[2]", "CPLD_D[1]",
+		"CPLD_D[3]", "CPLD_D[4]", "CPLD_D[5]", "CPLD_D[6]",
-		"CPLD_D[0]", "", "", "",
+		"CPLD_D[7]", "", "", "",
 		"", "", "", "",
 		"", "", "", "KBD_intK",
 		"", "", "", "";

arch/arm/dts/imx8mm-u-boot.dtsi

@@ -9,7 +9,7 @@
 	};
 };
 
-&soc {
+&{/soc@0} {
 	u-boot,dm-pre-reloc;
 	u-boot,dm-spl;
 };