Merge branch 'patch/usb-fam' into allwinner

# Conflicts:
#	drivers/phy/allwinner/Kconfig

Kconfig

@@ -459,7 +459,7 @@ config BUILD_TARGET
 	default "u-boot-spl.kwb" if ARCH_MVEBU && SPL
 	default "u-boot-elf.srec" if RCAR_GEN3
 	default "u-boot.itb" if !BINMAN && SPL_LOAD_FIT && (ARCH_ROCKCHIP || \
-				ARCH_SUNXI || RISCV || ARCH_ZYNQMP)
+				RISCV || ARCH_ZYNQMP)
 	default "u-boot.kwb" if ARCH_KIRKWOOD
 	default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT
 	default "u-boot-with-spl.imx" if ARCH_MX6 && SPL
@@ -508,9 +508,6 @@ config SYS_LOAD_ADDR
 	hex "Address in memory to use by default"
 	default 0x01000000 if ARCH_SOCFPGA
 	default 0x02000000 if PPC || X86
-	default 0x81000000 if MACH_SUNIV
-	default 0x22000000 if MACH_SUN9I
-	default 0x42000000 if ARCH_SUNXI
 	default 0x82000000 if ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_K3
 	default 0x82000000 if ARCH_MX6 && (MX6SL || MX6SLL  || MX6SX || MX6UL || MX6ULL)
 	default 0x12000000 if ARCH_MX6 && !(MX6SL || MX6SLL  || MX6SX || MX6UL || MX6ULL)

Makefile

@@ -1013,6 +1013,23 @@ INPUTS-y += u-boot.img
 endif
 endif
 
+ifeq ($(CONFIG_MACH_SUN8I_H3)$(CONFIG_ARMV7_PSCI),yy)
+INPUTS-$(CONFIG_ARMV7_PSCI) += u-boot-resume.img
+
+MKIMAGEFLAGS_u-boot-resume.img := -B 0x400 -T sunxi_egon
+
+u-boot-resume.img: u-boot-resume.bin
+	$(call if_changed,mkimage)
+
+OBJCOPYFLAGS_u-boot-resume.bin := -O binary
+
+u-boot-resume.bin: u-boot-resume.o
+	$(call if_changed,objcopy)
+
+u-boot-resume.S: u-boot
+	@sed -En 's/(0x[[:xdigit:]]+) +psci_cpu_entry/ldr pc, =\1/p' $<.map > $@
+endif
+
 INPUTS-$(CONFIG_X86) += u-boot-x86-start16.bin u-boot-x86-reset16.bin \
 	$(if $(CONFIG_SPL_X86_16BIT_INIT),spl/u-boot-spl.bin) \
 	$(if $(CONFIG_TPL_X86_16BIT_INIT),tpl/u-boot-tpl.bin)

arch/Kconfig

@@ -458,6 +458,7 @@ source "arch/Kconfig.nxp"
 endif
 
 source "board/keymile/Kconfig"
+source "board/sunxi/Kconfig"
 
 if MIPS || MICROBLAZE
 

arch/arm/Kconfig

@@ -1133,60 +1133,17 @@ config ARCH_SOCFPGA
 
 config ARCH_SUNXI
 	bool "Support sunxi (Allwinner) SoCs"
-	select BINMAN
-	select CMD_GPIO
-	select CMD_MMC if MMC
-	select CMD_USB if DISTRO_DEFAULTS && USB_HOST
-	select CLK
-	select DM
-	select DM_ETH
-	select DM_GPIO
-	select DM_I2C if I2C
-	select DM_SPI if SPI
-	select DM_SPI_FLASH if SPI
-	select DM_KEYBOARD
-	select DM_MMC if MMC
-	select DM_SCSI if SCSI
-	select DM_SERIAL
+	select BOARD_SUNXI
 	select GPIO_EXTRA_HEADER
-	select OF_BOARD_SETUP
 	select OF_CONTROL
 	select OF_SEPARATE
-	select PINCTRL
-	select SPECIFY_CONSOLE_INDEX
-	select SPL_SEPARATE_BSS if SPL
+	select SPECIFY_CONSOLE_INDEX if SERIAL
 	select SPL_STACK_R if SPL
 	select SPL_SYS_MALLOC_SIMPLE if SPL
 	select SPL_SYS_THUMB_BUILD if !ARM64
-	select SUNXI_GPIO
-	select SYS_NS16550
 	select SYS_THUMB_BUILD if !ARM64
-	select USB if DISTRO_DEFAULTS
-	select USB_KEYBOARD if DISTRO_DEFAULTS && USB_HOST
-	select USB_STORAGE if DISTRO_DEFAULTS && USB_HOST
 	select SPL_USE_TINY_PRINTF
-	select USE_PREBOOT
-	select SYS_RELOC_GD_ENV_ADDR
-	imply BOARD_LATE_INIT
-	imply CMD_DM
-	imply CMD_GPT
-	imply CMD_UBI if MTD_RAW_NAND
-	imply DISTRO_DEFAULTS
-	imply FAT_WRITE
-	imply FIT
-	imply OF_LIBFDT_OVERLAY
-	imply PRE_CONSOLE_BUFFER
-	imply SPL_GPIO
-	imply SPL_LIBCOMMON_SUPPORT
-	imply SPL_LIBGENERIC_SUPPORT
-	imply SPL_MMC if MMC
-	imply SPL_POWER
-	imply SPL_SERIAL
-	imply SYSRESET
-	imply SYSRESET_WATCHDOG
-	imply SYSRESET_WATCHDOG_AUTO
-	imply USB_GADGET
-	imply WDT
+	imply SPL_LOAD_FIT
 
 config ARCH_U8500
 	bool "ST-Ericsson U8500 Series"

arch/arm/cpu/armv7/Kconfig

@@ -75,11 +75,15 @@ config ARMV7_PSCI
 choice
 	prompt "Supported PSCI version"
 	depends on ARMV7_PSCI
+	default ARMV7_PSCI_1_1 if MACH_SUN8I_A33 || MACH_SUN8I_H3
 	default ARMV7_PSCI_0_1 if ARCH_SUNXI
 	default ARMV7_PSCI_1_0
 	help
 	  Select the supported PSCI version.
 
+config ARMV7_PSCI_1_1
+	bool "PSCI V1.1"
+
 config ARMV7_PSCI_1_0
 	bool "PSCI V1.0"
 

arch/arm/cpu/armv7/sunxi/Makefile

@@ -13,8 +13,12 @@ obj-$(CONFIG_MACH_SUN6I)	+= sram.o
 obj-$(CONFIG_MACH_SUN8I)	+= sram.o
 
 ifndef CONFIG_SPL_BUILD
+ifneq ($(CONFIG_MACH_SUN8I_A33)$(CONFIG_MACH_SUN8I_H3),)
+obj-$(CONFIG_ARMV7_PSCI)	+= psci-scpi.o
+else
 obj-$(CONFIG_ARMV7_PSCI)	+= psci.o
 endif
+endif
 
 ifdef CONFIG_SPL_BUILD
 obj-y	+= fel_utils.o

arch/arm/cpu/armv7/sunxi/psci-scpi.c

@@ -0,0 +1,455 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
+ * Copyright (C) 2018-2021 Samuel Holland <samuel@sholland.org>
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/cpucfg.h>
+#include <asm/armv7.h>
+#include <asm/gic.h>
+#include <asm/io.h>
+#include <asm/psci.h>
+#include <asm/secure.h>
+#include <asm/system.h>
+
+#define	GICD_BASE		(SUNXI_GIC400_BASE + GIC_DIST_OFFSET)
+#define	GICC_BASE		(SUNXI_GIC400_BASE + GIC_CPU_OFFSET_A15)
+
+#define HW_ON			0
+#define HW_OFF			1
+#define HW_STANDBY		2
+
+#define MPIDR_AFFLVL0(mpidr)	(mpidr & 0xf)
+#define MPIDR_AFFLVL1(mpidr)	(mpidr >> 8 & 0xf)
+
+#if defined(CONFIG_MACH_SUN8I_H3)
+#define SCPI_SHMEM_BASE		0x0004be00
+#else
+#define SCPI_SHMEM_BASE		0x00053e00
+#endif
+#define SCPI_SHMEM		((struct scpi_shmem *)SCPI_SHMEM_BASE)
+
+#define SCPI_RX_CHANNEL		1
+#define SCPI_TX_CHANNEL		0
+#define SCPI_VIRTUAL_CHANNEL	BIT(0)
+
+#define SCPI_MESSAGE_SIZE	0x100
+#define SCPI_PAYLOAD_SIZE	(SCPI_MESSAGE_SIZE - sizeof(struct scpi_header))
+
+#define SUNXI_MSGBOX_BASE	0x01c17000
+#define REMOTE_IRQ_STAT_REG	(SUNXI_MSGBOX_BASE + 0x0050)
+#define LOCAL_IRQ_STAT_REG	(SUNXI_MSGBOX_BASE + 0x0070)
+#define MSG_STAT_REG(n)		(SUNXI_MSGBOX_BASE + 0x0140 + 0x4 * (n))
+#define MSG_DATA_REG(n)		(SUNXI_MSGBOX_BASE + 0x0180 + 0x4 * (n))
+
+#define RX_IRQ(n)		BIT(0 + 2 * (n))
+#define TX_IRQ(n)		BIT(1 + 2 * (n))
+
+enum {
+	CORE_POWER_LEVEL		= 0,
+	CLUSTER_POWER_LEVEL		= 1,
+	CSS_POWER_LEVEL			= 2,
+};
+
+enum {
+	SCPI_CMD_SCP_READY		= 0x01,
+	SCPI_CMD_SET_CSS_POWER_STATE	= 0x03,
+	SCPI_CMD_GET_CSS_POWER_STATE	= 0x04,
+	SCPI_CMD_SET_SYS_POWER_STATE	= 0x05,
+};
+
+enum {
+	SCPI_E_OK			= 0,
+	SCPI_E_PARAM			= 1,
+	SCPI_E_ALIGN			= 2,
+	SCPI_E_SIZE			= 3,
+	SCPI_E_HANDLER			= 4,
+	SCPI_E_ACCESS			= 5,
+	SCPI_E_RANGE			= 6,
+	SCPI_E_TIMEOUT			= 7,
+	SCPI_E_NOMEM			= 8,
+	SCPI_E_PWRSTATE			= 9,
+	SCPI_E_SUPPORT			= 10,
+	SCPI_E_DEVICE			= 11,
+	SCPI_E_BUSY			= 12,
+	SCPI_E_OS			= 13,
+	SCPI_E_DATA			= 14,
+	SCPI_E_STATE			= 15,
+};
+
+enum {
+	SCPI_POWER_ON			= 0x00,
+	SCPI_POWER_RETENTION		= 0x01,
+	SCPI_POWER_OFF			= 0x03,
+};
+
+enum {
+	SCPI_SYSTEM_SHUTDOWN		= 0x00,
+	SCPI_SYSTEM_REBOOT		= 0x01,
+	SCPI_SYSTEM_RESET		= 0x02,
+};
+
+struct scpi_header {
+	u8			command;
+	u8			sender;
+	u16			size;
+	u32			status;
+};
+
+struct scpi_message {
+	struct scpi_header	header;
+	u8			payload[SCPI_PAYLOAD_SIZE];
+};
+
+struct scpi_shmem {
+	struct scpi_message	rx;
+	struct scpi_message	tx;
+};
+
+static bool __secure_data gic_dist_init;
+
+static u32 __secure_data lock;
+
+static inline u32 __secure read_mpidr(void)
+{
+	u32 val;
+
+	asm volatile ("mrc p15, 0, %0, c0, c0, 5" : "=r" (val));
+
+	return val;
+}
+
+static void __secure scpi_begin_command(void)
+{
+	u32 mpidr = read_mpidr();
+
+	do {
+		while (readl(&lock));
+		writel(mpidr, &lock);
+		dsb();
+	} while (readl(&lock) != mpidr);
+	while (readl(REMOTE_IRQ_STAT_REG) & RX_IRQ(SCPI_TX_CHANNEL));
+}
+
+static void __secure scpi_send_command(void)
+{
+	writel(SCPI_VIRTUAL_CHANNEL, MSG_DATA_REG(SCPI_TX_CHANNEL));
+}
+
+static void __secure scpi_wait_response(void)
+{
+	while (!readl(MSG_STAT_REG(SCPI_RX_CHANNEL)));
+}
+
+static void __secure scpi_end_command(void)
+{
+	while (readl(MSG_STAT_REG(SCPI_RX_CHANNEL)))
+		readl(MSG_DATA_REG(SCPI_RX_CHANNEL));
+	writel(RX_IRQ(SCPI_RX_CHANNEL), LOCAL_IRQ_STAT_REG);
+	writel(0, &lock);
+}
+
+static void __secure scpi_set_css_power_state(u32 target_cpu, u32 core_state,
+					      u32 cluster_state, u32 css_state)
+{
+	struct scpi_shmem *shmem = SCPI_SHMEM;
+
+	scpi_begin_command();
+
+	shmem->tx.header.command = SCPI_CMD_SET_CSS_POWER_STATE;
+	shmem->tx.header.size = 4;
+
+	shmem->tx.payload[0] = target_cpu    >> 4 | target_cpu;
+	shmem->tx.payload[1] = cluster_state << 4 | core_state;
+	shmem->tx.payload[2] = css_state;
+	shmem->tx.payload[3] = 0;
+
+	scpi_send_command();
+	scpi_end_command();
+}
+
+static s32 __secure scpi_get_css_power_state(u32 target_cpu, u8 *core_states,
+					     u8 *cluster_state)
+{
+	struct scpi_shmem *shmem = SCPI_SHMEM;
+	u32 cluster = MPIDR_AFFLVL1(target_cpu);
+	u32 offset;
+	s32 ret;
+
+	scpi_begin_command();
+
+	shmem->tx.header.command = SCPI_CMD_GET_CSS_POWER_STATE;
+	shmem->tx.header.size = 0;
+
+	scpi_send_command();
+	scpi_wait_response();
+
+	for (offset = 0; offset < shmem->rx.header.size; offset += 2) {
+		if ((shmem->rx.payload[offset] & 0xf) == cluster) {
+			*cluster_state = shmem->rx.payload[offset+0] >> 4;
+			*core_states   = shmem->rx.payload[offset+1];
+
+			break;
+		}
+	}
+
+	ret = shmem->rx.header.status;
+
+	scpi_end_command();
+
+	return ret;
+}
+
+static s32 __secure scpi_set_sys_power_state(u32 sys_state)
+{
+	struct scpi_shmem *shmem = SCPI_SHMEM;
+	s32 ret;
+
+	scpi_begin_command();
+
+	shmem->tx.header.command = SCPI_CMD_SET_SYS_POWER_STATE;
+	shmem->tx.header.size = 1;
+
+	shmem->tx.payload[0] = sys_state;
+
+	scpi_send_command();
+	scpi_wait_response();
+
+	ret = shmem->rx.header.status;
+
+	scpi_end_command();
+
+	return ret;
+}
+
+void psci_enable_smp(void);
+
+static s32 __secure psci_suspend_common(u32 pc, u32 context_id, u32 core_state,
+					u32 cluster_state, u32 css_state)
+
+{
+	u32 target_cpu = read_mpidr();
+
+	if (core_state == SCPI_POWER_OFF)
+		psci_save(MPIDR_AFFLVL0(target_cpu), pc, context_id);
+	if (css_state == SCPI_POWER_OFF)
+		gic_dist_init = true;
+
+	scpi_set_css_power_state(target_cpu, core_state,
+				 cluster_state, css_state);
+
+	psci_cpu_off_common();
+
+	wfi();
+
+	psci_enable_smp();
+
+	return ARM_PSCI_RET_SUCCESS;
+}
+
+u32 __secure psci_version(void)
+{
+	return ARM_PSCI_VER_1_1;
+}
+
+s32 __secure psci_cpu_suspend(u32 __always_unused function_id,
+			      u32 power_state, u32 pc, u32 context_id)
+{
+	return psci_suspend_common(pc, context_id,
+				   power_state >> 0 & 0xf,
+				   power_state >> 4 & 0xf,
+				   power_state >> 8 & 0xf);
+}
+
+s32 __secure psci_cpu_off(void)
+{
+	u32 pc = 0, context_id = 0;
+
+	return psci_suspend_common(pc, context_id, SCPI_POWER_OFF,
+				   SCPI_POWER_OFF, SCPI_POWER_ON);
+}
+
+s32 __secure psci_cpu_on(u32 __always_unused function_id,
+			 u32 target_cpu, u32 pc, u32 context_id)
+{
+	psci_save(MPIDR_AFFLVL0(target_cpu), pc, context_id);
+
+	scpi_set_css_power_state(target_cpu, SCPI_POWER_ON,
+				 SCPI_POWER_ON, SCPI_POWER_ON);
+
+	return ARM_PSCI_RET_SUCCESS;
+}
+
+s32 __secure psci_affinity_info(u32 function_id,
+				u32 target_cpu, u32 power_level)
+{
+	if (power_level != CORE_POWER_LEVEL)
+		return ARM_PSCI_RET_INVAL;
+
+	/* This happens to have the same HW_ON/HW_OFF encoding. */
+	return psci_node_hw_state(function_id, target_cpu, power_level);
+}
+
+void __secure psci_system_off(void)
+{
+	scpi_set_sys_power_state(SCPI_SYSTEM_SHUTDOWN);
+
+	/* Wait to be turned off. */
+	for (;;) wfi();
+}
+
+void __secure psci_system_reset(void)
+{
+	scpi_set_sys_power_state(SCPI_SYSTEM_REBOOT);
+
+	/* Wait to be turned off. */
+	for (;;) wfi();
+}
+
+s32 __secure psci_features(u32 __always_unused function_id,
+			   u32 psci_fid)
+{
+	switch (psci_fid) {
+	case ARM_PSCI_0_2_FN_PSCI_VERSION:
+	case ARM_PSCI_0_2_FN_CPU_SUSPEND:
+	case ARM_PSCI_0_2_FN_CPU_OFF:
+	case ARM_PSCI_0_2_FN_CPU_ON:
+	case ARM_PSCI_0_2_FN_AFFINITY_INFO:
+	case ARM_PSCI_0_2_FN_SYSTEM_OFF:
+	case ARM_PSCI_0_2_FN_SYSTEM_RESET:
+	case ARM_PSCI_1_0_FN_PSCI_FEATURES:
+	case ARM_PSCI_1_0_FN_CPU_DEFAULT_SUSPEND:
+	case ARM_PSCI_1_0_FN_NODE_HW_STATE:
+	case ARM_PSCI_1_0_FN_SYSTEM_SUSPEND:
+	case ARM_PSCI_1_1_FN_SYSTEM_RESET2:
+		return ARM_PSCI_RET_SUCCESS;
+	default:
+		return ARM_PSCI_RET_NI;
+	}
+}
+
+s32 __secure psci_cpu_default_suspend(u32 __always_unused function_id,
+				      u32 pc, u32 context_id)
+{
+	return psci_suspend_common(pc, context_id, SCPI_POWER_OFF,
+				   SCPI_POWER_OFF, SCPI_POWER_RETENTION);
+}
+
+s32 __secure psci_node_hw_state(u32 __always_unused function_id,
+				u32 target_cpu, u32 power_level)
+{
+	u32 core = MPIDR_AFFLVL0(target_cpu);
+	u8 core_states, cluster_state;
+
+	if (power_level >= CSS_POWER_LEVEL)
+		return HW_ON;
+	if (scpi_get_css_power_state(target_cpu, &core_states, &cluster_state))
+		return ARM_PSCI_RET_NI;
+	if (power_level == CLUSTER_POWER_LEVEL) {
+		if (cluster_state == SCPI_POWER_ON)
+			return HW_ON;
+		if (cluster_state < SCPI_POWER_OFF)
+			return HW_STANDBY;
+		return HW_OFF;
+	}
+
+	return (core_states & BIT(core)) ? HW_ON : HW_OFF;
+}
+
+s32 __secure psci_system_suspend(u32 __always_unused function_id,
+				 u32 pc, u32 context_id)
+{
+	return psci_suspend_common(pc, context_id, SCPI_POWER_OFF,
+				   SCPI_POWER_OFF, SCPI_POWER_OFF);
+}
+
+s32 __secure psci_system_reset2(u32 __always_unused function_id,
+				u32 reset_type, u32 cookie)
+{
+	s32 ret;
+
+	if (reset_type)
+		return ARM_PSCI_RET_INVAL;
+
+	ret = scpi_set_sys_power_state(SCPI_SYSTEM_RESET);
+	if (ret)
+		return ARM_PSCI_RET_INVAL;
+
+	/* Wait to be turned off. */
+	for (;;) wfi();
+}
+
+/*
+ * R40 is different from other single cluster SoCs. The secondary core
+ * entry address register is in the SRAM controller address range.
+ */
+#define SUN8I_R40_SRAMC_SOFT_ENTRY_REG0		(0xbc)
+
+#ifdef CONFIG_MACH_SUN8I_R40
+/* secondary core entry address is programmed differently on R40 */
+static void __secure sunxi_set_entry_address(void *entry)
+{
+	writel((u32)entry,
+	       SUNXI_SRAMC_BASE + SUN8I_R40_SRAMC_SOFT_ENTRY_REG0);
+}
+#else
+static void __secure sunxi_set_entry_address(void *entry)
+{
+	struct sunxi_cpucfg_reg *cpucfg =
+		(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
+
+	writel((u32)entry, &cpucfg->priv0);
+
+#ifdef CONFIG_MACH_SUN8I_H3
+	/* Redirect CPU 0 to the secure monitor via the resume shim. */
+	writel(0x16aaefe8, &cpucfg->super_standy_flag);
+	writel(0xaa16efe8, &cpucfg->super_standy_flag);
+	writel(SUNXI_RESUME_BASE, &cpucfg->priv1);
+#endif
+}
+#endif
+
+void __secure psci_arch_init(void)
+{
+	static bool __secure_data one_time_init = true;
+
+	if (one_time_init) {
+		/* Set secondary core power-on PC. */
+		sunxi_set_entry_address(psci_cpu_entry);
+
+		/* Wait for the SCP firmware to boot. */
+		scpi_begin_command();
+		scpi_wait_response();
+		scpi_end_command();
+
+		one_time_init = false;
+	}
+
+	/*
+	 * Copied from arch/arm/cpu/armv7/virt-v7.c
+	 * See also gic_resume() in arch/arm/mach-imx/mx7/psci-mx7.c
+	 */
+	if (gic_dist_init) {
+		u32 i, itlinesnr;
+
+		/* enable the GIC distributor */
+		writel(readl(GICD_BASE + GICD_CTLR) | 0x03, GICD_BASE + GICD_CTLR);
+
+		/* TYPER[4:0] contains an encoded number of available interrupts */
+		itlinesnr = readl(GICD_BASE + GICD_TYPER) & 0x1f;
+
+		/* set all bits in the GIC group registers to one to allow access
+		 * from non-secure state. The first 32 interrupts are private per
+		 * CPU and will be set later when enabling the GIC for each core
+		 */
+		for (i = 1; i <= itlinesnr; i++)
+			writel((unsigned)-1, GICD_BASE + GICD_IGROUPRn + 4 * i);
+
+		gic_dist_init = false;
+	}
+
+	/* Be cool with non-secure. */
+	writel(0xff, GICC_BASE + GICC_PMR);
+}

arch/arm/cpu/armv7/sunxi/psci.c

@@ -10,6 +10,7 @@
 #include <common.h>
 #include <asm/cache.h>
 
+#include <asm/arch/clock.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/cpucfg.h>
 #include <asm/arch/prcm.h>
@@ -38,6 +39,15 @@
 #define SUN8I_R40_PWR_CLAMP(cpu)		(0x120 + (cpu) * 0x4)
 #define SUN8I_R40_SRAMC_SOFT_ENTRY_REG0		(0xbc)
 
+static inline u32 __secure cp15_read_mpidr(void)
+{
+	u32 val;
+
+	asm volatile ("mrc p15, 0, %0, c0, c0, 5" : "=r" (val));
+
+	return val;
+}
+
 static void __secure cp15_write_cntp_tval(u32 tval)
 {
 	asm volatile ("mcr p15, 0, %0, c14, c2, 0" : : "r" (tval));
@@ -132,6 +142,13 @@ static void __secure sunxi_set_entry_address(void *entry)
 		(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
 
 	writel((u32)entry, &cpucfg->priv0);
+
+#ifdef CONFIG_MACH_SUN8I_H3
+	/* Redirect CPU 0 to the secure monitor via the resume shim. */
+	writel(0x16aaefe8, &cpucfg->super_standy_flag);
+	writel(0xaa16efe8, &cpucfg->super_standy_flag);
+	writel(SUNXI_RESUME_BASE, &cpucfg->priv1);
+#endif
 }
 #endif
 
@@ -246,9 +263,12 @@ out:
 int __secure psci_cpu_on(u32 __always_unused unused, u32 mpidr, u32 pc,
 			 u32 context_id)
 {
+	struct sunxi_ccm_reg *ccu = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 	struct sunxi_cpucfg_reg *cpucfg =
 		(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
 	u32 cpu = (mpidr & 0x3);
+	u32 cpu_clk;
+	u32 bus_clk;
 
 	/* store target PC and context id */
 	psci_save(cpu, pc, context_id);
@@ -265,12 +285,32 @@ int __secure psci_cpu_on(u32 __always_unused unused, u32 mpidr, u32 pc,
 	/* Lock CPU (Disable external debug access) */
 	clrbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
 
+	if (IS_ENABLED(CONFIG_MACH_SUN8I_H3) && cpu == 0) {
+		/* Save registers that will be clobbered by the BROM. */
+		cpu_clk = readl(&ccu->cpu_axi_cfg);
+		bus_clk = readl(&ccu->ahb1_apb1_div);
+
+		/* Bypass PLL_PERIPH0 so AHB1 frequency does not spike. */
+		setbits_le32(&ccu->pll6_cfg, BIT(25));
+	}
+
 	/* Power up target CPU */
 	sunxi_cpu_set_power(cpu, true);
 
 	/* De-assert reset on target CPU */
 	writel(BIT(1) | BIT(0), &cpucfg->cpu[cpu].rst);
 
+	if (IS_ENABLED(CONFIG_MACH_SUN8I_H3) && cpu == 0) {
+		/* Spin until the BROM has clobbered the clock registers. */
+		while (readl(&ccu->ahb1_apb1_div) != 0x00001100);
+
+		/* Restore the registers and turn off PLL_PERIPH0 bypass. */
+		writel(cpu_clk, &ccu->cpu_axi_cfg);
+		writel(bus_clk, &ccu->ahb1_apb1_div);
+
+		clrbits_le32(&ccu->pll6_cfg, BIT(25));
+	}
+
 	/* Unlock CPU (Disable external debug access) */
 	setbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
 
@@ -281,9 +321,14 @@ s32 __secure psci_cpu_off(void)
 {
 	psci_cpu_off_common();
 
-	/* Ask CPU0 via SGI15 to pull the rug... */
-	writel(BIT(16) | 15, GICD_BASE + GICD_SGIR);
-	dsb();
+	if (cp15_read_mpidr() & 3) {
+		/* Ask CPU0 via SGI15 to pull the rug... */
+		writel(BIT(16) | 15, GICD_BASE + GICD_SGIR);
+		dsb();
+	} else {
+		/* Unmask FIQs to service SGI15. */
+		asm volatile ("cpsie f");
+	}
 
 	/* Wait to be turned off */
 	while (1)

arch/arm/cpu/armv8/fwcall.c

@@ -103,7 +103,7 @@ void __noreturn psci_system_reset2(u32 reset_level, u32 cookie)
 {
 	struct pt_regs regs;
 
-	regs.regs[0] = ARM_PSCI_0_2_FN64_SYSTEM_RESET2;
+	regs.regs[0] = ARM_PSCI_1_1_FN64_SYSTEM_RESET2;
 	regs.regs[1] = PSCI_RESET2_TYPE_VENDOR | reset_level;
 	regs.regs[2] = cookie;
 	if (use_smc_for_psci)

arch/arm/dts/Makefile

@@ -641,6 +641,7 @@ dtb-$(CONFIG_MACH_SUN8I_A33) += \
 	sun8i-a33-et-q8-v1.6.dtb \
 	sun8i-a33-ga10h-v1.1.dtb \
 	sun8i-a33-inet-d978-rev2.dtb \
+	sun8i-a33-inet-u70b-rev1.dtb \
 	sun8i-a33-ippo-q8h-v1.2.dtb \
 	sun8i-a33-olinuxino.dtb \
 	sun8i-a33-q8-tablet.dtb \

arch/arm/dts/axp22x.dtsi

@@ -67,6 +67,12 @@
 		status = "disabled";
 	};
 
+	axp_gpio: gpio {
+		compatible = "x-powers,axp221-gpio";
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
 	regulators {
 		/* Default work frequency for buck regulators */
 		x-powers,dcdc-freq = <3000>;

arch/arm/dts/axp809.dtsi

@@ -50,4 +50,11 @@
 	compatible = "x-powers,axp809";
 	interrupt-controller;
 	#interrupt-cells = <1>;
+
+	axp_gpio: gpio {
+		compatible = "x-powers,axp809-gpio",
+			     "x-powers,axp221-gpio";
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
 };

arch/arm/dts/sun50i-h6-pine-h64.dts

@@ -89,6 +89,10 @@
 	status = "okay";
 };
 
+&dwc3 {
+	status = "okay";
+};
+
 &ehci0 {
 	status = "okay";
 };
@@ -332,3 +336,7 @@
 	usb3_vbus-supply = <&reg_usb_vbus>;
 	status = "okay";
 };
+
+&usb3phy {
+	status = "okay";
+};

arch/arm/dts/sun5i-a13-ampe-a76.dts

@@ -8,6 +8,8 @@
 /dts-v1/;
 #include "sun5i-a13.dtsi"
 
+#include <dt-bindings/gpio/gpio.h>
+
 / {
 	model = "Ampe A76";
 	compatible = "ampe,a76", "allwinner,sun5i-a13";
@@ -26,3 +28,7 @@
 	pinctrl-0 = <&uart1_pg_pins>;
 	status = "okay";
 };
+
+&usbphy {
+	usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
+};

arch/arm/dts/sun6i-a31-mixtile-loftq.dts

@@ -6,6 +6,9 @@
  */
 
 /dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+
 #include "sun6i-a31.dtsi"
 
 / {
@@ -19,6 +22,15 @@
 	chosen {
 		stdout-path = "serial0:115200n8";
 	};
+
+	reg_usb1_vbus: usb1-vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "usb1-vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		gpio = <&pio 7 24 GPIO_ACTIVE_HIGH>; /* PH24 */
+	};
 };
 
 &ehci0 {
@@ -56,3 +68,8 @@
 	pinctrl-0 = <&uart0_ph_pins>;
 	status = "okay";
 };
+
+&usbphy {
+	usb1_vbus-supply = <&reg_usb1_vbus>;
+	status = "okay";
+};

arch/arm/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts

@@ -176,6 +176,7 @@
 };
 
 &usbphy {
+	usb0_id_det-gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */
 	usb1_vbus-supply = <&reg_dldo1>;
 	usb2_vbus-supply = <&reg_dc1sw>;
 	status = "okay";

arch/arm/dts/sun8i-a23-a33.dtsi

@@ -138,6 +138,14 @@
 			#size-cells = <1>;
 			ranges;
 
+			sram_a2: sram@40000 {
+				compatible = "mmio-sram";
+				reg = <0x00040000 0x14000>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0 0x00040000 0x14000>;
+			};
+
 			sram_c: sram@1d00000 {
 				compatible = "mmio-sram";
 				reg = <0x01d00000 0x80000>;
@@ -847,5 +855,11 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 		};
+
+		remoteproc@1f01c00 {
+			compatible = "allwinner,sun6i-a31-ar100";
+			reg = <0x01f01c00 0x400>;
+			sram = <&sram_a2>;
+		};
 	};
 };

arch/arm/dts/sun8i-a33-inet-u70b-rev1.dts

@@ -0,0 +1,183 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+
+/dts-v1/;
+
+#include "sun8i-a33.dtsi"
+#include "sun8i-reference-design-tablet.dtsi"
+
+/ {
+	model = "iNet U70B REV01";
+	compatible = "inet-tek,inet-u70b-rev01", "allwinner,sun8i-a33";
+
+	aliases {
+		ethernet0 = &rtl8723cs;
+		serial0 = &uart0;
+	};
+
+	panel: panel {
+		compatible = "panel-dpi";
+		backlight = <&backlight>;
+		enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
+		power-supply = <&reg_dc1sw>;
+
+		panel-timing {
+			clock-frequency = <51000000>;
+			hactive = <1024>;
+			vactive = <600>;
+			hfront-porch = <162>;
+			hback-porch = <158>;
+			hsync-len = <20>;
+			vback-porch = <25>;
+			vfront-porch = <10>;
+			vsync-len = <3>;
+			hsync-active = <1>;
+			vsync-active = <1>;
+		};
+
+		port {
+			panel_in_tcon0: endpoint {
+				remote-endpoint = <&tcon0_out_panel>;
+			};
+		};
+	};
+
+	speaker_amp: audio-amplifier {
+		compatible = "simple-audio-amplifier";
+		enable-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */
+		sound-name-prefix = "Speaker Amp";
+	};
+
+	wifi_pwrseq: wifi-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL6 */
+		post-power-on-delay-ms = <200>;
+	};
+};
+
+&codec {
+	status = "okay";
+};
+
+&dai {
+	status = "okay";
+};
+
+&de {
+	status = "okay";
+};
+
+&i2c1 {
+	clock-frequency = <400000>;
+
+	accelerometer@18 {
+		compatible = "bosch,bma250";
+		reg = <0x18>;
+		interrupt-parent = <&pio>;
+		interrupts = <7 10 IRQ_TYPE_EDGE_RISING>; /* PH10 / EINT10 */
+	};
+};
+
+&mmc0 {
+	status = "disabled";
+};
+
+&mmc1 {
+	pinctrl-0 = <&mmc1_pg_pins>;
+	pinctrl-names = "default";
+	bus-width = <4>;
+	non-removable;
+	vmmc-supply = <&reg_dldo1>;
+	vqmmc-supply = <&reg_dldo2>;
+	status = "okay";
+
+	rtl8723cs: wifi@1 {
+		reg = <1>;
+		interrupt-parent = <&r_pio>;
+		interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */
+	};
+};
+
+&nfc {
+	status = "okay";
+
+	nand@0 {
+		reg = <0>;
+		allwinner,rb = <0>;
+		nand-ecc-maximize;
+	};
+};
+
+&r_uart {
+	status = "disabled";
+};
+
+&reg_dldo2 {
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-wifi-io";
+};
+
+&simplefb_lcd {
+	status = "okay";
+};
+
+&sound {
+	simple-audio-card,aux-devs = <&codec_analog>, <&speaker_amp>;
+	simple-audio-card,widgets = "Headphone", "Headphone Jack",
+				    "Microphone", "Internal Microphone",
+				    "Speaker", "Internal Speaker";
+	simple-audio-card,routing = "Headphone Jack", "HP",
+				    "Internal Speaker", "Speaker Amp OUTL",
+				    "Internal Speaker", "Speaker Amp OUTR",
+				    "Speaker Amp INL", "HP", /* PHONEOUT ??? */
+				    "Speaker Amp INR", "HP", /* PHONEOUT ??? */
+				    "Left DAC", "DACL",
+				    "Right DAC", "DACR",
+				    "ADCL", "Left ADC",
+				    "ADCR", "Right ADC",
+				    "MIC1", "Internal Microphone",
+				    "MIC2", "Headset Microphone",
+				    "Headset Microphone", "HBIAS",
+				    "Internal Microphone", "MBIAS";
+	status = "okay";
+};
+
+&tcon0 {
+	pinctrl-0 = <&lcd_rgb666_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&tcon0_out {
+	tcon0_out_panel: endpoint {
+		remote-endpoint = <&panel_in_tcon0>;
+	};
+};
+
+&touchscreen {
+	reg = <0x40>;
+	compatible = "silead,gsl1680";
+	avdd-supply = <&reg_ldo_io1>;
+	touchscreen-size-x = <1024>;
+	touchscreen-size-y = <600>;
+	status = "okay";
+};
+
+&uart0 {
+	pinctrl-0 = <&uart0_pf_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-0 = <&uart1_pg_pins>, <&uart1_cts_rts_pg_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	bluetooth {
+		compatible = "realtek,rtl8723cs-bt";
+		device-wake-gpios = <&r_pio 0 10 GPIO_ACTIVE_LOW>; /* PL10 */
+		enable-gpios = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
+		host-wake-gpios = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */
+	};
+};

arch/arm/dts/sun8i-a33-sinlinx-sina33.dts

@@ -271,5 +271,6 @@
 
 &usbphy {
 	status = "okay";
+	usb0_id_det-gpios = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* PH8 */
 	usb1_vbus-supply = <&reg_vcc5v0>; /* USB1 VBUS is always on */
 };

arch/arm/dts/sun8i-h3.dtsi

@@ -170,6 +170,14 @@
 			#size-cells = <1>;
 			ranges;
 
+			sram_a2: sram@40000 {
+				compatible = "mmio-sram";
+				reg = <0x00040000 0xc000>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0 0x00040000 0xc000>;
+			};
+
 			sram_c: sram@1d00000 {
 				compatible = "mmio-sram";
 				reg = <0x01d00000 0x80000>;
@@ -239,6 +247,12 @@
 			nvmem-cell-names = "calibration";
 			#thermal-sensor-cells = <0>;
 		};
+
+		remoteproc@1f01c00 {
+			compatible = "allwinner,sun6i-a31-ar100";
+			reg = <0x01f01c00 0x400>;
+			sram = <&sram_a2>;
+		};
 	};
 
 	thermal-zones {

arch/arm/dts/sunxi-u-boot.dtsi

@@ -1,13 +1,24 @@
 #include <config.h>
 
-#ifdef CONFIG_MACH_SUN50I_H6
-#define BL31_ADDR 0x104000
-#define  SCP_ADDR 0x114000
-#elif defined(CONFIG_MACH_SUN50I_H616)
-#define BL31_ADDR 0x40000000
+#ifdef CONFIG_ARM64
+#define ARCH "arm64"
 #else
-#define BL31_ADDR  0x44000
-#define  SCP_ADDR  0x50000
+#define ARCH "arm"
+#endif
+
+#if defined(CONFIG_ARMV7_PSCI) && (defined(CONFIG_MACH_SUN8I_A33) || defined(CONFIG_MACH_SUN8I_H3))
+#if defined(CONFIG_MACH_SUN8I_H3)
+#define RESUME_ADDR	SUNXI_RESUME_BASE
+#endif
+#define SCP_ADDR	SUNXI_SCP_BASE
+#elif defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN50I_H5)
+#define BL31_ADDR	0x00044000
+#define SCP_ADDR	0x00050000
+#elif defined(CONFIG_MACH_SUN50I_H6)
+#define BL31_ADDR	0x00104000
+#define SCP_ADDR	0x00114000
+#elif defined(CONFIG_MACH_SUN50I_H616)
+#define BL31_ADDR	0x40000000
 #endif
 
 / {
@@ -34,30 +45,33 @@
 			filename = "spl/sunxi-spl.bin";
 		};
 
-#ifdef CONFIG_ARM64
+#ifdef CONFIG_SPL_LOAD_FIT
 		fit {
-			description = "Configuration to load ATF before U-Boot";
+			description = "Configuration to load U-Boot and firmware";
+			offset = <32768>;
 			#address-cells = <1>;
 			fit,fdt-list = "of-list";
 
 			images {
 				uboot {
-					description = "U-Boot (64-bit)";
+					description = "U-Boot";
 					type = "standalone";
 					os = "u-boot";
-					arch = "arm64";
+					arch = ARCH;
 					compression = "none";
 					load = <CONFIG_TEXT_BASE>;
+					entry = <CONFIG_TEXT_BASE>;
 
 					u-boot-nodtb {
 					};
 				};
 
+#ifdef BL31_ADDR
 				atf {
 					description = "ARM Trusted Firmware";
 					type = "firmware";
 					os = "arm-trusted-firmware";
-					arch = "arm64";
+					arch = ARCH;
 					compression = "none";
 					load = <BL31_ADDR>;
 					entry = <BL31_ADDR>;
@@ -67,6 +81,21 @@
 						missing-msg = "atf-bl31-sunxi";
 					};
 				};
+#endif
+
+#ifdef RESUME_ADDR
+				resume {
+					description = "Super Standby resume image";
+					type = "standalone";
+					arch = ARCH;
+					compression = "none";
+					load = <RESUME_ADDR>;
+
+					blob-ext {
+						filename = "u-boot-resume.img";
+					};
+				};
+#endif
 
 #ifdef SCP_ADDR
 				scp {
@@ -95,19 +124,26 @@
 
 				@config-SEQ {
 					description = "NAME";
+#ifdef BL31_ADDR
 					firmware = "atf";
-#ifndef SCP_ADDR
-					loadables = "uboot";
 #else
-					loadables = "scp", "uboot";
+					firmware = "uboot";
 #endif
+					loadables =
+#ifdef RESUME_ADDR
+						    "resume",
+#endif
+#ifdef SCP_ADDR
+						    "scp",
+#endif
+						    "uboot";
 					fdt = "fdt-SEQ";
 				};
 			};
 		};
 #else
 		u-boot-img {
-			offset = <CONFIG_SPL_PAD_TO>;
+			offset = <32768>;
 		};
 #endif
 	};

arch/arm/include/asm/arch-sunxi/gpio.h

@@ -111,7 +111,6 @@ enum sunxi_gpio_number {
 	SUNXI_GPIO_L_START = 352,
 	SUNXI_GPIO_M_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_L),
 	SUNXI_GPIO_N_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_M),
-	SUNXI_GPIO_AXP0_START = 1024,
 };
 
 /* SUNXI GPIO number definitions */
@@ -128,8 +127,6 @@ enum sunxi_gpio_number {
 #define SUNXI_GPM(_nr)	(SUNXI_GPIO_M_START + (_nr))
 #define SUNXI_GPN(_nr)	(SUNXI_GPIO_N_START + (_nr))
 
-#define SUNXI_GPAXP0(_nr)	(SUNXI_GPIO_AXP0_START + (_nr))
-
 /* GPIO pin function config */
 #define SUNXI_GPIO_INPUT	0
 #define SUNXI_GPIO_OUTPUT	1
@@ -207,12 +204,6 @@ enum sunxi_gpio_number {
 #define SUNXI_GPIO_PULL_UP	1
 #define SUNXI_GPIO_PULL_DOWN	2
 
-/* Virtual AXP0 GPIOs */
-#define SUNXI_GPIO_AXP0_PREFIX "AXP0-"
-#define SUNXI_GPIO_AXP0_VBUS_DETECT	4
-#define SUNXI_GPIO_AXP0_VBUS_ENABLE	5
-#define SUNXI_GPIO_AXP0_GPIO_COUNT	6
-
 struct sunxi_gpio_plat {
 	struct sunxi_gpio	*regs;
 	char			bank_name[3];
@@ -228,10 +219,4 @@ void sunxi_gpio_set_pull(u32 pin, u32 val);
 void sunxi_gpio_set_pull_bank(struct sunxi_gpio *pio, int bank_offset, u32 val);
 int sunxi_name_to_gpio(const char *name);
 
-#if !defined CONFIG_SPL_BUILD && defined CONFIG_AXP_GPIO
-int axp_gpio_init(void);
-#else
-static inline int axp_gpio_init(void) { return 0; }
-#endif
-
 #endif /* _SUNXI_GPIO_H */

arch/arm/include/asm/arch-sunxi/mmc.h

@@ -1,139 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2007-2011
- * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
- * Aaron <leafy.myeh@allwinnertech.com>
- *
- * MMC register definition for allwinner sunxi platform.
- */
 
-#ifndef _SUNXI_MMC_H
-#define _SUNXI_MMC_H
-
-#include <linux/types.h>
-
-struct sunxi_mmc {
-	u32 gctrl;		/* 0x00 global control */
-	u32 clkcr;		/* 0x04 clock control */
-	u32 timeout;		/* 0x08 time out */
-	u32 width;		/* 0x0c bus width */
-	u32 blksz;		/* 0x10 block size */
-	u32 bytecnt;		/* 0x14 byte count */
-	u32 cmd;		/* 0x18 command */
-	u32 arg;		/* 0x1c argument */
-	u32 resp0;		/* 0x20 response 0 */
-	u32 resp1;		/* 0x24 response 1 */
-	u32 resp2;		/* 0x28 response 2 */
-	u32 resp3;		/* 0x2c response 3 */
-	u32 imask;		/* 0x30 interrupt mask */
-	u32 mint;		/* 0x34 masked interrupt status */
-	u32 rint;		/* 0x38 raw interrupt status */
-	u32 status;		/* 0x3c status */
-	u32 ftrglevel;		/* 0x40 FIFO threshold watermark*/
-	u32 funcsel;		/* 0x44 function select */
-	u32 cbcr;		/* 0x48 CIU byte count */
-	u32 bbcr;		/* 0x4c BIU byte count */
-	u32 dbgc;		/* 0x50 debug enable */
-	u32 res0;		/* 0x54 reserved */
-	u32 a12a;		/* 0x58 Auto command 12 argument */
-	u32 ntsr;		/* 0x5c	New timing set register */
-	u32 res1[8];
-	u32 dmac;		/* 0x80 internal DMA control */
-	u32 dlba;		/* 0x84 internal DMA descr list base address */
-	u32 idst;		/* 0x88 internal DMA status */
-	u32 idie;		/* 0x8c internal DMA interrupt enable */
-	u32 chda;		/* 0x90 */
-	u32 cbda;		/* 0x94 */
-	u32 res2[26];
-#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6)
-	u32 res3[17];
-	u32 samp_dl;
-	u32 res4[46];
-#endif
-	u32 fifo;		/* 0x100 / 0x200 FIFO access address */
-};
-
-#define SUNXI_MMC_CLK_POWERSAVE		(0x1 << 17)
-#define SUNXI_MMC_CLK_ENABLE		(0x1 << 16)
-#define SUNXI_MMC_CLK_DIVIDER_MASK	(0xff)
-
-#define SUNXI_MMC_GCTRL_SOFT_RESET	(0x1 << 0)
-#define SUNXI_MMC_GCTRL_FIFO_RESET	(0x1 << 1)
-#define SUNXI_MMC_GCTRL_DMA_RESET	(0x1 << 2)
-#define SUNXI_MMC_GCTRL_RESET		(SUNXI_MMC_GCTRL_SOFT_RESET|\
-					 SUNXI_MMC_GCTRL_FIFO_RESET|\
-					 SUNXI_MMC_GCTRL_DMA_RESET)
-#define SUNXI_MMC_GCTRL_DMA_ENABLE	(0x1 << 5)
-#define SUNXI_MMC_GCTRL_ACCESS_BY_AHB   (0x1 << 31)
-
-#define SUNXI_MMC_CMD_RESP_EXPIRE	(0x1 << 6)
-#define SUNXI_MMC_CMD_LONG_RESPONSE	(0x1 << 7)
-#define SUNXI_MMC_CMD_CHK_RESPONSE_CRC	(0x1 << 8)
-#define SUNXI_MMC_CMD_DATA_EXPIRE	(0x1 << 9)
-#define SUNXI_MMC_CMD_WRITE		(0x1 << 10)
-#define SUNXI_MMC_CMD_AUTO_STOP		(0x1 << 12)
-#define SUNXI_MMC_CMD_WAIT_PRE_OVER	(0x1 << 13)
-#define SUNXI_MMC_CMD_SEND_INIT_SEQ	(0x1 << 15)
-#define SUNXI_MMC_CMD_UPCLK_ONLY	(0x1 << 21)
-#define SUNXI_MMC_CMD_START		(0x1 << 31)
-
-#define SUNXI_MMC_RINT_RESP_ERROR		(0x1 << 1)
-#define SUNXI_MMC_RINT_COMMAND_DONE		(0x1 << 2)
-#define SUNXI_MMC_RINT_DATA_OVER		(0x1 << 3)
-#define SUNXI_MMC_RINT_TX_DATA_REQUEST		(0x1 << 4)
-#define SUNXI_MMC_RINT_RX_DATA_REQUEST		(0x1 << 5)
-#define SUNXI_MMC_RINT_RESP_CRC_ERROR		(0x1 << 6)
-#define SUNXI_MMC_RINT_DATA_CRC_ERROR		(0x1 << 7)
-#define SUNXI_MMC_RINT_RESP_TIMEOUT		(0x1 << 8)
-#define SUNXI_MMC_RINT_DATA_TIMEOUT		(0x1 << 9)
-#define SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE	(0x1 << 10)
-#define SUNXI_MMC_RINT_FIFO_RUN_ERROR		(0x1 << 11)
-#define SUNXI_MMC_RINT_HARD_WARE_LOCKED		(0x1 << 12)
-#define SUNXI_MMC_RINT_START_BIT_ERROR		(0x1 << 13)
-#define SUNXI_MMC_RINT_AUTO_COMMAND_DONE	(0x1 << 14)
-#define SUNXI_MMC_RINT_END_BIT_ERROR		(0x1 << 15)
-#define SUNXI_MMC_RINT_SDIO_INTERRUPT		(0x1 << 16)
-#define SUNXI_MMC_RINT_CARD_INSERT		(0x1 << 30)
-#define SUNXI_MMC_RINT_CARD_REMOVE		(0x1 << 31)
-#define SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT      \
-	(SUNXI_MMC_RINT_RESP_ERROR |		\
-	 SUNXI_MMC_RINT_RESP_CRC_ERROR |	\
-	 SUNXI_MMC_RINT_DATA_CRC_ERROR |	\
-	 SUNXI_MMC_RINT_RESP_TIMEOUT |		\
-	 SUNXI_MMC_RINT_DATA_TIMEOUT |		\
-	 SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE |	\
-	 SUNXI_MMC_RINT_FIFO_RUN_ERROR |	\
-	 SUNXI_MMC_RINT_HARD_WARE_LOCKED |	\
-	 SUNXI_MMC_RINT_START_BIT_ERROR |	\
-	 SUNXI_MMC_RINT_END_BIT_ERROR) /* 0xbfc2 */
-#define SUNXI_MMC_RINT_INTERRUPT_DONE_BIT	\
-	(SUNXI_MMC_RINT_AUTO_COMMAND_DONE |	\
-	 SUNXI_MMC_RINT_DATA_OVER |		\
-	 SUNXI_MMC_RINT_COMMAND_DONE |		\
-	 SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE)
-
-#define SUNXI_MMC_STATUS_RXWL_FLAG		(0x1 << 0)
-#define SUNXI_MMC_STATUS_TXWL_FLAG		(0x1 << 1)
-#define SUNXI_MMC_STATUS_FIFO_EMPTY		(0x1 << 2)
-#define SUNXI_MMC_STATUS_FIFO_FULL		(0x1 << 3)
-#define SUNXI_MMC_STATUS_CARD_PRESENT		(0x1 << 8)
-#define SUNXI_MMC_STATUS_CARD_DATA_BUSY		(0x1 << 9)
-#define SUNXI_MMC_STATUS_DATA_FSM_BUSY		(0x1 << 10)
-#define SUNXI_MMC_STATUS_FIFO_LEVEL(reg)	(((reg) >> 17) & 0x3fff)
-
-#define SUNXI_MMC_NTSR_MODE_SEL_NEW		(0x1 << 31)
-
-#define SUNXI_MMC_IDMAC_RESET		(0x1 << 0)
-#define SUNXI_MMC_IDMAC_FIXBURST	(0x1 << 1)
-#define SUNXI_MMC_IDMAC_ENABLE		(0x1 << 7)
-
-#define SUNXI_MMC_IDIE_TXIRQ		(0x1 << 0)
-#define SUNXI_MMC_IDIE_RXIRQ		(0x1 << 1)
-
-#define SUNXI_MMC_COMMON_CLK_GATE		(1 << 16)
-#define SUNXI_MMC_COMMON_RESET			(1 << 18)
-
-#define SUNXI_MMC_CAL_DL_SW_EN		(0x1 << 7)
+#ifndef _ASM_ARCH_MMC_H_
+#define _ASM_ARCH_MMC_H_
 
 struct mmc *sunxi_mmc_init(int sdc_no);
-#endif /* _SUNXI_MMC_H */
+
+#endif /* _ASM_ARCH_MMC_H_ */

arch/arm/include/asm/psci.h

@@ -22,8 +22,9 @@
 #include <linux/bitops.h>
 #endif
 
-#define ARM_PSCI_VER_1_0		(0x00010000)
 #define ARM_PSCI_VER_0_2		(0x00000002)
+#define ARM_PSCI_VER_1_0		(0x00010000)
+#define ARM_PSCI_VER_1_1		(0x00010001)
 
 /* PSCI 0.1 interface */
 #define ARM_PSCI_FN_BASE		0x95c1ba5e
@@ -68,7 +69,6 @@
 #define ARM_PSCI_0_2_FN64_AFFINITY_INFO		ARM_PSCI_0_2_FN64(4)
 #define ARM_PSCI_0_2_FN64_MIGRATE		ARM_PSCI_0_2_FN64(5)
 #define ARM_PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU	ARM_PSCI_0_2_FN64(7)
-#define ARM_PSCI_0_2_FN64_SYSTEM_RESET2		ARM_PSCI_0_2_FN64(18)
 
 /* PSCI 1.0 interface */
 #define ARM_PSCI_1_0_FN_PSCI_FEATURES		ARM_PSCI_0_2_FN(10)
@@ -86,6 +86,11 @@
 #define ARM_PSCI_1_0_FN64_STAT_RESIDENCY	ARM_PSCI_0_2_FN64(16)
 #define ARM_PSCI_1_0_FN64_STAT_COUNT		ARM_PSCI_0_2_FN64(17)
 
+/* PSCI 1.1 interface */
+#define ARM_PSCI_1_1_FN_SYSTEM_RESET2		ARM_PSCI_0_2_FN(18)
+
+#define ARM_PSCI_1_1_FN64_SYSTEM_RESET2		ARM_PSCI_0_2_FN64(18)
+
 /* 1KB stack per core */
 #define ARM_PSCI_STACK_SHIFT	10
 #define ARM_PSCI_STACK_SIZE	(1 << ARM_PSCI_STACK_SHIFT)

arch/arm/include/asm/system.h

@@ -557,16 +557,20 @@ void mmu_page_table_flush(unsigned long start, unsigned long stop);
 #ifdef CONFIG_ARMV7_PSCI
 void psci_arch_cpu_entry(void);
 void psci_arch_init(void);
+
 u32 psci_version(void);
-s32 psci_features(u32 function_id, u32 psci_fid);
+s32 psci_cpu_suspend(u32 function_id, u32 power_state, u32 pc, u32 context_id);
 s32 psci_cpu_off(void);
-s32 psci_cpu_on(u32 function_id, u32 target_cpu, u32 pc,
-		u32 context_id);
-s32 psci_affinity_info(u32 function_id, u32 target_affinity,
-		       u32  lowest_affinity_level);
+s32 psci_cpu_on(u32 function_id, u32 target_cpu, u32 pc, u32 context_id);
+s32 psci_affinity_info(u32 function_id, u32 target_affinity, u32 power_level);
 u32 psci_migrate_info_type(void);
 void psci_system_off(void);
 void psci_system_reset(void);
+s32 psci_features(u32 function_id, u32 psci_fid);
+s32 psci_cpu_default_suspend(u32 function_id, u32 pc, u32 context_id);
+s32 psci_node_hw_state(u32 function_id, u32 target_cpu, u32 power_level);
+s32 psci_system_suspend(u32 function_id, u32 pc, u32 context_id);
+s32 psci_system_reset2(u32 function_id, u32 reset_type, u32 cookie);
 #endif
 
 #endif /* __ASSEMBLY__ */

arch/arm/lib/psci-dt.c

@@ -66,6 +66,8 @@ int fdt_psci(void *fdt)
 init_psci_node:
 #if CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT)
 	psci_ver = sec_firmware_support_psci_version();
+#elif defined(CONFIG_ARMV7_PSCI_1_1)
+	psci_ver = ARM_PSCI_VER_1_1;
 #elif defined(CONFIG_ARMV7_PSCI_1_0) || defined(CONFIG_ARMV8_PSCI)
 	psci_ver = ARM_PSCI_VER_1_0;
 #elif defined(CONFIG_ARMV7_PSCI_0_2)

arch/arm/mach-sunxi/Kconfig

@@ -1,8 +1,5 @@
 if ARCH_SUNXI
 
-config IDENT_STRING
-	default " Allwinner Technology"
-
 config DRAM_SUN4I
 	bool
 	help
@@ -99,17 +96,6 @@ config AXP_PMIC_BUS
 	  Select this PMIC bus access helpers for Sunxi platform PRCM or other
 	  AXP family PMIC devices.
 
-config SUNXI_SRAM_ADDRESS
-	hex
-	default 0x10000 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5
-	default 0x20000 if SUN50I_GEN_H6
-	default 0x0
-	---help---
-	Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
-	with the first SRAM region being located at address 0.
-	Some newer SoCs map the boot ROM at address 0 instead and move the
-	SRAM to a different address.
-
 config SUNXI_A64_TIMER_ERRATUM
 	bool
 
@@ -133,7 +119,6 @@ config SUN50I_GEN_H6
 	select FIT
 	select SPL_LOAD_FIT
 	select MMC_SUNXI_HAS_NEW_MODE
-	select SUPPORT_SPL
 	---help---
 	Select this for sunxi SoCs which have H6 like peripherals, clocks
 	and memory map.
@@ -162,12 +147,10 @@ endif
 
 config MACH_SUNXI_H3_H5
 	bool
-	select PHY_SUN4I_USB
 	select SUNXI_DE2
 	select SUNXI_DRAM_DW
 	select SUNXI_DRAM_DW_32BIT
 	select SUNXI_GEN_SUN6I
-	select SUPPORT_SPL
 
 # TODO: try out A80's 8GiB DRAM space
 config SUNXI_DRAM_MAX_SIZE
@@ -184,17 +167,14 @@ config MACH_SUNIV
 	bool "suniv (Allwinner F1C100s/F1C200s/F1C600/R6)"
 	select CPU_ARM926EJS
 	select SUNXI_GEN_SUN6I
-	select SUPPORT_SPL
 	select SKIP_LOWLEVEL_INIT_ONLY
 	select SPL_SKIP_LOWLEVEL_INIT_ONLY
 
 config MACH_SUN4I
 	bool "sun4i (Allwinner A10)"
 	select CPU_V7A
-	select PHY_SUN4I_USB
 	select DRAM_SUN4I
 	select SUNXI_GEN_SUN4I
-	select SUPPORT_SPL
 	imply SPL_SYS_I2C_LEGACY
 	imply SYS_I2C_LEGACY
 
@@ -202,9 +182,7 @@ config MACH_SUN5I
 	bool "sun5i (Allwinner A13)"
 	select CPU_V7A
 	select DRAM_SUN4I
-	select PHY_SUN4I_USB
 	select SUNXI_GEN_SUN4I
-	select SUPPORT_SPL
 	imply SPL_SYS_I2C_LEGACY
 	imply SYS_I2C_LEGACY
 
@@ -216,11 +194,9 @@ config MACH_SUN6I
 	select ARCH_SUPPORT_PSCI
 	select SPL_ARMV7_SET_CORTEX_SMPEN
 	select DRAM_SUN6I
-	select PHY_SUN4I_USB
 	select SPL_I2C
 	select SUN6I_PRCM
 	select SUNXI_GEN_SUN6I
-	select SUPPORT_SPL
 	select SYS_I2C_SUN6I_P2WI
 	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
 
@@ -232,9 +208,7 @@ config MACH_SUN7I
 	select ARCH_SUPPORT_PSCI
 	select SPL_ARMV7_SET_CORTEX_SMPEN
 	select DRAM_SUN4I
-	select PHY_SUN4I_USB
 	select SUNXI_GEN_SUN4I
-	select SUPPORT_SPL
 	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
 	imply SPL_SYS_I2C_LEGACY
 	imply SYS_I2C_LEGACY
@@ -246,10 +220,8 @@ config MACH_SUN8I_A23
 	select CPU_V7_HAS_VIRT
 	select ARCH_SUPPORT_PSCI
 	select DRAM_SUN8I_A23
-	select PHY_SUN4I_USB
 	select SPL_I2C
 	select SUNXI_GEN_SUN6I
-	select SUPPORT_SPL
 	select SYS_I2C_SUN8I_RSB
 	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
 
@@ -260,10 +232,8 @@ config MACH_SUN8I_A33
 	select CPU_V7_HAS_VIRT
 	select ARCH_SUPPORT_PSCI
 	select DRAM_SUN8I_A33
-	select PHY_SUN4I_USB
 	select SPL_I2C
 	select SUNXI_GEN_SUN6I
-	select SUPPORT_SPL
 	select SYS_I2C_SUN8I_RSB
 	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
 
@@ -271,12 +241,10 @@ config MACH_SUN8I_A83T
 	bool "sun8i (Allwinner A83T)"
 	select CPU_V7A
 	select DRAM_SUN8I_A83T
-	select PHY_SUN4I_USB
 	select SPL_I2C
 	select SUNXI_GEN_SUN6I
 	select MMC_SUNXI_HAS_NEW_MODE
 	select MMC_SUNXI_HAS_MODE_SWITCH
-	select SUPPORT_SPL
 	select SYS_I2C_SUN8I_RSB
 
 config MACH_SUN8I_H3
@@ -296,10 +264,8 @@ config MACH_SUN8I_R40
 	select ARCH_SUPPORT_PSCI
 	select SUNXI_GEN_SUN6I
 	select MMC_SUNXI_HAS_NEW_MODE
-	select SUPPORT_SPL
 	select SUNXI_DRAM_DW
 	select SUNXI_DRAM_DW_32BIT
-	select PHY_SUN4I_USB
 	imply SPL_SYS_I2C_LEGACY
 
 config MACH_SUN8I_V3S
@@ -311,7 +277,6 @@ config MACH_SUN8I_V3S
 	select SUNXI_GEN_SUN6I
 	select SUNXI_DRAM_DW
 	select SUNXI_DRAM_DW_16BIT
-	select SUPPORT_SPL
 	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
 
 config MACH_SUN9I
@@ -322,17 +287,14 @@ config MACH_SUN9I
 	select SPL_I2C
 	select SUN6I_PRCM
 	select SUNXI_GEN_SUN6I
-	select SUPPORT_SPL
 
 config MACH_SUN50I
 	bool "sun50i (Allwinner A64)"
 	select ARM64
-	select PHY_SUN4I_USB
 	select SUN6I_PRCM
 	select SUNXI_DE2
 	select SUNXI_GEN_SUN6I
 	select MMC_SUNXI_HAS_NEW_MODE
-	select SUPPORT_SPL
 	select SUNXI_DRAM_DW
 	select SUNXI_DRAM_DW_32BIT
 	select FIT
@@ -350,7 +312,6 @@ config MACH_SUN50I_H5
 config MACH_SUN50I_H6
 	bool "sun50i (Allwinner H6)"
 	select ARM64
-	select PHY_SUN4I_USB
 	select DRAM_SUN50I_H6
 	select SUN50I_GEN_H6
 
@@ -587,58 +548,6 @@ config DRAM_ODT_CORRECTION
 	then the correction is negative. Usually the value for this is 0.
 endif
 
-config SYS_CLK_FREQ
-	default 408000000 if MACH_SUNIV
-	default 1008000000 if MACH_SUN4I
-	default 1008000000 if MACH_SUN5I
-	default 1008000000 if MACH_SUN6I
-	default 912000000 if MACH_SUN7I
-	default 816000000 if MACH_SUN50I || MACH_SUN50I_H5
-	default 1008000000 if MACH_SUN8I
-	default 1008000000 if MACH_SUN9I
-	default 888000000 if MACH_SUN50I_H6
-	default 1008000000 if MACH_SUN50I_H616
-
-config SYS_CONFIG_NAME
-	default "suniv" if MACH_SUNIV
-	default "sun4i" if MACH_SUN4I
-	default "sun5i" if MACH_SUN5I
-	default "sun6i" if MACH_SUN6I
-	default "sun7i" if MACH_SUN7I
-	default "sun8i" if MACH_SUN8I
-	default "sun9i" if MACH_SUN9I
-	default "sun50i" if MACH_SUN50I
-	default "sun50i" if MACH_SUN50I_H6
-	default "sun50i" if MACH_SUN50I_H616
-
-config SYS_BOARD
-	default "sunxi"
-
-config SYS_SOC
-	default "sunxi"
-
-config SUNXI_MINIMUM_DRAM_MB
-	int "minimum DRAM size"
-	default 32 if MACH_SUNIV
-	default 64 if MACH_SUN8I_V3S
-	default 256
-	---help---
-	Minimum DRAM size expected on the board. Traditionally we assumed
-	256 MB, so that U-Boot would load at 160MB. With co-packaged DRAM
-	we have smaller sizes, though, so that U-Boot's own load address and
-	the default payload addresses must be shifted down.
-	This is expected to be fixed by the SoC selection.
-
-config UART0_PORT_F
-	bool "UART0 on MicroSD breakout board"
-	---help---
-	Repurpose the SD card slot for getting access to the UART0 serial
-	console. Primarily useful only for low level u-boot debugging on
-	tablets, where normal UART0 is difficult to access and requires
-	device disassembly and/or soldering. As the SD card can't be used
-	at the same time, the system can be only booted in the FEL mode.
-	Only enable this if you really know what you are doing.
-
 config OLD_SUNXI_KERNEL_COMPAT
 	bool "Enable workarounds for booting old kernels"
 	---help---
@@ -652,90 +561,6 @@ config MACPWR
 	  Set the pin used to power the MAC. This takes a string in the format
 	  understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
 
-config MMC0_CD_PIN
-	string "Card detect pin for mmc0"
-	default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
-	default ""
-	---help---
-	Set the card detect pin for mmc0, leave empty to not use cd. This
-	takes a string in the format understood by sunxi_name_to_gpio, e.g.
-	PH1 for pin 1 of port H.
-
-config MMC1_CD_PIN
-	string "Card detect pin for mmc1"
-	default ""
-	---help---
-	See MMC0_CD_PIN help text.
-
-config MMC2_CD_PIN
-	string "Card detect pin for mmc2"
-	default ""
-	---help---
-	See MMC0_CD_PIN help text.
-
-config MMC3_CD_PIN
-	string "Card detect pin for mmc3"
-	default ""
-	---help---
-	See MMC0_CD_PIN help text.
-
-config MMC1_PINS_PH
-	bool "Pins for mmc1 are on Port H"
-	depends on MACH_SUN4I || MACH_SUN7I || MACH_SUN8I_R40
-	---help---
-	Select this option for boards where mmc1 uses the Port H pinmux.
-
-config MMC_SUNXI_SLOT_EXTRA
-	int "mmc extra slot number"
-	default -1
-	---help---
-	sunxi builds always enable mmc0, some boards also have a second sdcard
-	slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
-	support for this.
-
-config USB0_VBUS_PIN
-	string "Vbus enable pin for usb0 (otg)"
-	default ""
-	---help---
-	Set the Vbus enable pin for usb0 (otg). This takes a string in the
-	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
-
-config USB0_VBUS_DET
-	string "Vbus detect pin for usb0 (otg)"
-	default ""
-	---help---
-	Set the Vbus detect pin for usb0 (otg). This takes a string in the
-	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
-
-config USB0_ID_DET
-	string "ID detect pin for usb0 (otg)"
-	default ""
-	---help---
-	Set the ID detect pin for usb0 (otg). This takes a string in the
-	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
-
-config USB1_VBUS_PIN
-	string "Vbus enable pin for usb1 (ehci0)"
-	default "PH6" if MACH_SUN4I || MACH_SUN7I
-	default "PH27" if MACH_SUN6I
-	---help---
-	Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
-	a string in the format understood by sunxi_name_to_gpio, e.g.
-	PH1 for pin 1 of port H.
-
-config USB2_VBUS_PIN
-	string "Vbus enable pin for usb2 (ehci1)"
-	default "PH3" if MACH_SUN4I || MACH_SUN7I
-	default "PH24" if MACH_SUN6I
-	---help---
-	See USB1_VBUS_PIN help text.
-
-config USB3_VBUS_PIN
-	string "Vbus enable pin for usb3 (ehci2)"
-	default ""
-	---help---
-	See USB1_VBUS_PIN help text.
-
 config I2C0_ENABLE
 	bool "Enable I2C/TWI controller 0"
 	default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
@@ -763,22 +588,6 @@ config R_I2C_ENABLE
 	Set this to y to enable the I2C controller which is part of the PRCM.
 endif
 
-config AXP_GPIO
-	bool "Enable support for gpio-s on axp PMICs"
-	depends on AXP_PMIC_BUS
-	---help---
-	Say Y here to enable support for the gpio pins of the axp PMIC ICs.
-
-config AXP_DISABLE_BOOT_ON_POWERON
-	bool "Disable device boot on power plug-in"
-	depends on AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER
-	default n
-	---help---
-	  Say Y here to prevent the device from booting up because of a plug-in
-	  event. When set, the device will boot into the SPL briefly to
-	  determine why it was powered on, and if it was determined because of
-	  a plug-in event instead of a button press event it will shut back off.
-
 config VIDEO_SUNXI
 	bool "Enable graphical uboot console on HDMI, LCD or VGA"
 	depends on !MACH_SUN8I_A83T
@@ -999,17 +808,6 @@ config GMAC_TX_DELAY
 	---help---
 	Set the GMAC Transmit Clock Delay Chain value.
 
-config SPL_STACK_R_ADDR
-	default 0x81e00000 if MACH_SUNIV
-	default 0x4fe00000 if MACH_SUN4I
-	default 0x4fe00000 if MACH_SUN5I
-	default 0x4fe00000 if MACH_SUN6I
-	default 0x4fe00000 if MACH_SUN7I
-	default 0x4fe00000 if MACH_SUN8I
-	default 0x2fe00000 if MACH_SUN9I
-	default 0x4fe00000 if MACH_SUN50I
-	default 0x4fe00000 if SUN50I_GEN_H6
-
 config SPL_SPI_SUNXI
 	bool "Support for SPI Flash on Allwinner SoCs in SPL"
 	depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || SUN50I_GEN_H6 || MACH_SUNIV
@@ -1018,43 +816,4 @@ config SPL_SPI_SUNXI
 	  sunxi SPI Flash. It uses the same method as the boot ROM, so does
 	  not need any extra configuration.
 
-config PINE64_DT_SELECTION
-	bool "Enable Pine64 device tree selection code"
-	depends on MACH_SUN50I
-	help
-	  The original Pine A64 and Pine A64+ are similar but different
-	  boards and can be differed by the DRAM size. Pine A64 has
-	  512MiB DRAM, and Pine A64+ has 1GiB or 2GiB. By selecting this
-	  option, the device tree selection code specific to Pine64 which
-	  utilizes the DRAM size will be enabled.
-
-config PINEPHONE_DT_SELECTION
-	bool "Enable PinePhone device tree selection code"
-	depends on MACH_SUN50I
-	help
-	  Enable this option to automatically select the device tree for the
-	  correct PinePhone hardware revision during boot.
-
-config BLUETOOTH_DT_DEVICE_FIXUP
-	string "Fixup the Bluetooth controller address"
-	default ""
-	help
-	  This option specifies the DT compatible name of the Bluetooth
-	  controller for which to set the "local-bd-address" property.
-	  Set this option if your device ships with the Bluetooth controller
-	  default address.
-	  The used address is "bdaddr" if set, and "ethaddr" with the LSB
-	  flipped elsewise.
-
-source "board/sunxi/Kconfig"
-
 endif
-
-config CHIP_DIP_SCAN
-	bool "Enable DIPs detection for CHIP board"
-	select SUPPORT_EXTENSION_SCAN
-	select W1
-	select W1_GPIO
-	select W1_EEPROM
-	select W1_EEPROM_DS24XXX
-	select CMD_EXTENSION

board/sunxi/Kconfig

@@ -1,5 +1,153 @@
+config BOARD_SUNXI
+	bool
+	select BINMAN
+	select CLK
+	select CMD_GPIO if GPIO
+	select CMD_MMC if MMC
+	select CMD_USB if DISTRO_DEFAULTS && USB_HOST
+	select DM
+	select DM_ETH if NET
+	select DM_GPIO if GPIO
+	select DM_I2C if I2C
+	select DM_SCSI if BLK && SCSI
+	select DM_SERIAL if SERIAL
+	select DM_SPI if SPI
+	select DM_SPI_FLASH if SPI
+	select OF_BOARD_SETUP
+	select PINCTRL
+	select SPL_SEPARATE_BSS if SPL
+	select SUPPORT_SPL
+	select SYS_RELOC_GD_ENV_ADDR
+	select USB if DISTRO_DEFAULTS
+	select USB_KEYBOARD if DISTRO_DEFAULTS && USB_HOST
+	select USE_PREBOOT
+	imply BOARD_LATE_INIT
+	imply CMD_DM
+	imply CMD_GPT
+	imply CMD_UBI if MTD_RAW_NAND
+	imply DISTRO_DEFAULTS
+	imply FAT_WRITE
+	imply FIT
+	imply OF_LIBFDT_OVERLAY
+	imply PRE_CONSOLE_BUFFER
+	imply SPL
+	imply SPL_GPIO
+	imply SPL_LIBCOMMON_SUPPORT
+	imply SPL_LIBGENERIC_SUPPORT
+	imply SPL_MMC if MMC
+	imply SPL_POWER
+	imply SPL_SERIAL
+	imply SUNXI_GPIO
+	imply SYS_I2C_MVTWSI
+	imply SYS_NS16550
+	imply SYSRESET
+	imply SYSRESET_WATCHDOG
+	imply SYSRESET_WATCHDOG_AUTO
+	imply USB_EHCI_GENERIC
+	imply USB_EHCI_HCD
+	imply USB_GADGET
+	imply USB_OHCI_GENERIC
+	imply USB_OHCI_HCD
+	imply WDT
+
+if BOARD_SUNXI
+
+config IDENT_STRING
+	default " Allwinner Technology"
+
+config PRE_CON_BUF_ADDR
+	default 0x81000000 if MACH_SUNIV
+	default 0x2f000000 if MACH_SUN9I
+	default 0x4f000000 if SUNXI_MINIMUM_DRAM_MB >= 256
+	default 0x43000000 if SUNXI_MINIMUM_DRAM_MB >= 64
+
+config SPL_BSS_START_ADDR
+	default 0x81f80000 if MACH_SUNIV
+	default 0x2ff80000 if MACH_SUN9I
+	default 0x4ff80000 if SUNXI_MINIMUM_DRAM_MB >= 256
+	default 0x43f80000 if SUNXI_MINIMUM_DRAM_MB >= 64
+
+config SPL_STACK_R_ADDR
+	default 0x81e00000 if MACH_SUNIV
+	default 0x2fe00000 if MACH_SUN9I
+	default 0x4fe00000 if SUNXI_MINIMUM_DRAM_MB >= 256
+	default 0x43e00000 if SUNXI_MINIMUM_DRAM_MB >= 64
+
+config SPL_TEXT_BASE
+	default 0x10060 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5
+	default 0x20060 if SUN50I_GEN_H6
+	default 0x00060
+
+config SUNXI_MINIMUM_DRAM_MB
+	int
+	default 32 if MACH_SUNIV
+	default 64 if MACH_SUN8I_V3S
+	default 256
+	help
+	  Minimum DRAM size expected on the board. Traditionally we
+	  assumed 256 MB, so that U-Boot would load at 160MB. With
+	  co-packaged DRAM we have smaller sizes, though, so U-Boot's
+	  own load address and the default payload addresses must be
+	  shifted down. This is expected to be fixed by the SoC
+	  selection.
+
+config SUNXI_SRAM_ADDRESS
+	hex
+	default 0x10000 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5
+	default 0x20000 if SUN50I_GEN_H6
+	default 0x0
+	help
+	  Older Allwinner SoCs have their boot mask ROM mapped just
+	  below 4GB, with the first SRAM region located at address 0.
+	  Newer SoCs map the boot ROM at address 0 instead and move the
+	  SRAM to a different address.
+
+config SYS_BOARD
+	default "sunxi"
+
+config SYS_CLK_FREQ
+	default  408000000 if MACH_SUNIV
+	default 1008000000 if MACH_SUN4I
+	default 1008000000 if MACH_SUN5I
+	default 1008000000 if MACH_SUN6I
+	default  912000000 if MACH_SUN7I
+	default 1008000000 if MACH_SUN8I
+	default 1008000000 if MACH_SUN9I
+	default  816000000 if MACH_SUN50I || MACH_SUN50I_H5
+	default  888000000 if MACH_SUN50I_H6
+	default 1008000000 if MACH_SUN50I_H616
+
+config SYS_CONFIG_NAME
+	default "suniv"  if MACH_SUNIV
+	default "sun4i"  if MACH_SUN4I
+	default "sun5i"  if MACH_SUN5I
+	default "sun6i"  if MACH_SUN6I
+	default "sun7i"  if MACH_SUN7I
+	default "sun8i"  if MACH_SUN8I
+	default "sun9i"  if MACH_SUN9I
+	default "sun50i" if MACH_SUN50I
+	default "sun50i" if MACH_SUN50I_H6
+	default "sun50i" if MACH_SUN50I_H616
+
+config SYS_LOAD_ADDR
+	default 0x81000000 if MACH_SUNIV
+	default 0x22000000 if MACH_SUN9I
+	default 0x42000000
+
+config SYS_SOC
+	default "sunxi"
+
+config TEXT_BASE
+	default 0x81700000 if MACH_SUNIV
+	default 0x2a000000 if MACH_SUN9I
+	default 0x4a000000 if SUNXI_MINIMUM_DRAM_MB >= 256
+	default 0x42e00000 if SUNXI_MINIMUM_DRAM_MB >= 64
+
+menu "sunxi board options"
+
 choice
 	prompt "SPL Image Type"
+	depends on SPL
 	default SPL_IMAGE_TYPE_SUNXI_EGON
 
 config SPL_IMAGE_TYPE_SUNXI_EGON
@@ -22,3 +170,79 @@ config SPL_IMAGE_TYPE
 	string
 	default "sunxi_egon" if SPL_IMAGE_TYPE_SUNXI_EGON
 	default "sunxi_toc0" if SPL_IMAGE_TYPE_SUNXI_TOC0
+
+config MMC_SUNXI_SLOT_EXTRA
+	int "MMC extra slot number"
+	default -1
+	help
+	  sunxi builds always enable mmc0. Some boards also have a
+	  second SD card slot or eMMC on mmc1 - mmc3. Setting this to 1,
+	  2 or 3 will enable support for this.
+
+config MMC1_PINS_PH
+	bool "MMC1 pins are on Port H"
+	depends on MACH_SUN4I || MACH_SUN7I || MACH_SUN8I_R40
+	help
+	  Select this option on boards where mmc1 uses the Port H pinmux.
+
+config UART0_PORT_F
+	bool "UART0 pins are on Port F (MicroSD breakout board)"
+	help
+	  Repurpose the SD card slot for getting access to the UART0
+	  serial console. Primarily useful only for low level u-boot
+	  debugging on tablets, where normal UART0 is difficult to
+	  access and requires device disassembly and/or soldering. As
+	  the SD card can't be used at the same time, the system can be
+	  only booted in FEL mode. Only enable this if you really know
+	  what you are doing.
+
+config AXP_DISABLE_BOOT_ON_POWERON
+	bool "Disable device boot on power plug-in"
+	depends on AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER
+	help
+	  Say Y here to prevent the device from booting up because of a
+	  plug-in event. When set, the device will boot into the SPL
+	  briefly to determine why it was powered on, and if the board
+	  was powered on because of a plug-in event instead of a button
+	  press event, it will shut back off.
+
+config CHIP_DIP_SCAN
+	bool "Enable DIPs detection for CHIP board"
+	select SUPPORT_EXTENSION_SCAN
+	select W1
+	select W1_GPIO
+	select W1_EEPROM
+	select W1_EEPROM_DS24XXX
+	select CMD_EXTENSION
+
+config PINE64_DT_SELECTION
+	bool "Enable Pine64 device tree selection code"
+	depends on MACH_SUN50I
+	help
+	  The original Pine A64 and Pine A64+ are similar but different
+	  boards and can be differed by the DRAM size. Pine A64 has
+	  512MiB DRAM, and Pine A64+ has 1GiB or 2GiB. By selecting this
+	  option, the device tree selection code specific to Pine64 which
+	  utilizes the DRAM size will be enabled.
+
+config PINEPHONE_DT_SELECTION
+	bool "Enable PinePhone device tree selection code"
+	depends on MACH_SUN50I
+	help
+	  Enable this option to automatically select the device tree for the
+	  correct PinePhone hardware revision during boot.
+
+config BLUETOOTH_DT_DEVICE_FIXUP
+	string "Fixup the Bluetooth controller address"
+	default ""
+	help
+	  This option specifies the DT compatible name of the Bluetooth
+	  controller for which to set the "local-bd-address" property.
+	  Set this option if your device ships with the Bluetooth controller
+	  default address.
+	  The used address is "bdaddr" if set, and "ethaddr" with the LSB
+	  flipped elsewise.
+
+endmenu
+
+endif

board/sunxi/board.c

@@ -19,6 +19,7 @@
 #include <init.h>
 #include <log.h>
 #include <mmc.h>
+#include <remoteproc.h>
 #include <axp_pmic.h>
 #include <generic-phy.h>
 #include <phy-sun4i-usb.h>
@@ -224,10 +225,6 @@ int board_init(void)
 	}
 #endif /* !CONFIG_ARM64 && !CONFIG_MACH_SUNIV */
 
-	ret = axp_gpio_init();
-	if (ret)
-		return ret;
-
 	/* strcmp() would look better, but doesn't get optimised away. */
 	if (CONFIG_SATAPWR[0]) {
 		satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
@@ -315,7 +312,7 @@ int dram_init(void)
 	return 0;
 }
 
-#if defined(CONFIG_NAND_SUNXI)
+#if defined(CONFIG_NAND_SUNXI) && defined(CONFIG_SPL_BUILD)
 static void nand_pinmux_setup(void)
 {
 	unsigned int pin;
@@ -351,9 +348,6 @@ void board_nand_init(void)
 {
 	nand_pinmux_setup();
 	nand_clock_setup();
-#ifndef CONFIG_SPL_BUILD
-	sunxi_nand_init();
-#endif
 }
 #endif
 
@@ -869,6 +863,13 @@ int board_late_init(void)
 	usb_ether_init();
 #endif
 
+#ifdef CONFIG_REMOTEPROC_SUN6I_AR100
+	if (!rproc_load(0, SUNXI_SCP_BASE, SUNXI_SCP_MAX_SIZE)) {
+		puts("Starting SCP...\n");
+		rproc_start(0);
+	}
+#endif
+
 	return 0;
 }
 

boot/Kconfig

@@ -633,10 +633,6 @@ config TEXT_BASE
 	depends on HAVE_TEXT_BASE
 	default 0x0 if POSITION_INDEPENDENT
 	default 0x80800000 if ARCH_OMAP2PLUS || ARCH_K3
-	default 0x81700000 if MACH_SUNIV
-	default 0x2a000000 if MACH_SUN9I
-	default 0x4a000000 if SUNXI_MINIMUM_DRAM_MB >= 256
-	default 0x42e00000 if SUNXI_MINIMUM_DRAM_MB >= 64
 	hex "Text Base"
 	help
 	  The address in memory that U-Boot will be running from, initially.

boot/image.c

@@ -180,6 +180,7 @@ static const table_entry_t uimage_type[] = {
 	{	IH_TYPE_COPRO, "copro", "Coprocessor Image"},
 	{	IH_TYPE_SUNXI_EGON, "sunxi_egon",  "Allwinner eGON Boot Image" },
 	{	IH_TYPE_SUNXI_TOC0, "sunxi_toc0",  "Allwinner TOC0 Boot Image" },
+	{	IH_TYPE_SUNXI_TOC1, "sunxi_toc1",  "Allwinner TOC1 Boot Image" },
 	{	-1,		    "",		  "",			},
 };
 

common/Kconfig

@@ -195,8 +195,6 @@ config PRE_CON_BUF_SZ
 config PRE_CON_BUF_ADDR
 	hex "Address of the pre-console buffer"
 	depends on PRE_CONSOLE_BUFFER
-	default 0x2f000000 if ARCH_SUNXI && MACH_SUN9I
-	default 0x4f000000 if ARCH_SUNXI && !MACH_SUN9I
 	default 0x0f000000 if ROCKCHIP_RK3288
 	default 0x0f200000 if ROCKCHIP_RK3399
 	help

common/spl/Kconfig

@@ -76,12 +76,12 @@ config SPL_SIZE_LIMIT_PROVIDE_STACK
 
 config SPL_MAX_SIZE
 	hex "Maximum size of the SPL image, excluding BSS"
+	default 0x37fa0 if MACH_SUN50I_H616
 	default 0x30000 if ARCH_MX6 && MX6_OCRAM_256KB
+	default 0x25fa0 if MACH_SUN50I_H6
 	default 0x1b000 if AM33XX && !TI_SECURE_DEVICE
 	default 0x10000 if ARCH_MX6 && !MX6_OCRAM_256KB
 	default 0x7fa0 if SUNXI_SRAM_ADDRESS = 0x10000
-	default 0x7fa0 if SUNXI_SRAM_ADDRESS = 0x20000 && !MACH_SUN50I_H616
-	default 0xbfa0 if MACH_SUN50I_H616
 	default 0x7000 if RCAR_GEN3
 	default 0x5fa0 if SUNXI_SRAM_ADDRESS = 0x0
 	default 0x10000 if ASPEED_AST2600
@@ -97,7 +97,7 @@ config SPL_PAD_TO
 	default 0x31000 if ARCH_MX6 && MX6_OCRAM_256KB
 	default 0x11000 if ARCH_MX7 || (ARCH_MX6 && !MX6_OCRAM_256KB)
 	default 0x10000 if ARCH_KEYSTONE
-	default 0x8000 if ARCH_SUNXI && !MACH_SUN50I_H616
+	default 0x0 if ARCH_SUNXI
 	default TPL_MAX_SIZE if TPL_MAX_SIZE > SPL_MAX_SIZE
 	default SPL_MAX_SIZE
 	help
@@ -110,7 +110,7 @@ config SPL_PAD_TO
 config SPL_HAS_BSS_LINKER_SECTION
 	depends on SPL_FRAMEWORK
 	bool "Use a specific address for the BSS via the linker script"
-	default y if ARCH_SUNXI || ARCH_MX6 || ARCH_OMAP2PLUS || MIPS || RISCV || ARCH_ZYNQMP
+	default y if ARCH_MX6 || ARCH_OMAP2PLUS || ARCH_ZYNQMP || BOARD_SUNXI || MIPS || RISCV
 
 config SPL_BSS_START_ADDR
 	hex "Link address for the BSS within the SPL binary"
@@ -118,9 +118,6 @@ config SPL_BSS_START_ADDR
 	default 0x88200000 if (ARCH_MX6 && (MX6SX || MX6SL || MX6UL || MX6ULL)) || ARCH_MX7
 	default 0x18200000 if ARCH_MX6 && !(MX6SX || MX6SL || MX6UL || MX6ULL)
 	default 0x80a00000 if ARCH_OMAP2PLUS
-	default 0x81f80000 if ARCH_SUNXI && MACH_SUNIV
-	default 0x4ff80000 if ARCH_SUNXI && !(MACH_SUN9I || MACH_SUNIV)
-	default 0x2ff80000 if ARCH_SUNXI && MACH_SUN9I
 	default 0x1000 if ARCH_ZYNQMP
 
 choice
@@ -263,9 +260,6 @@ config SPL_TEXT_BASE
 	default 0x402F4000 if AM43XX
 	default 0x402F0400 if AM33XX
 	default 0x40301350 if OMAP54XX
-	default 0x10060 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN9I
-	default 0x20060 if SUN50I_GEN_H6
-	default 0x00060 if ARCH_SUNXI
 	default 0xfffc0000 if ARCH_ZYNQMP
 	default 0x0
 	help
@@ -340,7 +334,7 @@ config SPL_SYS_MALLOC_SIMPLE
 config SPL_SHARES_INIT_SP_ADDR
 	bool "SPL and U-Boot use the same initial stack pointer location"
 	depends on (ARM || ARCH_JZ47XX || MICROBLAZE || RISCV) && SPL_FRAMEWORK
-	default n if ARCH_SUNXI || ARCH_MX6 || ARCH_MX7
+	default n if BOARD_SUNXI || ARCH_MX6 || ARCH_MX7
 	default y
 	help
 	  In many cases, we can use the same initial stack pointer address for
@@ -458,7 +452,7 @@ config SPL_DISPLAY_PRINT
 
 config SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
 	bool "MMC raw mode: by sector"
-	default y if ARCH_SUNXI || ARCH_DAVINCI || ARCH_UNIPHIER || \
+	default y if BOARD_SUNXI || ARCH_DAVINCI || ARCH_UNIPHIER || \
 		     ARCH_MX6 || ARCH_MX7 || \
 		     ARCH_ROCKCHIP || ARCH_MVEBU ||  ARCH_SOCFPGA || \
 		     ARCH_AT91 || ARCH_ZYNQ || ARCH_KEYSTONE || OMAP34XX || \
@@ -471,7 +465,7 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
 config SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
 	hex "Address on the MMC to load U-Boot from"
 	depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
-	default 0x40 if ARCH_SUNXI
+	default 0x40 if BOARD_SUNXI
 	default 0x75 if ARCH_DAVINCI
 	default 0x8a if ARCH_MX6 || ARCH_MX7
 	default 0x100 if ARCH_UNIPHIER
@@ -488,7 +482,7 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
 config SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET
 	hex "U-Boot main hardware partition image offset"
 	depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
-	default 0x10 if ARCH_SUNXI
+	default 0x10 if BOARD_SUNXI
 	default 0x0
 	help
 	  On some platforms SPL location depends on hardware partition. The ROM
@@ -574,8 +568,7 @@ config SPL_MD5
 config SPL_FIT_IMAGE_TINY
 	bool "Remove functionality from SPL FIT loading to reduce size"
 	depends on SPL_FIT
-	default y if MACH_SUN50I || MACH_SUN50I_H5 || SUN50I_GEN_H6
-	default y if ARCH_IMX8M || ARCH_IMX9
+	default y if ARCH_IMX8M || ARCH_IMX9 || ARCH_SUNXI
 	help
 	  Enable this to reduce the size of the FIT image loading code
 	  in SPL, if space for the SPL binary is very tight.
@@ -1314,7 +1307,7 @@ endif # SPL_SPI_FLASH_SUPPORT
 
 config SYS_SPI_U_BOOT_OFFS
 	hex "address of u-boot payload in SPI flash"
-	default 0x8000 if ARCH_SUNXI
+	default 0x8000 if BOARD_SUNXI
 	default 0x0
 	depends on SPL_SPI_LOAD || SPL_SPI_SUNXI
 	help
@@ -1439,7 +1432,8 @@ config SPL_YMODEM_SUPPORT
 
 config SPL_ATF
 	bool "Support ARM Trusted Firmware"
-	depends on ARM64 && SPL_FIT
+	depends on ARM64
+	depends on SPL_LOAD_FIT && !SPL_FIT_IMAGE_TINY
 	help
 	  ATF(ARM Trusted Firmware) is a component for ARM AArch64 which
 	  is loaded by SPL (which is considered as BL2 in ATF terminology).
@@ -1486,6 +1480,7 @@ config SPL_OPTEE_IMAGE
 config SPL_OPENSBI
 	bool "Support RISC-V OpenSBI"
 	depends on RISCV && SPL_RISCV_MMODE && RISCV_SMODE
+	depends on SPL_LOAD_FIT && !SPL_FIT_IMAGE_TINY
 	help
 	  OpenSBI is an open-source implementation of the RISC-V Supervisor Binary
 	  Interface (SBI) specification. U-Boot supports the OpenSBI FW_DYNAMIC

configs/A10-OLinuXino-Lime_defconfig

@@ -6,7 +6,6 @@ CONFIG_MACH_SUN4I=y
 CONFIG_DRAM_CLK=480
 CONFIG_DRAM_EMR1=4
 CONFIG_SYS_CLK_FREQ=912000000
-CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_I2C1_ENABLE=y
 CONFIG_SATAPWR="PC3"
 CONFIG_AHCI=y
@@ -19,6 +18,7 @@ CONFIG_SYS_I2C_SLAVE=0x7f
 CONFIG_SYS_I2C_SPEED=400000
 CONFIG_MII=y
 CONFIG_SUN4I_EMAC=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_AXP_ALDO3_VOLT=2800
 CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_SCSI=y

configs/A10s-OLinuXino-M_defconfig

@@ -4,10 +4,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-olinuxino-micro"
 CONFIG_SPL=y
 CONFIG_MACH_SUN5I=y
 CONFIG_DRAM_CLK=432
-CONFIG_MMC0_CD_PIN="PG1"
-CONFIG_MMC1_CD_PIN="PG13"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=1
-CONFIG_USB1_VBUS_PIN="PB10"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_I2C=y
 CONFIG_SYS_I2C_MVTWSI=y
@@ -15,6 +12,7 @@ CONFIG_SYS_I2C_SLAVE=0x7f
 CONFIG_SYS_I2C_SPEED=400000
 CONFIG_MII=y
 CONFIG_SUN4I_EMAC=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_AXP152_POWER=y
 CONFIG_CONS_INDEX=2
 CONFIG_USB_EHCI_HCD=y

configs/A13-OLinuXinoM_defconfig

@@ -5,8 +5,6 @@ CONFIG_SPL=y
 CONFIG_MACH_SUN5I=y
 CONFIG_DRAM_CLK=408
 CONFIG_DRAM_EMR1=0
-CONFIG_MMC0_CD_PIN="PG0"
-CONFIG_USB1_VBUS_PIN="PG11"
 # CONFIG_VIDEO_HDMI is not set
 CONFIG_VIDEO_VGA_VIA_LCD=y
 CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH=y
@@ -16,6 +14,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2"
 CONFIG_SYS_I2C_MVTWSI=y
 CONFIG_SYS_I2C_SLAVE=0x7f
 CONFIG_SYS_I2C_SPEED=400000
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_SUNXI_NO_PMIC=y
 CONFIG_CONS_INDEX=2
 CONFIG_USB_EHCI_HCD=y

configs/A13-OLinuXino_defconfig

@@ -5,10 +5,6 @@ CONFIG_SPL=y
 CONFIG_MACH_SUN5I=y
 CONFIG_DRAM_CLK=408
 CONFIG_DRAM_EMR1=0
-CONFIG_MMC0_CD_PIN="PG0"
-CONFIG_USB0_VBUS_DET="PG1"
-CONFIG_USB1_VBUS_PIN="PG11"
-CONFIG_AXP_GPIO=y
 # CONFIG_VIDEO_HDMI is not set
 CONFIG_VIDEO_VGA_VIA_LCD=y
 CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH=y
@@ -20,9 +16,11 @@ CONFIG_CMD_DFU=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_DFU_RAM=y
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_AXP_GPIO=y
 CONFIG_SYS_I2C_MVTWSI=y
 CONFIG_SYS_I2C_SLAVE=0x7f
 CONFIG_SYS_I2C_SPEED=400000
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_AXP_ALDO3_VOLT=3300
 CONFIG_CONS_INDEX=2
 CONFIG_USB_EHCI_HCD=y

configs/A20-OLinuXino-Lime2-eMMC_defconfig

@@ -4,10 +4,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime2-emmc"
 CONFIG_SPL=y
 CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=384
-CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-CONFIG_USB0_VBUS_PIN="PC17"
-CONFIG_USB0_VBUS_DET="PH5"
 CONFIG_I2C1_ENABLE=y
 CONFIG_SATAPWR="PC3"
 CONFIG_SPL_SPI_SUNXI=y
@@ -30,6 +27,7 @@ CONFIG_ETH_DESIGNWARE=y
 CONFIG_RGMII=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_AXP_ALDO3_VOLT=2800
 CONFIG_AXP_ALDO3_VOLT_SLOPE_08=y
 CONFIG_AXP_ALDO3_INRUSH_QUIRK=y

configs/A20-OLinuXino-Lime2_defconfig

@@ -4,9 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime2"
 CONFIG_SPL=y
 CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=384
-CONFIG_MMC0_CD_PIN="PH1"
-CONFIG_USB0_VBUS_PIN="PC17"
-CONFIG_USB0_VBUS_DET="PH5"
 CONFIG_I2C1_ENABLE=y
 CONFIG_SATAPWR="PC3"
 CONFIG_AHCI=y
@@ -27,6 +24,7 @@ CONFIG_ETH_DESIGNWARE=y
 CONFIG_RGMII=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_AXP_ALDO3_VOLT=2800
 CONFIG_AXP_ALDO3_VOLT_SLOPE_08=y
 CONFIG_AXP_ALDO3_INRUSH_QUIRK=y

configs/A20-OLinuXino-Lime_defconfig

@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime"
 CONFIG_SPL=y
 CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=384
-CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_I2C1_ENABLE=y
 CONFIG_SATAPWR="PC3"
 CONFIG_AHCI=y
@@ -19,6 +18,7 @@ CONFIG_PHY_REALTEK=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_AXP_ALDO3_VOLT=2800
 CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_SCSI=y

configs/A20-OLinuXino_MICRO-eMMC_defconfig

@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-micro-emmc"
 CONFIG_SPL=y
 CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=384
-CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
 CONFIG_I2C1_ENABLE=y
 CONFIG_VIDEO_VGA=y
@@ -22,6 +21,7 @@ CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
 CONFIG_SUN7I_GMAC_FORCE_TXERR=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_AXP_ALDO3_VOLT=2800
 CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_SCSI=y

configs/A20-OLinuXino_MICRO_defconfig

@@ -4,8 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-micro"
 CONFIG_SPL=y
 CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=384
-CONFIG_MMC0_CD_PIN="PH1"
-CONFIG_MMC3_CD_PIN="PH11"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=3
 CONFIG_I2C1_ENABLE=y
 CONFIG_VIDEO_VGA=y
@@ -23,6 +21,7 @@ CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
 CONFIG_SUN7I_GMAC_FORCE_TXERR=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_AXP_ALDO3_VOLT=2800
 CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_SCSI=y

configs/A20-Olimex-SOM-EVB_defconfig

@@ -4,11 +4,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olimex-som-evb"
 CONFIG_SPL=y
 CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=384
-CONFIG_MMC0_CD_PIN="PH1"
-CONFIG_MMC3_CD_PIN="PH0"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=3
-CONFIG_USB0_VBUS_PIN="PB9"
-CONFIG_USB0_VBUS_DET="PH5"
 CONFIG_SATAPWR="PC3"
 CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
@@ -24,6 +20,7 @@ CONFIG_ETH_DESIGNWARE=y
 CONFIG_RGMII=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_AXP_ALDO3_VOLT=2800
 CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_SCSI=y

configs/A20-Olimex-SOM204-EVB-eMMC_defconfig

@@ -4,10 +4,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olimex-som204-evb-emmc"
 CONFIG_SPL=y
 CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=384
-CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-CONFIG_USB0_VBUS_PIN="PC17"
-CONFIG_USB0_VBUS_DET="PH5"
 CONFIG_I2C1_ENABLE=y
 CONFIG_SATAPWR="PC3"
 CONFIG_GMAC_TX_DELAY=4
@@ -28,6 +25,7 @@ CONFIG_ETH_DESIGNWARE=y
 CONFIG_RGMII=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_AXP_ALDO3_VOLT=2800
 CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_SCSI=y

configs/A20-Olimex-SOM204-EVB_defconfig

@@ -4,9 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olimex-som204-evb"
 CONFIG_SPL=y
 CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=384
-CONFIG_MMC0_CD_PIN="PH1"
-CONFIG_USB0_VBUS_PIN="PC17"
-CONFIG_USB0_VBUS_DET="PH5"
 CONFIG_I2C1_ENABLE=y
 CONFIG_SATAPWR="PC3"
 CONFIG_GMAC_TX_DELAY=4
@@ -27,6 +24,7 @@ CONFIG_ETH_DESIGNWARE=y
 CONFIG_RGMII=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_AXP_ALDO3_VOLT=2800
 CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_SCSI=y

configs/A33-OLinuXino_defconfig

@@ -6,15 +6,13 @@ CONFIG_MACH_SUN8I_A33=y
 CONFIG_DRAM_CLK=432
 CONFIG_DRAM_ZQ=15291
 CONFIG_DRAM_ODT_EN=y
-CONFIG_MMC0_CD_PIN="PB4"
-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
-CONFIG_USB0_ID_DET="PB3"
-CONFIG_AXP_GPIO=y
 CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:3,vmode:0"
 CONFIG_VIDEO_LCD_DCLK_PHASE=0
 CONFIG_VIDEO_LCD_BL_EN="PB2"
 CONFIG_VIDEO_LCD_BL_PWM="PH0"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_AXP_GPIO=y
+CONFIG_REGULATOR_AXP=y
+CONFIG_REGULATOR_AXP_USB_POWER=y
 CONFIG_AXP_DCDC1_VOLT=3300
 CONFIG_USB_MUSB_HOST=y

configs/Ainol_AW1_defconfig

@@ -5,17 +5,16 @@ CONFIG_SPL=y
 CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=432
 CONFIG_DRAM_ZQ=123
-CONFIG_MMC0_CD_PIN="PH1"
-CONFIG_USB0_VBUS_PIN="PB9"
-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
-CONFIG_AXP_GPIO=y
 CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:40000,le:87,ri:112,up:38,lo:141,hs:1,vs:1,sync:3,vmode:0"
 CONFIG_VIDEO_LCD_POWER="PH8"
 CONFIG_VIDEO_LCD_BL_EN="PH7"
 CONFIG_VIDEO_LCD_BL_PWM="PB2"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_I2C=y
+CONFIG_AXP_GPIO=y
 CONFIG_SYS_I2C_MVTWSI=y
 CONFIG_SYS_I2C_SLAVE=0x7f
 CONFIG_SYS_I2C_SPEED=400000
+CONFIG_REGULATOR_AXP_USB_POWER=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_USB_MUSB_HOST=y

configs/Ampe_A76_defconfig

@@ -4,11 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-ampe-a76"
 CONFIG_SPL=y
 CONFIG_MACH_SUN5I=y
 CONFIG_DRAM_CLK=432
-CONFIG_MMC0_CD_PIN="PG0"
-CONFIG_USB0_VBUS_PIN="PG12"
-CONFIG_USB0_VBUS_DET="PG1"
-CONFIG_USB0_ID_DET="PG2"
-CONFIG_AXP_GPIO=y
 # CONFIG_VIDEO_HDMI is not set
 CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:45,ri:82,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0"
 CONFIG_VIDEO_LCD_POWER="AXP0-0"
@@ -16,8 +11,10 @@ CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
 CONFIG_VIDEO_LCD_BL_PWM="PB2"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_I2C=y
+CONFIG_AXP_GPIO=y
 CONFIG_SYS_I2C_MVTWSI=y
 CONFIG_SYS_I2C_SLAVE=0x7f
 CONFIG_SYS_I2C_SPEED=400000
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_CONS_INDEX=2
 CONFIG_USB_MUSB_HOST=y

configs/Auxtek-T003_defconfig

@@ -5,13 +5,13 @@ CONFIG_SPL=y
 CONFIG_MACH_SUN5I=y
 CONFIG_DRAM_CLK=408
 CONFIG_DRAM_EMR1=0
-CONFIG_USB1_VBUS_PIN="PB10"
 CONFIG_VIDEO_COMPOSITE=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_I2C=y
 CONFIG_SYS_I2C_MVTWSI=y
 CONFIG_SYS_I2C_SLAVE=0x7f
 CONFIG_SYS_I2C_SPEED=400000
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_AXP152_POWER=y
 CONFIG_CONS_INDEX=2
 CONFIG_USB_EHCI_HCD=y

configs/Auxtek-T004_defconfig

@@ -4,12 +4,12 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-auxtek-t004"
 CONFIG_SPL=y
 CONFIG_MACH_SUN5I=y
 CONFIG_DRAM_CLK=432
-CONFIG_USB1_VBUS_PIN="PG13"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_I2C=y
 CONFIG_SYS_I2C_MVTWSI=y
 CONFIG_SYS_I2C_SLAVE=0x7f
 CONFIG_SYS_I2C_SPEED=400000
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_AXP152_POWER=y
 CONFIG_CONS_INDEX=2
 CONFIG_USB_EHCI_HCD=y

configs/Bananapi_M2_Ultra_defconfig

@@ -5,10 +5,7 @@ CONFIG_SPL=y
 CONFIG_MACH_SUN8I_R40=y
 CONFIG_DRAM_CLK=576
 CONFIG_MACPWR="PA17"
-CONFIG_MMC0_CD_PIN="PH13"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-CONFIG_USB1_VBUS_PIN="PH23"
-CONFIG_USB2_VBUS_PIN="PH23"
 # CONFIG_HAS_ARMV7_SECURE_BASE is not set
 CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
@@ -20,6 +17,7 @@ CONFIG_SYS_I2C_SLAVE=0x7f
 CONFIG_SYS_I2C_SPEED=400000
 CONFIG_RGMII=y
 CONFIG_SUN8I_EMAC=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_AXP_DLDO4_VOLT=2500
 CONFIG_AXP_ELDO3_VOLT=1200
 CONFIG_SCSI=y

configs/Bananapi_defconfig

@@ -21,6 +21,7 @@ CONFIG_ETH_DESIGNWARE=y
 CONFIG_RGMII=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_SCSI=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y

configs/Bananapi_m2m_defconfig

@@ -6,9 +6,7 @@ CONFIG_MACH_SUN8I_A33=y
 CONFIG_DRAM_CLK=600
 CONFIG_DRAM_ZQ=15291
 CONFIG_DRAM_ODT_EN=y
-CONFIG_MMC0_CD_PIN="PB4"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-CONFIG_USB0_ID_DET="PH8"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
 CONFIG_USB_EHCI_HCD=y

configs/Bananapro_defconfig

@@ -5,8 +5,6 @@ CONFIG_SPL=y
 CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=432
 CONFIG_MACPWR="PH23"
-CONFIG_USB1_VBUS_PIN="PH0"
-CONFIG_USB2_VBUS_PIN="PH1"
 CONFIG_VIDEO_COMPOSITE=y
 CONFIG_GMAC_TX_DELAY=3
 CONFIG_AHCI=y
@@ -23,6 +21,7 @@ CONFIG_ETH_DESIGNWARE=y
 CONFIG_RGMII=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_AXP_ALDO4_VOLT=2500
 CONFIG_SCSI=y
 CONFIG_USB_EHCI_HCD=y

configs/CHIP_defconfig

@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-r8-chip"
 CONFIG_SPL=y
 CONFIG_MACH_SUN5I=y
 CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y
-CONFIG_USB0_VBUS_PIN="PB10"
 CONFIG_VIDEO_COMPOSITE=y
 CONFIG_CHIP_DIP_SCAN=y
 CONFIG_SPL_I2C=y
@@ -14,6 +13,7 @@ CONFIG_SYS_I2C_MVTWSI=y
 CONFIG_SYS_I2C_SLAVE=0x7f
 CONFIG_SYS_I2C_SPEED=400000
 # CONFIG_MMC is not set
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_AXP_ALDO3_VOLT=3300
 CONFIG_AXP_ALDO4_VOLT=3300
 CONFIG_CONS_INDEX=2

configs/CHIP_pro_defconfig

@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-gr8-chip-pro"
 CONFIG_SPL=y
 CONFIG_MACH_SUN5I=y
 CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y
-CONFIG_USB0_VBUS_PIN="PB10"
 CONFIG_SPL_I2C=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_MTDPARTS=y
@@ -23,6 +22,7 @@ CONFIG_SYS_NAND_BLOCK_SIZE=0x40000
 CONFIG_SYS_NAND_ONFI_DETECTION=y
 CONFIG_SYS_NAND_PAGE_SIZE=0x1000
 CONFIG_SYS_NAND_OOBSIZE=0x100
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_AXP_ALDO3_VOLT=3300
 CONFIG_AXP_ALDO4_VOLT=3300
 CONFIG_CONS_INDEX=2

configs/CSQ_CS908_defconfig

@@ -4,13 +4,12 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-cs908"
 CONFIG_SPL=y
 CONFIG_MACH_SUN6I=y
 CONFIG_DRAM_CLK=432
-CONFIG_USB1_VBUS_PIN=""
-CONFIG_USB2_VBUS_PIN=""
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_PHY_REALTEK=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_AXP_ALDO1_VOLT=3300
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_USB_EHCI_HCD=y

configs/Chuwi_V7_CW0825_defconfig

@@ -5,9 +5,6 @@ CONFIG_SPL=y
 CONFIG_MACH_SUN4I=y
 CONFIG_DRAM_CLK=408
 CONFIG_DRAM_EMR1=4
-CONFIG_USB0_VBUS_PIN="PB9"
-CONFIG_USB0_VBUS_DET="PH5"
-CONFIG_USB0_ID_DET="PH4"
 CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:24,pclk_khz:51000,le:19,ri:300,up:6,lo:31,hs:1,vs:1,sync:3,vmode:0"
 CONFIG_VIDEO_LCD_POWER="PH8"
 CONFIG_VIDEO_LCD_BL_EN="PH7"
@@ -18,6 +15,7 @@ CONFIG_SPL_I2C=y
 CONFIG_SYS_I2C_MVTWSI=y
 CONFIG_SYS_I2C_SLAVE=0x7f
 CONFIG_SYS_I2C_SPEED=400000
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_USB_MUSB_HOST=y
 CONFIG_VIDEO_LCD_SPI_CS="PA0"
 CONFIG_VIDEO_LCD_SPI_SCLK="PA1"

configs/Colombus_defconfig

@@ -5,9 +5,7 @@ CONFIG_SPL=y
 CONFIG_MACH_SUN6I=y
 CONFIG_DRAM_CLK=240
 CONFIG_DRAM_ZQ=251
-CONFIG_USB1_VBUS_PIN=""
 CONFIG_I2C0_ENABLE=y
-CONFIG_AXP_GPIO=y
 CONFIG_VIDEO_LCD_MODE="x:2048,y:1536,depth:24,pclk_khz:208000,le:5,ri:150,up:9,lo:24,hs:5,vs:1,sync:3,vmode:0"
 CONFIG_VIDEO_LCD_DCLK_PHASE=0
 CONFIG_VIDEO_LCD_POWER="PH27"
@@ -15,6 +13,7 @@ CONFIG_VIDEO_LCD_BL_EN="PM1"
 CONFIG_VIDEO_LCD_BL_PWM="PH13"
 CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_AXP_GPIO=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_SYS_I2C_MVTWSI=y
 CONFIG_SYS_I2C_SLAVE=0x7f
@@ -24,6 +23,7 @@ CONFIG_ETH_DESIGNWARE=y
 CONFIG_RGMII=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_AXP_ALDO1_VOLT=3300
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y

configs/Cubieboard2_defconfig

@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-cubieboard2"
 CONFIG_SPL=y
 CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=480
-CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_SATAPWR="PB8"
 CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
@@ -18,6 +17,7 @@ CONFIG_PHY_REALTEK=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_SCSI=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y

configs/Cubieboard4_defconfig

@@ -4,13 +4,11 @@ CONFIG_DEFAULT_DEVICE_TREE="sun9i-a80-cubieboard4"
 CONFIG_SPL=y
 CONFIG_MACH_SUN9I=y
 CONFIG_DRAM_CLK=672
-CONFIG_MMC0_CD_PIN="PH18"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
-CONFIG_USB0_ID_DET="PH16"
-CONFIG_USB1_VBUS_PIN="PH14"
-CONFIG_USB3_VBUS_PIN="PH15"
 CONFIG_AXP_GPIO=y
 CONFIG_SYS_I2C_SUN8I_RSB=y
+CONFIG_DM_REGULATOR=y
+CONFIG_REGULATOR_AXP=y
+CONFIG_REGULATOR_AXP_USB_POWER=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_AXP809_POWER=y

configs/Cubieboard_defconfig

@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-cubieboard"
 CONFIG_SPL=y
 CONFIG_MACH_SUN4I=y
 CONFIG_DRAM_CLK=480
-CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_SATAPWR="PB8"
 CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
@@ -16,6 +15,7 @@ CONFIG_SYS_I2C_SLAVE=0x7f
 CONFIG_SYS_I2C_SPEED=400000
 CONFIG_MII=y
 CONFIG_SUN4I_EMAC=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_SCSI=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y

configs/Cubietruck_defconfig

@@ -4,10 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-cubietruck"
 CONFIG_SPL=y
 CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=432
-CONFIG_MMC0_CD_PIN="PH1"
-CONFIG_USB0_VBUS_PIN="PH17"
-CONFIG_USB0_VBUS_DET="PH22"
-CONFIG_USB0_ID_DET="PH19"
 CONFIG_VIDEO_VGA=y
 CONFIG_SATAPWR="PH12"
 CONFIG_GMAC_TX_DELAY=1
@@ -28,6 +24,7 @@ CONFIG_ETH_DESIGNWARE=y
 CONFIG_RGMII=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_SCSI=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y

configs/Cubietruck_plus_defconfig

@@ -7,21 +7,19 @@ CONFIG_DRAM_CLK=672
 CONFIG_DRAM_ZQ=15355
 CONFIG_DRAM_ODT_EN=y
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
-CONFIG_USB0_ID_DET="PH11"
-CONFIG_USB1_VBUS_PIN="PD29"
-CONFIG_USB2_VBUS_PIN="PL6"
 CONFIG_I2C0_ENABLE=y
-CONFIG_AXP_GPIO=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_CONSOLE_MUX=y
+CONFIG_AXP_GPIO=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_SYS_I2C_MVTWSI=y
 CONFIG_SYS_I2C_SLAVE=0x7f
 CONFIG_SYS_I2C_SPEED=400000
 CONFIG_PHY_REALTEK=y
 CONFIG_SUN8I_EMAC=y
+CONFIG_REGULATOR_AXP=y
+CONFIG_REGULATOR_AXP_USB_POWER=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_AXP_DLDO3_VOLT=2500
 CONFIG_AXP_DLDO4_VOLT=3300
 CONFIG_AXP_FLDO1_VOLT=1200

configs/Empire_electronix_d709_defconfig

@@ -5,11 +5,6 @@ CONFIG_SPL=y
 CONFIG_MACH_SUN5I=y
 CONFIG_DRAM_CLK=432
 CONFIG_DRAM_EMR1=0
-CONFIG_MMC0_CD_PIN="PG0"
-CONFIG_USB0_VBUS_PIN="PG12"
-CONFIG_USB0_VBUS_DET="PG1"
-CONFIG_USB0_ID_DET="PG2"
-CONFIG_AXP_GPIO=y
 # CONFIG_VIDEO_HDMI is not set
 CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:45,ri:210,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0"
 CONFIG_VIDEO_LCD_POWER="AXP0-0"
@@ -17,8 +12,10 @@ CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
 CONFIG_VIDEO_LCD_BL_PWM="PB2"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_I2C=y
+CONFIG_AXP_GPIO=y
 CONFIG_SYS_I2C_MVTWSI=y
 CONFIG_SYS_I2C_SLAVE=0x7f
 CONFIG_SYS_I2C_SPEED=400000
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_CONS_INDEX=2
 CONFIG_USB_MUSB_HOST=y

configs/Empire_electronix_m712_defconfig

@@ -4,11 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-empire-electronix-m712"
 CONFIG_SPL=y
 CONFIG_MACH_SUN5I=y
 CONFIG_DRAM_CLK=408
-CONFIG_MMC0_CD_PIN="PG0"
-CONFIG_USB0_VBUS_PIN="PG12"
-CONFIG_USB0_VBUS_DET="PG1"
-CONFIG_USB0_ID_DET="PG2"
-CONFIG_AXP_GPIO=y
 # CONFIG_VIDEO_HDMI is not set
 CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:45,ri:82,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0"
 CONFIG_VIDEO_LCD_POWER="AXP0-0"
@@ -16,8 +11,10 @@ CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
 CONFIG_VIDEO_LCD_BL_PWM="PB2"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_I2C=y
+CONFIG_AXP_GPIO=y
 CONFIG_SYS_I2C_MVTWSI=y
 CONFIG_SYS_I2C_SLAVE=0x7f
 CONFIG_SYS_I2C_SPEED=400000
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_CONS_INDEX=2
 CONFIG_USB_MUSB_HOST=y

configs/Hummingbird_A31_defconfig

@@ -4,8 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-hummingbird"
 CONFIG_SPL=y
 CONFIG_MACH_SUN6I=y
 CONFIG_DRAM_ZQ=251
-CONFIG_USB1_VBUS_PIN="PH24"
-CONFIG_USB2_VBUS_PIN=""
 CONFIG_VIDEO_VGA_VIA_LCD=y
 CONFIG_VIDEO_VGA_EXTERNAL_DAC_EN="PH25"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
@@ -14,6 +12,7 @@ CONFIG_ETH_DESIGNWARE=y
 CONFIG_RGMII=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_AXP_ALDO1_VOLT=3300
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y

configs/Hyundai_A7HD_defconfig

@@ -4,10 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-hyundai-a7hd"
 CONFIG_SPL=y
 CONFIG_MACH_SUN4I=y
 CONFIG_DRAM_EMR1=4
-CONFIG_USB0_VBUS_PIN="PB09"
-CONFIG_USB0_VBUS_DET="PH5"
-CONFIG_USB1_VBUS_PIN=""
-CONFIG_USB2_VBUS_PIN="PH6"
 CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:51000,le:45,ri:274,up:22,lo:12,hs:1,vs:1,sync:3,vmode:0"
 CONFIG_VIDEO_LCD_POWER="PH2"
 CONFIG_VIDEO_LCD_BL_EN="PH9"
@@ -19,4 +15,5 @@ CONFIG_SPL_I2C=y
 CONFIG_SYS_I2C_MVTWSI=y
 CONFIG_SYS_I2C_SLAVE=0x7f
 CONFIG_SYS_I2C_SPEED=400000
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_USB_MUSB_HOST=y

configs/Itead_Ibox_A20_defconfig

@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-itead-ibox"
 CONFIG_SPL=y
 CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=480
-CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_SATAPWR="PB8"
 CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
@@ -18,6 +17,7 @@ CONFIG_PHY_REALTEK=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_SCSI=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y

configs/Lamobo_R1_defconfig

@@ -5,7 +5,6 @@ CONFIG_SPL=y
 CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=432
 CONFIG_MACPWR="PH23"
-CONFIG_MMC0_CD_PIN="PH10"
 CONFIG_SATAPWR="PB3"
 CONFIG_GMAC_TX_DELAY=4
 CONFIG_AHCI=y
@@ -23,6 +22,7 @@ CONFIG_ETH_DESIGNWARE=y
 CONFIG_RGMII=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_SCSI=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y

configs/Linksprite_pcDuino3_Nano_defconfig

@@ -5,7 +5,6 @@ CONFIG_SPL=y
 CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=408
 CONFIG_DRAM_ZQ=122
-CONFIG_USB1_VBUS_PIN="PH11"
 CONFIG_SATAPWR="PH2"
 CONFIG_GMAC_TX_DELAY=3
 CONFIG_AHCI=y
@@ -21,6 +20,7 @@ CONFIG_ETH_DESIGNWARE=y
 CONFIG_RGMII=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_SCSI=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y

configs/Linksprite_pcDuino3_defconfig

@@ -18,6 +18,7 @@ CONFIG_PHY_REALTEK=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_SCSI=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y

configs/Linksprite_pcDuino_defconfig

@@ -3,8 +3,6 @@ CONFIG_ARCH_SUNXI=y
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-pcduino"
 CONFIG_SPL=y
 CONFIG_MACH_SUN4I=y
-CONFIG_USB1_VBUS_PIN=""
-CONFIG_USB2_VBUS_PIN=""
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_I2C=y
 CONFIG_SYS_I2C_MVTWSI=y
@@ -12,5 +10,6 @@ CONFIG_SYS_I2C_SLAVE=0x7f
 CONFIG_SYS_I2C_SPEED=400000
 CONFIG_MII=y
 CONFIG_SUN4I_EMAC=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y

configs/MK808C_defconfig

@@ -9,5 +9,6 @@ CONFIG_SPL_I2C=y
 CONFIG_SYS_I2C_MVTWSI=y
 CONFIG_SYS_I2C_SLAVE=0x7f
 CONFIG_SYS_I2C_SPEED=400000
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y

configs/MSI_Primo73_defconfig

@@ -14,3 +14,4 @@ CONFIG_SPL_I2C=y
 CONFIG_SYS_I2C_MVTWSI=y
 CONFIG_SYS_I2C_SLAVE=0x7f
 CONFIG_SYS_I2C_SPEED=400000
+CONFIG_DM_REGULATOR_FIXED=y

configs/MSI_Primo81_defconfig

@@ -5,14 +5,15 @@ CONFIG_SPL=y
 CONFIG_MACH_SUN6I=y
 CONFIG_DRAM_CLK=360
 CONFIG_DRAM_ZQ=122
-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
-CONFIG_AXP_GPIO=y
 CONFIG_VIDEO_LCD_MODE="x:768,y:1024,depth:18,pclk_khz:66000,le:56,ri:60,up:30,lo:36,hs:64,vs:50,sync:3,vmode:0"
 CONFIG_VIDEO_LCD_BL_EN="PA25"
 CONFIG_VIDEO_LCD_BL_PWM="PH13"
 CONFIG_VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_AXP_GPIO=y
+CONFIG_REGULATOR_AXP=y
+CONFIG_REGULATOR_AXP_USB_POWER=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_AXP_DLDO1_VOLT=3300
 # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
 CONFIG_USB_MUSB_HOST=y

configs/Marsboard_A10_defconfig

@@ -12,6 +12,7 @@ CONFIG_SYS_I2C_SLAVE=0x7f
 CONFIG_SYS_I2C_SPEED=400000
 CONFIG_MII=y
 CONFIG_SUN4I_EMAC=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_SUNXI_NO_PMIC=y
 CONFIG_SCSI=y
 CONFIG_USB_EHCI_HCD=y

configs/Mele_A1000G_quad_defconfig

@@ -4,14 +4,13 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-mele-a1000g-quad"
 CONFIG_SPL=y
 CONFIG_MACH_SUN6I=y
 CONFIG_DRAM_ZQ=120
-CONFIG_USB1_VBUS_PIN="PC27"
-CONFIG_USB2_VBUS_PIN=""
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_PHY_REALTEK=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
 CONFIG_INITIAL_USB_SCAN_DELAY=2000
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_AXP_DCDC1_VOLT=3300
 CONFIG_AXP_ALDO1_VOLT=3300
 CONFIG_AXP_DLDO1_VOLT=3300

configs/Mele_A1000_defconfig

@@ -16,6 +16,7 @@ CONFIG_SYS_I2C_SLAVE=0x7f
 CONFIG_SYS_I2C_SPEED=400000
 CONFIG_MII=y
 CONFIG_SUN4I_EMAC=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_SCSI=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y

configs/Mele_I7_defconfig

@@ -4,13 +4,12 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-i7"
 CONFIG_SPL=y
 CONFIG_MACH_SUN6I=y
 CONFIG_DRAM_ZQ=120
-CONFIG_USB1_VBUS_PIN="PC27"
-CONFIG_USB2_VBUS_PIN=""
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_PHY_REALTEK=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_AXP_DCDC1_VOLT=3300
 CONFIG_AXP_ALDO1_VOLT=3300
 CONFIG_AXP_DLDO1_VOLT=3300

configs/Mele_M3_defconfig

@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-m3"
 CONFIG_SPL=y
 CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=384
-CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
 CONFIG_VIDEO_VGA=y
 CONFIG_VIDEO_COMPOSITE=y
@@ -17,5 +16,6 @@ CONFIG_PHY_REALTEK=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y

configs/Mele_M5_defconfig

@@ -5,7 +5,6 @@ CONFIG_SPL=y
 CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=432
 CONFIG_DRAM_ZQ=122
-CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_VIDEO_COMPOSITE=y
 CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
@@ -19,6 +18,7 @@ CONFIG_PHY_REALTEK=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_SCSI=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y

configs/Mele_M9_defconfig

@@ -4,13 +4,12 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-m9"
 CONFIG_SPL=y
 CONFIG_MACH_SUN6I=y
 CONFIG_DRAM_ZQ=120
-CONFIG_USB1_VBUS_PIN="PC27"
-CONFIG_USB2_VBUS_PIN=""
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_PHY_REALTEK=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_AXP_DCDC1_VOLT=3300
 CONFIG_AXP_ALDO1_VOLT=3300
 CONFIG_AXP_DLDO1_VOLT=3300

configs/Merrii_A80_Optimus_defconfig

@@ -4,13 +4,11 @@ CONFIG_DEFAULT_DEVICE_TREE="sun9i-a80-optimus"
 CONFIG_SPL=y
 CONFIG_MACH_SUN9I=y
 CONFIG_DRAM_CLK=672
-CONFIG_MMC0_CD_PIN="PH18"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
-CONFIG_USB0_ID_DET="PH3"
-CONFIG_USB1_VBUS_PIN="PH4"
-CONFIG_USB3_VBUS_PIN="PH5"
 CONFIG_AXP_GPIO=y
 CONFIG_SYS_I2C_SUN8I_RSB=y
+CONFIG_DM_REGULATOR=y
+CONFIG_REGULATOR_AXP=y
+CONFIG_REGULATOR_AXP_USB_POWER=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_AXP809_POWER=y

configs/Mini-X_defconfig

@@ -3,13 +3,13 @@ CONFIG_ARCH_SUNXI=y
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mini-xplus"
 CONFIG_SPL=y
 CONFIG_MACH_SUN4I=y
-CONFIG_USB0_VBUS_PIN="PB9"
 CONFIG_VIDEO_COMPOSITE=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_I2C=y
 CONFIG_SYS_I2C_MVTWSI=y
 CONFIG_SYS_I2C_SLAVE=0x7f
 CONFIG_SYS_I2C_SPEED=400000
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y

configs/Nintendo_NES_Classic_Edition_defconfig

@@ -6,11 +6,10 @@ CONFIG_MACH_SUN8I_A33=y
 CONFIG_DRAM_CLK=600
 CONFIG_DRAM_ZQ=15291
 CONFIG_DRAM_ODT_EN=y
-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
-CONFIG_AXP_GPIO=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_MTDPARTS=y
+CONFIG_AXP_GPIO=y
 # CONFIG_MMC is not set
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
@@ -18,6 +17,7 @@ CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
 CONFIG_SYS_NAND_ONFI_DETECTION=y
 CONFIG_SYS_NAND_PAGE_SIZE=0x800
 CONFIG_SYS_NAND_OOBSIZE=0x40
+CONFIG_REGULATOR_AXP_USB_POWER=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_AXP_ELDO2_VOLT=1800
 CONFIG_CONS_INDEX=5

configs/Orangepi_defconfig

@@ -5,8 +5,6 @@ CONFIG_SPL=y
 CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=432
 CONFIG_MACPWR="PH23"
-CONFIG_USB1_VBUS_PIN="PH26"
-CONFIG_USB2_VBUS_PIN="PH22"
 CONFIG_VIDEO_VGA=y
 CONFIG_VIDEO_COMPOSITE=y
 CONFIG_GMAC_TX_DELAY=3
@@ -23,6 +21,7 @@ CONFIG_ETH_DESIGNWARE=y
 CONFIG_RGMII=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_SCSI=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y

configs/Orangepi_mini_defconfig

@@ -5,11 +5,7 @@ CONFIG_SPL=y
 CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=432
 CONFIG_MACPWR="PH23"
-CONFIG_MMC0_CD_PIN="PH10"
-CONFIG_MMC3_CD_PIN="PH11"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=3
-CONFIG_USB1_VBUS_PIN="PH26"
-CONFIG_USB2_VBUS_PIN="PH22"
 CONFIG_VIDEO_COMPOSITE=y
 CONFIG_GMAC_TX_DELAY=3
 CONFIG_AHCI=y
@@ -25,6 +21,7 @@ CONFIG_ETH_DESIGNWARE=y
 CONFIG_RGMII=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_SCSI=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y

configs/Sinlinx_SinA31s_defconfig

@@ -5,15 +5,13 @@ CONFIG_SPL=y
 CONFIG_MACH_SUN6I=y
 CONFIG_DRAM_CLK=432
 CONFIG_DRAM_ZQ=251
-CONFIG_MMC0_CD_PIN="PA4"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=3
-CONFIG_USB1_VBUS_PIN=""
-CONFIG_USB2_VBUS_PIN=""
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_PHY_REALTEK=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y

configs/Sinlinx_SinA33_defconfig

@@ -5,9 +5,7 @@ CONFIG_SPL=y
 CONFIG_MACH_SUN8I_A33=y
 CONFIG_DRAM_CLK=552
 CONFIG_DRAM_ZQ=15291
-CONFIG_MMC0_CD_PIN="PB4"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-CONFIG_USB0_ID_DET="PH8"
 CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:66000,le:90,ri:160,up:3,lo:127,hs:70,vs:20,sync:3,vmode:0"
 CONFIG_VIDEO_LCD_DCLK_PHASE=0
 CONFIG_VIDEO_LCD_BL_EN="PH6"

configs/Sinovoip_BPI_M2_defconfig

@@ -4,14 +4,13 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-sinovoip-bpi-m2"
 CONFIG_SPL=y
 CONFIG_MACH_SUN6I=y
 CONFIG_DRAM_CLK=432
-CONFIG_USB1_VBUS_PIN=""
-CONFIG_USB2_VBUS_PIN=""
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_PHY_REALTEK=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_RGMII=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_AXP_ALDO1_VOLT=3300
 CONFIG_AXP_ALDO2_VOLT=1800
 CONFIG_AXP_DLDO1_VOLT=3000

configs/Sinovoip_BPI_M3_defconfig

@@ -8,17 +8,16 @@ CONFIG_DRAM_CLK=480
 CONFIG_DRAM_ZQ=15355
 CONFIG_DRAM_ODT_EN=y
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
-CONFIG_USB0_ID_DET="PH11"
-CONFIG_USB1_VBUS_PIN="PD24"
-CONFIG_AXP_GPIO=y
 CONFIG_SATAPWR="PD25"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_CONSOLE_MUX=y
+CONFIG_AXP_GPIO=y
 CONFIG_PHY_REALTEK=y
 CONFIG_SUN8I_EMAC=y
 CONFIG_INITIAL_USB_SCAN_DELAY=500
+CONFIG_REGULATOR_AXP=y
+CONFIG_REGULATOR_AXP_USB_POWER=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_AXP_DCDC5_VOLT=1200
 CONFIG_AXP_DLDO3_VOLT=3300
 CONFIG_AXP_SW_ON=y

configs/Sunchip_CX-A99_defconfig

@@ -6,9 +6,7 @@ CONFIG_MACH_SUN9I=y
 CONFIG_DRAM_CLK=600
 CONFIG_DRAM_ZQ=3881915
 CONFIG_DRAM_ODT_EN=y
-CONFIG_MMC0_CD_PIN="PH17"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-CONFIG_USB0_VBUS_PIN="PH15"
-CONFIG_USB1_VBUS_PIN="PL7"
-CONFIG_USB3_VBUS_PIN="PL8"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y

configs/UTOO_P66_defconfig

@@ -5,12 +5,7 @@ CONFIG_SPL=y
 CONFIG_MACH_SUN5I=y
 CONFIG_DRAM_CLK=432
 CONFIG_DRAM_EMR1=0
-CONFIG_MMC0_CD_PIN="PG0"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-CONFIG_USB0_VBUS_PIN="PB04"
-CONFIG_USB0_VBUS_DET="PG01"
-CONFIG_USB0_ID_DET="PG2"
-CONFIG_AXP_GPIO=y
 # CONFIG_VIDEO_HDMI is not set
 CONFIG_VIDEO_LCD_MODE="x:480,y:800,depth:18,pclk_khz:25000,le:2,ri:93,up:2,lo:93,hs:1,vs:1,sync:3,vmode:0"
 CONFIG_VIDEO_LCD_DCLK_PHASE=0
@@ -21,9 +16,11 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2"
 CONFIG_VIDEO_LCD_TL059WV5C0=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_I2C=y
+CONFIG_AXP_GPIO=y
 CONFIG_SYS_I2C_MVTWSI=y
 CONFIG_SYS_I2C_SLAVE=0x7f
 CONFIG_SYS_I2C_SPEED=400000
+CONFIG_DM_REGULATOR_FIXED=y
 # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
 CONFIG_CONS_INDEX=2
 CONFIG_USB_MUSB_HOST=y

configs/Wexler_TAB7200_defconfig

@@ -4,19 +4,18 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-wexler-tab7200"
 CONFIG_SPL=y
 CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=384
-CONFIG_USB0_VBUS_PIN="PB9"
-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
-CONFIG_USB0_ID_DET="PH4"
-CONFIG_AXP_GPIO=y
 CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:24,pclk_khz:33000,le:45,ri:210,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0"
 CONFIG_VIDEO_LCD_POWER="PH8"
 CONFIG_VIDEO_LCD_BL_EN="PH7"
 CONFIG_VIDEO_LCD_BL_PWM="PB2"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_I2C=y
+CONFIG_AXP_GPIO=y
 CONFIG_SYS_I2C_MVTWSI=y
 CONFIG_SYS_I2C_SLAVE=0x7f
 CONFIG_SYS_I2C_SPEED=400000
+CONFIG_REGULATOR_AXP_USB_POWER=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y

configs/Wits_Pro_A20_DKT_defconfig

@@ -23,6 +23,7 @@ CONFIG_ETH_DESIGNWARE=y
 CONFIG_RGMII=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_SCSI=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y

configs/Wobo_i5_defconfig

@@ -4,13 +4,12 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-wobo-i5"
 CONFIG_SPL=y
 CONFIG_MACH_SUN5I=y
 CONFIG_DRAM_CLK=432
-CONFIG_MMC0_CD_PIN="PB3"
-CONFIG_USB1_VBUS_PIN="PG12"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_I2C=y
 CONFIG_SYS_I2C_MVTWSI=y
 CONFIG_SYS_I2C_SLAVE=0x7f
 CONFIG_SYS_I2C_SPEED=400000
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_AXP_ALDO3_VOLT=3300
 CONFIG_AXP_ALDO4_VOLT=3300
 CONFIG_CONS_INDEX=2

configs/Yones_Toptech_BD1078_defconfig

@@ -4,13 +4,8 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-yones-toptech-bd1078"
 CONFIG_SPL=y
 CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=408
-CONFIG_MMC0_CD_PIN="PH1"
-CONFIG_MMC1_CD_PIN="PH2"
 CONFIG_MMC1_PINS_PH=y
 CONFIG_MMC_SUNXI_SLOT_EXTRA=1
-CONFIG_USB0_VBUS_PIN="PB9"
-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
-CONFIG_AXP_GPIO=y
 CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:24,pclk_khz:63000,le:32,ri:287,up:22,lo:12,hs:1,vs:1,sync:3,vmode:0"
 CONFIG_VIDEO_LCD_DCLK_PHASE=0
 CONFIG_VIDEO_LCD_POWER="PH8"
@@ -20,7 +15,10 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2"
 CONFIG_VIDEO_LCD_PANEL_LVDS=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_I2C=y
+CONFIG_AXP_GPIO=y
 CONFIG_SYS_I2C_MVTWSI=y
 CONFIG_SYS_I2C_SLAVE=0x7f
 CONFIG_SYS_I2C_SPEED=400000
+CONFIG_REGULATOR_AXP_USB_POWER=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_USB_MUSB_HOST=y

configs/Yones_Toptech_BS1078_V2_defconfig

@@ -5,16 +5,15 @@ CONFIG_SPL=y
 CONFIG_MACH_SUN6I=y
 CONFIG_DRAM_CLK=420
 CONFIG_DRAM_ZQ=251
-CONFIG_MMC0_CD_PIN="PA8"
-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
-CONFIG_USB0_ID_DET="PA15"
-CONFIG_AXP_GPIO=y
 CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:24,pclk_khz:70000,le:120,ri:180,up:17,lo:15,hs:20,vs:3,sync:3,vmode:0"
 CONFIG_VIDEO_LCD_DCLK_PHASE=0
 CONFIG_VIDEO_LCD_BL_EN="PA25"
 CONFIG_VIDEO_LCD_BL_PWM="PH13"
 CONFIG_VIDEO_LCD_PANEL_LVDS=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_AXP_GPIO=y
+CONFIG_REGULATOR_AXP=y
+CONFIG_REGULATOR_AXP_USB_POWER=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_USB_MUSB_HOST=y

configs/arbel_evb_defconfig

@@ -60,6 +60,5 @@ CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_OHCI_GENERIC=y
-CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1
 CONFIG_USB_STORAGE=y
 # CONFIG_EFI_LOADER is not set