/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */

#ifndef _DT_BINDINGS_CLOCK_BL808_GLB_H_
#define _DT_BINDINGS_CLOCK_BL808_GLB_H_

#define CLK_CPU			0
#define CLK_FCLK		1
#define CLK_HCLK		2
#define CLK_BCLK		3
#define CLK_PICO		4
#define CLK_EMI			5
#define CLK_CPU_RTC		6
#define CLK_DMA			7
#define CLK_DMA2		8
#define CLK_IR			9
#define CLK_UART		10
#define CLK_SF			11
#define CLK_I2C			12
#define CLK_I2S_REF		13
#define CLK_I2S_DI_REF		14
#define CLK_I2S_DO_REF		15
#define CLK_SPI			16
#define CLK_DIG_32K		17
#define CLK_DIG_512K		18
#define CLK_DIG			19
#define CLK_DSPPLL		20
#define CLK_MM_MUXPLL_160M	22
#define CLK_MM_MUXPLL_240M	23
#define CLK_MM_MUXPLL_320M	24
#define CLK_TOP_MUXPLL_80M	25
#define CLK_TOP_MUXPLL_160M	26
#define CLK_OUT0		27
#define CLK_OUT1		28
#define CLK_OUT2		29
#define CLK_OUT3		30
#define CLK_GPIO_TMR		31
#define CLK_GPIO_MM_TMR		32
#define CLK_DSI_TXCLKESC	33
#define CLK_CSI_TXCLKESC	34
#define CLK_RF2_TEST		35
#define CLK_AUDIO_PDM		36
#define CLK_AUDIO_ADC		37
#define CLK_AUDIO_DAC		38
#define CLK_PADC		39
#define CLK_ETH_REF		40
#define CLK_ETH_TX		41
#define CLK_ETH_RX		42
#define CLK_CAM_REF		43
#define CLK_SDH			44
#define CLK_PKA			45
#define CLK_MM_WIFIPLL_160M	46
#define CLK_MM_WIFIPLL_240M	47
#define CLK_MM_WIFIPLL_320M	48
#define CLK_MM_AUPLL_DIV1	49
#define CLK_MM_AUPLL_DIV2	50
#define CLK_EMI_CPUPLL_400M	51
#define CLK_EMI_CPUPLL_200M	52
#define CLK_EMI_WIFIPLL_320M	53
#define CLK_EMI_AUPLL_DIV1	54
#define CLK_TOP_CPUPLL_80M	55
#define CLK_TOP_CPUPLL_100M	56
#define CLK_TOP_CPUPLL_160M	57
#define CLK_TOP_CPUPLL_400M	58
#define CLK_TOP_WIFIPLL_240M	59
#define CLK_TOP_WIFIPLL_320M	60
#define CLK_TOP_AUPLL_DIV2	61
#define CLK_TOP_AUPLL_DIV1	62
#define CLK_PSRAMB		63
#define CLK_MIPIPLL		64
#define CLK_MIPIPLL_POSTDIV	65
#define CLK_UHSPLL		66
#define CLK_UHSPLL_POSTDIV	67
#define CLK_WIFIPLL		68
#define CLK_WIFIPLL_POSTDIV	69
#define CLK_WIFIPLL_DIV2	70
#define CLK_WIFIPLL_DIV4	71
#define CLK_WIFIPLL_DIV5	72
#define CLK_WIFIPLL_DIV6	73
#define CLK_WIFIPLL_DIV8	74
#define CLK_WIFIPLL_DIV10	75
#define CLK_WIFIPLL_DIV12	76
#define CLK_WIFIPLL_DIV20	77
#define CLK_WIFIPLL_DIV30	78
#define CLK_USBPLL		79
#define CLK_BUS_USB		80
#define CLK_BUS_SDH		82
#define CLK_BUS_EMAC		82

#endif /* _DT_BINDINGS_CLOCK_BL808_GLB_H_ */