// SPDX-License-Identifier: (GPL-2.0+ or MIT)
// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#define SOC_PERIPHERAL_IRQ(nr)	GIC_SPI nr

#include "../../riscv/dts/sunxi-d1s-t113.dtsi"
#include "../../riscv/dts/sunxi-d1-t113.dtsi"

/ {
	interrupt-parent = <&gic>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0>;
			clocks = <&ccu CLK_CPUX>;
			#cooling-cells = <2>;
		};

		cpu1: cpu@1 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <1>;
			clocks = <&ccu CLK_CPUX>;
			#cooling-cells = <2>;
		};
	};

	pmu {
		compatible = "arm,cortex-a7-pmu";
		interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&cpu0>, <&cpu1>;
	};

	soc {
		gic: interrupt-controller@3021000 {
			compatible = "arm,gic-400";
			reg = <0x3021000 0x1000>,
			      <0x3022000 0x2000>,
			      <0x3024000 0x2000>,
			      <0x3026000 0x2000>;
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
			interrupt-controller;
			#interrupt-cells = <3>;
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
		arm,no-tick-in-suspend;
	};
};