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6bde55b05b
Implement the operations to get pin and function names, and to set the
mux for a pin. The pin count and pin names are calculated as if each
bank has the maximum number of pins. Function names are simply the index
into a list of { function name, mux value } pairs.
We assume all pins associated with a function use the same mux value for
that function. This is generally true within a group of pins on a single
port, but generally false when some peripheral can be muxed to multiple
ports. For example, A64 UART3 uses mux 3 on port D, and mux 2 on port H.
But all of the port D pins use the same mux value, and so do all of the
port H pins. This applies even when the pins for some function are not
contiguous, and when the lower-numbered mux values are unused. A good
example of both of these cases is SPI0 on most SoCs.
This strategy saves a lot of space (which is especially important for
SPL), but where the mux value for a certain function differs across
ports, it forces us to choose a single port for that function at build
time. Since almost all boards use the default (i.e. reference design)
pin muxes[1], this is unlikely to be a problem.
[1]: See commit dda9fa734f81 ("sunxi: Simplify MMC pinmux selection")
Signed-off-by: Samuel Holland <samuel@sholland.org>
22 lines
430 B
C
22 lines
430 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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struct sunxi_pinctrl_function {
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const char name[sizeof("gpio_out")];
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u8 mux;
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};
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struct sunxi_pinctrl_desc {
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const struct sunxi_pinctrl_function *functions;
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u8 num_functions;
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u8 first_bank;
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u8 num_banks;
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};
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struct sunxi_pinctrl_plat {
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struct sunxi_gpio __iomem *base;
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};
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extern const struct pinctrl_ops sunxi_pinctrl_ops;
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int sunxi_pinctrl_bind(struct udevice *dev);
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