mirror of
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456 lines
10 KiB
C
456 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
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* Copyright (C) 2018-2021 Samuel Holland <samuel@sholland.org>
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*/
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#include <common.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/cpucfg.h>
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#include <asm/armv7.h>
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#include <asm/gic.h>
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#include <asm/io.h>
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#include <asm/psci.h>
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#include <asm/secure.h>
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#include <asm/system.h>
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#define GICD_BASE (SUNXI_GIC400_BASE + GIC_DIST_OFFSET)
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#define GICC_BASE (SUNXI_GIC400_BASE + GIC_CPU_OFFSET_A15)
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#define HW_ON 0
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#define HW_OFF 1
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#define HW_STANDBY 2
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#define MPIDR_AFFLVL0(mpidr) (mpidr & 0xf)
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#define MPIDR_AFFLVL1(mpidr) (mpidr >> 8 & 0xf)
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#if defined(CONFIG_MACH_SUN8I_H3)
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#define SCPI_SHMEM_BASE 0x0004be00
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#else
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#define SCPI_SHMEM_BASE 0x00053e00
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#endif
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#define SCPI_SHMEM ((struct scpi_shmem *)SCPI_SHMEM_BASE)
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#define SCPI_RX_CHANNEL 1
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#define SCPI_TX_CHANNEL 0
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#define SCPI_VIRTUAL_CHANNEL BIT(0)
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#define SCPI_MESSAGE_SIZE 0x100
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#define SCPI_PAYLOAD_SIZE (SCPI_MESSAGE_SIZE - sizeof(struct scpi_header))
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#define SUNXI_MSGBOX_BASE 0x01c17000
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#define REMOTE_IRQ_STAT_REG (SUNXI_MSGBOX_BASE + 0x0050)
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#define LOCAL_IRQ_STAT_REG (SUNXI_MSGBOX_BASE + 0x0070)
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#define MSG_STAT_REG(n) (SUNXI_MSGBOX_BASE + 0x0140 + 0x4 * (n))
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#define MSG_DATA_REG(n) (SUNXI_MSGBOX_BASE + 0x0180 + 0x4 * (n))
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#define RX_IRQ(n) BIT(0 + 2 * (n))
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#define TX_IRQ(n) BIT(1 + 2 * (n))
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enum {
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CORE_POWER_LEVEL = 0,
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CLUSTER_POWER_LEVEL = 1,
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CSS_POWER_LEVEL = 2,
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};
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enum {
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SCPI_CMD_SCP_READY = 0x01,
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SCPI_CMD_SET_CSS_POWER_STATE = 0x03,
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SCPI_CMD_GET_CSS_POWER_STATE = 0x04,
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SCPI_CMD_SET_SYS_POWER_STATE = 0x05,
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};
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enum {
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SCPI_E_OK = 0,
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SCPI_E_PARAM = 1,
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SCPI_E_ALIGN = 2,
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SCPI_E_SIZE = 3,
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SCPI_E_HANDLER = 4,
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SCPI_E_ACCESS = 5,
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SCPI_E_RANGE = 6,
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SCPI_E_TIMEOUT = 7,
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SCPI_E_NOMEM = 8,
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SCPI_E_PWRSTATE = 9,
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SCPI_E_SUPPORT = 10,
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SCPI_E_DEVICE = 11,
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SCPI_E_BUSY = 12,
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SCPI_E_OS = 13,
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SCPI_E_DATA = 14,
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SCPI_E_STATE = 15,
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};
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enum {
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SCPI_POWER_ON = 0x00,
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SCPI_POWER_RETENTION = 0x01,
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SCPI_POWER_OFF = 0x03,
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};
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enum {
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SCPI_SYSTEM_SHUTDOWN = 0x00,
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SCPI_SYSTEM_REBOOT = 0x01,
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SCPI_SYSTEM_RESET = 0x02,
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};
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struct scpi_header {
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u8 command;
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u8 sender;
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u16 size;
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u32 status;
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};
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struct scpi_message {
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struct scpi_header header;
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u8 payload[SCPI_PAYLOAD_SIZE];
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};
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struct scpi_shmem {
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struct scpi_message rx;
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struct scpi_message tx;
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};
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static bool __secure_data gic_dist_init;
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static u32 __secure_data lock;
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static inline u32 __secure read_mpidr(void)
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{
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u32 val;
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asm volatile ("mrc p15, 0, %0, c0, c0, 5" : "=r" (val));
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return val;
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}
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static void __secure scpi_begin_command(void)
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{
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u32 mpidr = read_mpidr();
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do {
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while (readl(&lock));
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writel(mpidr, &lock);
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dsb();
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} while (readl(&lock) != mpidr);
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while (readl(REMOTE_IRQ_STAT_REG) & RX_IRQ(SCPI_TX_CHANNEL));
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}
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static void __secure scpi_send_command(void)
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{
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writel(SCPI_VIRTUAL_CHANNEL, MSG_DATA_REG(SCPI_TX_CHANNEL));
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}
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static void __secure scpi_wait_response(void)
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{
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while (!readl(MSG_STAT_REG(SCPI_RX_CHANNEL)));
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}
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static void __secure scpi_end_command(void)
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{
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while (readl(MSG_STAT_REG(SCPI_RX_CHANNEL)))
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readl(MSG_DATA_REG(SCPI_RX_CHANNEL));
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writel(RX_IRQ(SCPI_RX_CHANNEL), LOCAL_IRQ_STAT_REG);
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writel(0, &lock);
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}
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static void __secure scpi_set_css_power_state(u32 target_cpu, u32 core_state,
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u32 cluster_state, u32 css_state)
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{
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struct scpi_shmem *shmem = SCPI_SHMEM;
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scpi_begin_command();
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shmem->tx.header.command = SCPI_CMD_SET_CSS_POWER_STATE;
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shmem->tx.header.size = 4;
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shmem->tx.payload[0] = target_cpu >> 4 | target_cpu;
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shmem->tx.payload[1] = cluster_state << 4 | core_state;
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shmem->tx.payload[2] = css_state;
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shmem->tx.payload[3] = 0;
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scpi_send_command();
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scpi_end_command();
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}
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static s32 __secure scpi_get_css_power_state(u32 target_cpu, u8 *core_states,
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u8 *cluster_state)
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{
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struct scpi_shmem *shmem = SCPI_SHMEM;
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u32 cluster = MPIDR_AFFLVL1(target_cpu);
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u32 offset;
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s32 ret;
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scpi_begin_command();
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shmem->tx.header.command = SCPI_CMD_GET_CSS_POWER_STATE;
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shmem->tx.header.size = 0;
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scpi_send_command();
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scpi_wait_response();
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for (offset = 0; offset < shmem->rx.header.size; offset += 2) {
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if ((shmem->rx.payload[offset] & 0xf) == cluster) {
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*cluster_state = shmem->rx.payload[offset+0] >> 4;
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*core_states = shmem->rx.payload[offset+1];
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break;
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}
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}
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ret = shmem->rx.header.status;
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scpi_end_command();
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return ret;
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}
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static s32 __secure scpi_set_sys_power_state(u32 sys_state)
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{
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struct scpi_shmem *shmem = SCPI_SHMEM;
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s32 ret;
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scpi_begin_command();
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shmem->tx.header.command = SCPI_CMD_SET_SYS_POWER_STATE;
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shmem->tx.header.size = 1;
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shmem->tx.payload[0] = sys_state;
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scpi_send_command();
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scpi_wait_response();
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ret = shmem->rx.header.status;
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scpi_end_command();
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return ret;
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}
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void psci_enable_smp(void);
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static s32 __secure psci_suspend_common(u32 pc, u32 context_id, u32 core_state,
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u32 cluster_state, u32 css_state)
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{
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u32 target_cpu = read_mpidr();
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if (core_state == SCPI_POWER_OFF)
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psci_save(MPIDR_AFFLVL0(target_cpu), pc, context_id);
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if (css_state == SCPI_POWER_OFF)
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gic_dist_init = true;
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scpi_set_css_power_state(target_cpu, core_state,
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cluster_state, css_state);
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psci_cpu_off_common();
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wfi();
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psci_enable_smp();
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return ARM_PSCI_RET_SUCCESS;
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}
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u32 __secure psci_version(void)
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{
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return ARM_PSCI_VER_1_1;
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}
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s32 __secure psci_cpu_suspend(u32 __always_unused function_id,
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u32 power_state, u32 pc, u32 context_id)
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{
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return psci_suspend_common(pc, context_id,
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power_state >> 0 & 0xf,
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power_state >> 4 & 0xf,
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power_state >> 8 & 0xf);
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}
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s32 __secure psci_cpu_off(void)
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{
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u32 pc = 0, context_id = 0;
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return psci_suspend_common(pc, context_id, SCPI_POWER_OFF,
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SCPI_POWER_OFF, SCPI_POWER_ON);
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}
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s32 __secure psci_cpu_on(u32 __always_unused function_id,
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u32 target_cpu, u32 pc, u32 context_id)
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{
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psci_save(MPIDR_AFFLVL0(target_cpu), pc, context_id);
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scpi_set_css_power_state(target_cpu, SCPI_POWER_ON,
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SCPI_POWER_ON, SCPI_POWER_ON);
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return ARM_PSCI_RET_SUCCESS;
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}
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s32 __secure psci_affinity_info(u32 function_id,
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u32 target_cpu, u32 power_level)
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{
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if (power_level != CORE_POWER_LEVEL)
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return ARM_PSCI_RET_INVAL;
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/* This happens to have the same HW_ON/HW_OFF encoding. */
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return psci_node_hw_state(function_id, target_cpu, power_level);
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}
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void __secure psci_system_off(void)
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{
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scpi_set_sys_power_state(SCPI_SYSTEM_SHUTDOWN);
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/* Wait to be turned off. */
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for (;;) wfi();
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}
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void __secure psci_system_reset(void)
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{
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scpi_set_sys_power_state(SCPI_SYSTEM_REBOOT);
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/* Wait to be turned off. */
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for (;;) wfi();
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}
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s32 __secure psci_features(u32 __always_unused function_id,
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u32 psci_fid)
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{
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switch (psci_fid) {
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case ARM_PSCI_0_2_FN_PSCI_VERSION:
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case ARM_PSCI_0_2_FN_CPU_SUSPEND:
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case ARM_PSCI_0_2_FN_CPU_OFF:
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case ARM_PSCI_0_2_FN_CPU_ON:
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case ARM_PSCI_0_2_FN_AFFINITY_INFO:
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case ARM_PSCI_0_2_FN_SYSTEM_OFF:
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case ARM_PSCI_0_2_FN_SYSTEM_RESET:
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case ARM_PSCI_1_0_FN_PSCI_FEATURES:
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case ARM_PSCI_1_0_FN_CPU_DEFAULT_SUSPEND:
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case ARM_PSCI_1_0_FN_NODE_HW_STATE:
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case ARM_PSCI_1_0_FN_SYSTEM_SUSPEND:
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case ARM_PSCI_1_1_FN_SYSTEM_RESET2:
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return ARM_PSCI_RET_SUCCESS;
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default:
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return ARM_PSCI_RET_NI;
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}
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}
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s32 __secure psci_cpu_default_suspend(u32 __always_unused function_id,
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u32 pc, u32 context_id)
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{
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return psci_suspend_common(pc, context_id, SCPI_POWER_OFF,
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SCPI_POWER_OFF, SCPI_POWER_RETENTION);
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}
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s32 __secure psci_node_hw_state(u32 __always_unused function_id,
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u32 target_cpu, u32 power_level)
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{
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u32 core = MPIDR_AFFLVL0(target_cpu);
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u8 core_states, cluster_state;
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if (power_level >= CSS_POWER_LEVEL)
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return HW_ON;
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if (scpi_get_css_power_state(target_cpu, &core_states, &cluster_state))
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return ARM_PSCI_RET_NI;
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if (power_level == CLUSTER_POWER_LEVEL) {
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if (cluster_state == SCPI_POWER_ON)
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return HW_ON;
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if (cluster_state < SCPI_POWER_OFF)
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return HW_STANDBY;
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return HW_OFF;
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}
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return (core_states & BIT(core)) ? HW_ON : HW_OFF;
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}
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s32 __secure psci_system_suspend(u32 __always_unused function_id,
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u32 pc, u32 context_id)
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{
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return psci_suspend_common(pc, context_id, SCPI_POWER_OFF,
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SCPI_POWER_OFF, SCPI_POWER_OFF);
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}
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s32 __secure psci_system_reset2(u32 __always_unused function_id,
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u32 reset_type, u32 cookie)
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{
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s32 ret;
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if (reset_type)
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return ARM_PSCI_RET_INVAL;
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ret = scpi_set_sys_power_state(SCPI_SYSTEM_RESET);
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if (ret)
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return ARM_PSCI_RET_INVAL;
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/* Wait to be turned off. */
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for (;;) wfi();
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}
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/*
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* R40 is different from other single cluster SoCs. The secondary core
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* entry address register is in the SRAM controller address range.
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*/
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#define SUN8I_R40_SRAMC_SOFT_ENTRY_REG0 (0xbc)
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#ifdef CONFIG_MACH_SUN8I_R40
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/* secondary core entry address is programmed differently on R40 */
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static void __secure sunxi_set_entry_address(void *entry)
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{
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writel((u32)entry,
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SUNXI_SRAMC_BASE + SUN8I_R40_SRAMC_SOFT_ENTRY_REG0);
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}
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#else
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static void __secure sunxi_set_entry_address(void *entry)
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{
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struct sunxi_cpucfg_reg *cpucfg =
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(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
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writel((u32)entry, &cpucfg->priv0);
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#ifdef CONFIG_MACH_SUN8I_H3
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/* Redirect CPU 0 to the secure monitor via the resume shim. */
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writel(0x16aaefe8, &cpucfg->super_standy_flag);
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writel(0xaa16efe8, &cpucfg->super_standy_flag);
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writel(SUNXI_RESUME_BASE, &cpucfg->priv1);
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#endif
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}
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#endif
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void __secure psci_arch_init(void)
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{
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static bool __secure_data one_time_init = true;
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if (one_time_init) {
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/* Set secondary core power-on PC. */
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sunxi_set_entry_address(psci_cpu_entry);
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/* Wait for the SCP firmware to boot. */
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scpi_begin_command();
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scpi_wait_response();
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scpi_end_command();
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one_time_init = false;
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}
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/*
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* Copied from arch/arm/cpu/armv7/virt-v7.c
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* See also gic_resume() in arch/arm/mach-imx/mx7/psci-mx7.c
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*/
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if (gic_dist_init) {
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u32 i, itlinesnr;
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/* enable the GIC distributor */
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writel(readl(GICD_BASE + GICD_CTLR) | 0x03, GICD_BASE + GICD_CTLR);
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/* TYPER[4:0] contains an encoded number of available interrupts */
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itlinesnr = readl(GICD_BASE + GICD_TYPER) & 0x1f;
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/* set all bits in the GIC group registers to one to allow access
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* from non-secure state. The first 32 interrupts are private per
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* CPU and will be set later when enabling the GIC for each core
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*/
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for (i = 1; i <= itlinesnr; i++)
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writel((unsigned)-1, GICD_BASE + GICD_IGROUPRn + 4 * i);
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gic_dist_init = false;
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}
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/* Be cool with non-secure. */
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writel(0xff, GICC_BASE + GICC_PMR);
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}
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