mirror of
https://github.com/smaeul/u-boot.git
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3fe7ba6039
Now that the PMIC has a DM driver and binds device tree subnodes, the GPIO device can be bound that way, instead of from inside board code. Since the driver still uses the single set of register definitions from axpXXX.h (as selected by AXPxxx_POWER), it does not differentiate among the supported compatibles. Signed-off-by: Samuel Holland <samuel@sholland.org>
223 lines
5.9 KiB
C
223 lines
5.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2007-2012
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Tom Cubie <tangliang@allwinnertech.com>
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*/
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#ifndef _SUNXI_GPIO_H
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#define _SUNXI_GPIO_H
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#include <linux/types.h>
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#include <asm/arch/cpu.h>
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/*
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* sunxi has 9 banks of gpio, they are:
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* PA0 - PA17 | PB0 - PB23 | PC0 - PC24
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* PD0 - PD27 | PE0 - PE31 | PF0 - PF5
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* PG0 - PG9 | PH0 - PH27 | PI0 - PI12
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*/
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#define SUNXI_GPIO_A 0
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#define SUNXI_GPIO_B 1
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#define SUNXI_GPIO_C 2
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#define SUNXI_GPIO_D 3
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#define SUNXI_GPIO_E 4
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#define SUNXI_GPIO_F 5
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#define SUNXI_GPIO_G 6
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#define SUNXI_GPIO_H 7
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#define SUNXI_GPIO_I 8
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/*
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* This defines the number of GPIO banks for the _main_ GPIO controller.
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* You should fix up the padding in struct sunxi_gpio_reg below if you
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* change this.
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*/
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#define SUNXI_GPIO_BANKS 9
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/*
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* sun6i/sun8i and later SoCs have an additional GPIO controller (R_PIO)
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* at a different register offset.
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*
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* sun6i has 2 banks:
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* PL0 - PL8 | PM0 - PM7
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*
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* sun8i has 1 bank:
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* PL0 - PL11
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*
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* sun9i has 3 banks:
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* PL0 - PL9 | PM0 - PM15 | PN0 - PN1
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*/
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#define SUNXI_GPIO_L 11
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#define SUNXI_GPIO_M 12
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#define SUNXI_GPIO_N 13
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struct sunxi_gpio {
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u32 cfg[4];
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u32 dat;
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u32 drv[2];
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u32 pull[2];
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};
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/* gpio interrupt control */
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struct sunxi_gpio_int {
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u32 cfg[3];
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u32 ctl;
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u32 sta;
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u32 deb; /* interrupt debounce */
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};
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struct sunxi_gpio_reg {
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struct sunxi_gpio gpio_bank[SUNXI_GPIO_BANKS];
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u8 res[0xbc];
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struct sunxi_gpio_int gpio_int;
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};
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#define SUN50I_H6_GPIO_POW_MOD_SEL 0x340
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#define SUN50I_H6_GPIO_POW_MOD_VAL 0x348
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#define BANK_TO_GPIO(bank) (((bank) < SUNXI_GPIO_L) ? \
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&((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank] : \
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&((struct sunxi_gpio_reg *)SUNXI_R_PIO_BASE)->gpio_bank[(bank) - SUNXI_GPIO_L])
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#define GPIO_BANK(pin) ((pin) >> 5)
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#define GPIO_NUM(pin) ((pin) & 0x1f)
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#define GPIO_CFG_INDEX(pin) (((pin) & 0x1f) >> 3)
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#define GPIO_CFG_OFFSET(pin) ((((pin) & 0x1f) & 0x7) << 2)
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#define GPIO_DRV_INDEX(pin) (((pin) & 0x1f) >> 4)
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#define GPIO_DRV_OFFSET(pin) ((((pin) & 0x1f) & 0xf) << 1)
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#define GPIO_PULL_INDEX(pin) (((pin) & 0x1f) >> 4)
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#define GPIO_PULL_OFFSET(pin) ((((pin) & 0x1f) & 0xf) << 1)
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/* GPIO bank sizes */
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#define SUNXI_GPIOS_PER_BANK 32
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#define SUNXI_GPIO_NEXT(__gpio) \
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((__gpio##_START) + SUNXI_GPIOS_PER_BANK)
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enum sunxi_gpio_number {
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SUNXI_GPIO_A_START = 0,
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SUNXI_GPIO_B_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_A),
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SUNXI_GPIO_C_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_B),
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SUNXI_GPIO_D_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_C),
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SUNXI_GPIO_E_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_D),
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SUNXI_GPIO_F_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_E),
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SUNXI_GPIO_G_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_F),
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SUNXI_GPIO_H_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_G),
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SUNXI_GPIO_I_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_H),
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SUNXI_GPIO_L_START = 352,
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SUNXI_GPIO_M_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_L),
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SUNXI_GPIO_N_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_M),
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};
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/* SUNXI GPIO number definitions */
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#define SUNXI_GPA(_nr) (SUNXI_GPIO_A_START + (_nr))
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#define SUNXI_GPB(_nr) (SUNXI_GPIO_B_START + (_nr))
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#define SUNXI_GPC(_nr) (SUNXI_GPIO_C_START + (_nr))
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#define SUNXI_GPD(_nr) (SUNXI_GPIO_D_START + (_nr))
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#define SUNXI_GPE(_nr) (SUNXI_GPIO_E_START + (_nr))
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#define SUNXI_GPF(_nr) (SUNXI_GPIO_F_START + (_nr))
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#define SUNXI_GPG(_nr) (SUNXI_GPIO_G_START + (_nr))
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#define SUNXI_GPH(_nr) (SUNXI_GPIO_H_START + (_nr))
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#define SUNXI_GPI(_nr) (SUNXI_GPIO_I_START + (_nr))
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#define SUNXI_GPL(_nr) (SUNXI_GPIO_L_START + (_nr))
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#define SUNXI_GPM(_nr) (SUNXI_GPIO_M_START + (_nr))
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#define SUNXI_GPN(_nr) (SUNXI_GPIO_N_START + (_nr))
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/* GPIO pin function config */
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#define SUNXI_GPIO_INPUT 0
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#define SUNXI_GPIO_OUTPUT 1
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#define SUNXI_GPIO_DISABLE 7
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#define SUN8I_H3_GPA_UART0 2
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#define SUN8I_H3_GPA_UART2 2
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#define SUN4I_GPB_PWM 2
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#define SUN4I_GPB_TWI0 2
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#define SUN4I_GPB_TWI1 2
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#define SUN5I_GPB_TWI1 2
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#define SUN8I_V3S_GPB_TWI0 2
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#define SUN4I_GPB_UART0 2
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#define SUN5I_GPB_UART0 2
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#define SUN8I_GPB_UART2 2
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#define SUN8I_A33_GPB_UART0 3
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#define SUN8I_A83T_GPB_UART0 2
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#define SUN8I_V3S_GPB_UART0 3
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#define SUN50I_GPB_UART0 4
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#define SUNXI_GPC_NAND 2
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#define SUNXI_GPC_SPI0 3
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#define SUNXI_GPC_SDC2 3
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#define SUN6I_GPC_SDC3 4
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#define SUN50I_GPC_SPI0 4
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#define SUNIV_GPC_SPI0 2
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#define SUNXI_GPD_LCD0 2
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#define SUNXI_GPD_LVDS0 3
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#define SUNIV_GPE_UART0 5
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#define SUNXI_GPF_SDC0 2
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#define SUNXI_GPF_UART0 4
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#define SUN8I_GPF_UART0 3
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#define SUN4I_GPG_SDC1 4
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#define SUN5I_GPG_SDC1 2
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#define SUN6I_GPG_SDC1 2
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#define SUN8I_GPG_SDC1 2
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#define SUN8I_GPG_UART1 2
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#define SUN5I_GPG_UART1 4
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#define SUN6I_GPH_PWM 2
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#define SUN8I_GPH_PWM 2
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#define SUN4I_GPH_SDC1 5
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#define SUN6I_GPH_TWI0 2
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#define SUN8I_GPH_TWI0 2
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#define SUN50I_GPH_TWI0 2
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#define SUN6I_GPH_TWI1 2
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#define SUN8I_GPH_TWI1 2
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#define SUN50I_GPH_TWI1 2
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#define SUN6I_GPH_UART0 2
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#define SUN9I_GPH_UART0 2
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#define SUN50I_H6_GPH_UART0 2
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#define SUN50I_H616_GPH_UART0 2
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#define SUNXI_GPI_SDC3 2
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#define SUN6I_GPL0_R_P2WI_SCK 3
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#define SUN6I_GPL1_R_P2WI_SDA 3
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#define SUN8I_GPL_R_RSB 2
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#define SUN8I_H3_GPL_R_TWI 2
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#define SUN8I_A23_GPL_R_TWI 3
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#define SUN8I_GPL_R_UART 2
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#define SUN50I_GPL_R_TWI 2
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#define SUN50I_H616_GPL_R_TWI 3
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#define SUN9I_GPN_R_RSB 3
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/* GPIO pin pull-up/down config */
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#define SUNXI_GPIO_PULL_DISABLE 0
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#define SUNXI_GPIO_PULL_UP 1
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#define SUNXI_GPIO_PULL_DOWN 2
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struct sunxi_gpio_plat {
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struct sunxi_gpio *regs;
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char bank_name[3];
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};
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void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val);
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void sunxi_gpio_set_cfgpin(u32 pin, u32 val);
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int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset);
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int sunxi_gpio_get_cfgpin(u32 pin);
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void sunxi_gpio_set_drv(u32 pin, u32 val);
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void sunxi_gpio_set_drv_bank(struct sunxi_gpio *pio, u32 bank_offset, u32 val);
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void sunxi_gpio_set_pull(u32 pin, u32 val);
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void sunxi_gpio_set_pull_bank(struct sunxi_gpio *pio, int bank_offset, u32 val);
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int sunxi_name_to_gpio(const char *name);
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#endif /* _SUNXI_GPIO_H */
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