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099f3145b4
Currently NAND clock setup is done in board code, both in SPL and in U-Boot proper. Add the NAND clocks/resets here so they can be used by the "full" NAND driver once it is converted to the driver model. The bit locations are copied from the Linux CCU drivers. Signed-off-by: Samuel Holland <samuel@sholland.org>
124 lines
3.6 KiB
C
124 lines
3.6 KiB
C
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) 2021 Jernej Skrabec <jernej.skrabec@siol.net>
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <errno.h>
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#include <clk/sunxi.h>
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#include <dt-bindings/clock/sun50i-h616-ccu.h>
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#include <dt-bindings/reset/sun50i-h616-ccu.h>
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#include <linux/bitops.h>
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static struct ccu_clk_gate h616_gates[] = {
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[CLK_PLL_PERIPH0] = GATE(0x020, BIT(31) | BIT(27)),
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[CLK_APB1] = GATE_DUMMY,
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[CLK_NAND0] = GATE(0x810, BIT(31)),
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[CLK_NAND1] = GATE(0x814, BIT(31)),
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[CLK_BUS_NAND] = GATE(0x82c, BIT(0)),
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[CLK_BUS_MMC0] = GATE(0x84c, BIT(0)),
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[CLK_BUS_MMC1] = GATE(0x84c, BIT(1)),
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[CLK_BUS_MMC2] = GATE(0x84c, BIT(2)),
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[CLK_BUS_UART0] = GATE(0x90c, BIT(0)),
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[CLK_BUS_UART1] = GATE(0x90c, BIT(1)),
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[CLK_BUS_UART2] = GATE(0x90c, BIT(2)),
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[CLK_BUS_UART3] = GATE(0x90c, BIT(3)),
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[CLK_BUS_UART4] = GATE(0x90c, BIT(4)),
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[CLK_BUS_UART5] = GATE(0x90c, BIT(5)),
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[CLK_BUS_I2C0] = GATE(0x91c, BIT(0)),
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[CLK_BUS_I2C1] = GATE(0x91c, BIT(1)),
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[CLK_BUS_I2C2] = GATE(0x91c, BIT(2)),
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[CLK_BUS_I2C3] = GATE(0x91c, BIT(3)),
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[CLK_BUS_I2C4] = GATE(0x91c, BIT(4)),
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[CLK_SPI0] = GATE(0x940, BIT(31)),
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[CLK_SPI1] = GATE(0x944, BIT(31)),
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[CLK_BUS_SPI0] = GATE(0x96c, BIT(0)),
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[CLK_BUS_SPI1] = GATE(0x96c, BIT(1)),
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[CLK_BUS_EMAC0] = GATE(0x97c, BIT(0)),
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[CLK_BUS_EMAC1] = GATE(0x97c, BIT(1)),
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[CLK_USB_PHY0] = GATE(0xa70, BIT(29)),
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[CLK_USB_OHCI0] = GATE(0xa70, BIT(31)),
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[CLK_USB_PHY1] = GATE(0xa74, BIT(29)),
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[CLK_USB_OHCI1] = GATE(0xa74, BIT(31)),
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[CLK_USB_PHY2] = GATE(0xa78, BIT(29)),
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[CLK_USB_OHCI2] = GATE(0xa78, BIT(31)),
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[CLK_USB_PHY3] = GATE(0xa7c, BIT(29)),
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[CLK_USB_OHCI3] = GATE(0xa7c, BIT(31)),
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[CLK_BUS_OHCI0] = GATE(0xa8c, BIT(0)),
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[CLK_BUS_OHCI1] = GATE(0xa8c, BIT(1)),
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[CLK_BUS_OHCI2] = GATE(0xa8c, BIT(2)),
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[CLK_BUS_OHCI3] = GATE(0xa8c, BIT(3)),
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[CLK_BUS_EHCI0] = GATE(0xa8c, BIT(4)),
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[CLK_BUS_EHCI1] = GATE(0xa8c, BIT(5)),
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[CLK_BUS_EHCI2] = GATE(0xa8c, BIT(6)),
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[CLK_BUS_EHCI3] = GATE(0xa8c, BIT(7)),
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[CLK_BUS_OTG] = GATE(0xa8c, BIT(8)),
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};
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static struct ccu_reset h616_resets[] = {
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[RST_BUS_NAND] = RESET(0x82c, BIT(16)),
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[RST_BUS_MMC0] = RESET(0x84c, BIT(16)),
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[RST_BUS_MMC1] = RESET(0x84c, BIT(17)),
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[RST_BUS_MMC2] = RESET(0x84c, BIT(18)),
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[RST_BUS_UART0] = RESET(0x90c, BIT(16)),
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[RST_BUS_UART1] = RESET(0x90c, BIT(17)),
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[RST_BUS_UART2] = RESET(0x90c, BIT(18)),
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[RST_BUS_UART3] = RESET(0x90c, BIT(19)),
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[RST_BUS_UART4] = RESET(0x90c, BIT(20)),
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[RST_BUS_UART5] = RESET(0x90c, BIT(21)),
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[RST_BUS_I2C0] = RESET(0x91c, BIT(16)),
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[RST_BUS_I2C1] = RESET(0x91c, BIT(17)),
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[RST_BUS_I2C2] = RESET(0x91c, BIT(18)),
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[RST_BUS_I2C3] = RESET(0x91c, BIT(19)),
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[RST_BUS_I2C4] = RESET(0x91c, BIT(20)),
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[RST_BUS_SPI0] = RESET(0x96c, BIT(16)),
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[RST_BUS_SPI1] = RESET(0x96c, BIT(17)),
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[RST_BUS_EMAC0] = RESET(0x97c, BIT(16)),
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[RST_BUS_EMAC1] = RESET(0x97c, BIT(17)),
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[RST_USB_PHY0] = RESET(0xa70, BIT(30)),
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[RST_USB_PHY1] = RESET(0xa74, BIT(30)),
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[RST_USB_PHY2] = RESET(0xa78, BIT(30)),
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[RST_USB_PHY3] = RESET(0xa7c, BIT(30)),
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[RST_BUS_OHCI0] = RESET(0xa8c, BIT(16)),
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[RST_BUS_OHCI1] = RESET(0xa8c, BIT(17)),
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[RST_BUS_OHCI2] = RESET(0xa8c, BIT(18)),
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[RST_BUS_OHCI3] = RESET(0xa8c, BIT(19)),
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[RST_BUS_EHCI0] = RESET(0xa8c, BIT(20)),
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[RST_BUS_EHCI1] = RESET(0xa8c, BIT(21)),
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[RST_BUS_EHCI2] = RESET(0xa8c, BIT(22)),
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[RST_BUS_EHCI3] = RESET(0xa8c, BIT(23)),
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[RST_BUS_OTG] = RESET(0xa8c, BIT(24)),
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};
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const struct ccu_desc h616_ccu_desc = {
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.gates = h616_gates,
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.resets = h616_resets,
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.num_gates = ARRAY_SIZE(h616_gates),
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.num_resets = ARRAY_SIZE(h616_resets),
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};
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