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smaeul-u-boot/arch/riscv/cpu
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Samuel Holland 0636e3e95b riscv: cpu: thead: Add CPU-specific cache operations 
Use the vendor CSRs for enabling/disabling the caches, and the ISA
extension for cache maintenance.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2023-02-05 14:15:31 -06:00
..
ax25
riscv: ax25: bypass malloc when spl fit boots from ram
2023-02-01 16:17:45 +08:00
fu540
board_f: Fix types for board_get_usable_ram_top()
2022-09-23 15:12:42 -04:00
fu740
board_f: Fix types for board_get_usable_ram_top()
2022-09-23 15:12:42 -04:00
generic
board_f: Fix types for board_get_usable_ram_top()
2022-09-23 15:12:42 -04:00
thead
riscv: cpu: thead: Add CPU-specific cache operations
2023-02-05 14:15:31 -06:00
cpu.c
riscv: cpu: check U-Mode before counteren write
2023-02-01 16:17:13 +08:00
Makefile
riscv: Move trap handler codes to mtrap.S
2018-12-18 09:56:27 +08:00
mtrap.S
riscv: Add option to print registers on exception
2020-02-10 14:51:08 +08:00
start.S
riscv: Introduce AVAILABLE_HARTS
2022-09-26 14:29:13 +08:00
u-boot-spl.lds
linker_lists: Rename sections to remove . prefix
2022-06-23 12:58:18 -04:00
u-boot.lds
linker_lists: Rename sections to remove . prefix
2022-06-23 12:58:18 -04:00