mirror of
https://github.com/smaeul/u-boot.git
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320 lines
6.9 KiB
Plaintext
320 lines
6.9 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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#include <dt-bindings/clock/bl808-glb.h>
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#include <dt-bindings/clock/bl808-hbn.h>
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#include <dt-bindings/clock/bl808-mm-glb.h>
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#include <dt-bindings/clock/bl808-pds.h>
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#include <dt-bindings/reset/bl808-mm-glb.h>
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/dts-v1/;
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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ext_xtal: clk-ext-xtal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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mcu_peri: bus@20000000 {
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compatible = "simple-bus";
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ranges;
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#address-cells = <1>;
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#size-cells = <1>;
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glb: syscon@20000000 {
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compatible = "bflb,bl808-glb", "simple-mfd";
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reg = <0x20000000 0x1000>;
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ranges;
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#address-cells = <1>;
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#size-cells = <1>;
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glb_clk: clock-controller@20000000 {
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compatible = "bflb,bl808-glb-clk";
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reg = <0x20000000 0x1000>;
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clocks = <&hbn_clk CLK_XCLK>,
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<&hbn_clk CLK_HBN_ROOT>,
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<&hbn_clk CLK_HBN_UART>;
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clock-names = "xclk",
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"hbn_root",
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"hbn_uart";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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sysreset: sysreset@20000000 {
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compatible = "bflb,bl808-glb-sysreset";
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reg = <0x20000000 0x1000>;
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};
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gpio: gpio@20000000 {
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compatible = "bflb,bl808-gpio";
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reg = <0x20000000 0x1000>;
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gpio-controller;
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interrupt-controller;
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#gpio-cells = <2>;
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#interrupt-cells = <2>;
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emac_pins: emac-pins {
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pins = "GPIO24", "GPIO25", "GPIO26",
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"GPIO27", "GPIO28", "GPIO29",
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"GPIO30", "GPIO31", "GPIO32",
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"GPIO33";
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function = "emac";
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};
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sdh_pins: sdh-pins {
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pins = "GPIO0", "GPIO1", "GPIO2",
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"GPIO3", "GPIO4", "GPIO5";
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function = "sdh";
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};
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};
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};
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gpip: gpip@20002000 {
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compatible = "bflb,bl808-gpip";
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reg = <0x20002000 0x400>;
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#io-channel-cells = <1>;
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};
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cci: clock-controller@20008000 {
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compatible = "bflb,bl808-cci";
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reg = <0x20008000 0x1000>;
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clocks = <&pds_clk CLK_RC32M>,
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<&hbn_clk CLK_XTAL>;
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clock-names = "rc32m",
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"xtal";
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#clock-cells = <1>;
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};
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uart0: serial@2000a000 {
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compatible = "bflb,bl808-uart";
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reg = <0x2000a000 0x100>;
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clocks = <&glb_clk CLK_UART>;
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status = "disabled";
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};
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uart1: serial@2000a100 {
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compatible = "bflb,bl808-uart";
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reg = <0x2000a100 0x100>;
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clocks = <&glb_clk CLK_UART>;
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status = "disabled";
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};
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spi0: spi@2000a200 {
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compatible = "bflb,bl808-spi";
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reg = <0x2000a200 0x100>;
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};
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i2c0: i2c@2000a300 {
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compatible = "bflb,bl808-i2c";
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reg = <0x2000a300 0x100>;
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};
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pwm: pwm@2000a400 {
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compatible = "bflb,bl808-pwm";
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reg = <0x2000a400 0x100>;
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};
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timer0: timer@2000a500 {
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compatible = "bflb,bl808-timer";
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reg = <0x2000a500 0x100>;
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};
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ir: ir@2000a600 {
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compatible = "bflb,bl808-ir";
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reg = <0x2000a600 0x100>;
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};
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i2c1: i2c@2000a900 {
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compatible = "bflb,bl808-i2c";
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reg = <0x2000a900 0x100>;
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};
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uart2: serial@2000aa00 {
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compatible = "bflb,bl808-uart";
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reg = <0x2000aa00 0x100>;
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clocks = <&hbn_clk CLK_HBN_UART>;
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};
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i2s: i2s@2000ab00 {
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compatible = "bflb,bl808-i2s";
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reg = <0x2000ab00 0x100>;
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};
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dma0: dma@2000c000 {
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compatible = "bflb,bl808-dma";
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reg = <0x2000c000 0x1000>;
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};
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pds: syscon@2000e000 {
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compatible = "bflb,bl808-pds", "simple-mfd";
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reg = <0x2000e000 0x1000>;
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ranges;
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#address-cells = <1>;
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#size-cells = <1>;
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pds_clk: clock-controller@2000e000 {
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compatible = "bflb,bl808-pds-clk";
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reg = <0x2000e000 0x1000>;
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clocks = <&glb_clk CLK_TOP_AUPLL_DIV1>,
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<&glb_clk CLK_TOP_CPUPLL_400M>,
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<&glb_clk CLK_TOP_WIFIPLL_240M>,
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<&glb_clk CLK_TOP_WIFIPLL_320M>;
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clock-names = "aupll_div1",
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"cpupll_400m",
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"wifipll_240m",
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"wifipll_320m";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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usb_phy: phy@2000e500 {
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compatible = "bflb,bl808-usb-phy";
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reg = <0x2000e500 0x8>;
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#phy-cells = <0>;
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};
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};
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hbn: syscon@2000f000 {
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compatible = "bflb,bl808-hbn", "simple-mfd";
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reg = <0x2000f000 0x1000>;
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ranges;
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#address-cells = <1>;
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#size-cells = <1>;
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hbn_clk: clock-controller@2000f000 {
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compatible = "bflb,bl808-hbn-clk";
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reg = <0x2000f000 0x1000>;
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clocks = <&pds_clk CLK_RC32M>,
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<&pds_clk CLK_PDS_PLL>,
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<&glb_clk CLK_BCLK>,
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<&glb_clk CLK_DIG_32K>,
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<&glb_clk CLK_TOP_MUXPLL_160M>,
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<&ext_xtal>;
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clock-names = "rc32m",
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"pds_pll",
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"bclk",
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"dig_32k",
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"muxpll_160m",
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"ext_xtal";
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#clock-cells = <1>;
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};
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};
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audio: audio@20055000 {
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compatible = "bflb,bl808-audio";
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reg = <0x20055000 0x1000>;
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};
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efuse: efuse@20056000 {
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compatible = "bflb,bl808-efuse";
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reg = <0x20056000 0x1000>;
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};
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sdh: mmc@20060000 {
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compatible = "bflb,bl808-sdhci";
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reg = <0x20060000 0x1000>;
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clocks = <&glb_clk CLK_BUS_SDH>,
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<&glb_clk CLK_SDH>;
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clock-names = "bus", "mod";
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pinctrl-0 = <&sdh_pins>;
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pinctrl-names = "default";
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};
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emac: emac@20070000 {
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compatible = "bflb,bl808-emac";
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reg = <0x20070000 0x1000>;
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clocks = <&glb_clk CLK_BUS_EMAC>;
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clock-names = "bus";
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pinctrl-0 = <&emac_pins>;
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pinctrl-names = "default";
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};
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dma1: dma@20071000 {
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compatible = "bflb,bl808-dma";
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reg = <0x20071000 0x1000>;
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};
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usb: usb@20072000 {
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compatible = "bflb,bl808-usb";
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reg = <0x20072000 0x1000>;
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clocks = <&glb_clk CLK_BUS_USB>;
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clock-names = "bus";
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phys = <&usb_phy>;
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};
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};
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mm_peri: bus@30000000 {
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compatible = "simple-bus";
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ranges;
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#address-cells = <1>;
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#size-cells = <1>;
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mm_misc: syscon@30000000 {
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compatible = "bflb,bl808-mm-misc";
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reg = <0x30000000 0x1000>;
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clocks = <&mm_glb_clk CLK_MM_CPU>;
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resets = <&mm_glb_clk RST_MM_CPU>;
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};
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dma2: dma@30001000 {
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compatible = "bflb,bl808-dma";
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reg = <0x30001000 0x1000>;
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};
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uart3: serial@30002000 {
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compatible = "bflb,bl808-uart";
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reg = <0x30002000 0x1000>;
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clocks = <&mm_glb_clk CLK_MM_UART0>;
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};
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i2c2: i2c@30003000 {
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compatible = "bflb,bl808-i2c";
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reg = <0x30003000 0x1000>;
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};
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i2c3: i2c@30004000 {
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compatible = "bflb,bl808-i2c";
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reg = <0x30004000 0x1000>;
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};
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mm_glb_clk: clock-controller@30007000 {
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compatible = "bflb,bl808-mm-glb-clk";
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reg = <0x30007000 0x1000>;
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clocks = <&pds_clk CLK_RC32M>,
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<&hbn_clk CLK_XTAL>,
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<&glb_clk CLK_TOP_CPUPLL_400M>,
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<&glb_clk CLK_DSPPLL>,
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<&glb_clk CLK_MM_MUXPLL_160M>,
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<&glb_clk CLK_MM_MUXPLL_240M>,
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<&glb_clk CLK_MM_MUXPLL_320M>;
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clock-names = "rc32m",
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"xtal",
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"cpupll_400m",
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"dsppll",
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"muxpll_160m",
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"muxpll_240m",
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"muxpll_320m";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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spi1: spi@30008000 {
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compatible = "bflb,bl808-spi";
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reg = <0x30008000 0x1000>;
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};
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timer1: timer@30009000 {
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compatible = "bflb,bl808-timer";
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reg = <0x30009000 0x1000>;
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};
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psram_uhs: memory-controller@3000f000 {
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compatible = "bflb,bl808-psram-uhs";
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reg = <0x3000f000 0x1000>;
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};
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};
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};
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