Samuel Holland bbcc76ee51 riscv: Weakly define invalidate_icache_range()
Some RISC-V CPUs have a vendor-specific way to invalidate a portion of
the instruction cache. Allow them to override invalidate_icache_range().

Signed-off-by: Samuel Holland <samuel@sholland.org>
2023-02-05 09:58:59 -06:00
..
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