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e110ca11b3
BL808 contains clocks and resets controlled by registers in several MMIO regions, mostly because each MMIO region is in a separate power domain. Add the descriptions for the known clocks and resets. Signed-off-by: Samuel Holland <samuel@sholland.org>
444 lines
11 KiB
C
444 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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#include <bl808/glb_reg.h>
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#include <bl808/hbn_reg.h>
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#include <bl808/mm_glb_reg.h>
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#include <bl808/pds_reg.h>
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#include <clk/bflb.h>
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#include <dt-bindings/clock/bl808-glb.h>
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#include <dt-bindings/clock/bl808-hbn.h>
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#include <dt-bindings/clock/bl808-mm-glb.h>
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#include <dt-bindings/clock/bl808-pds.h>
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#include <dt-bindings/reset/bl808-glb.h>
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#include <dt-bindings/reset/bl808-mm-glb.h>
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#include <linux/bitops.h>
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#define PRNTS(...) (const u8[]) { __VA_ARGS__ }
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enum {
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/* Fixed clocks */
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FW_EXT_XTAL = FW_PARENT_BASE,
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FW_EXT_XTAL32K,
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/* Provided by GLB */
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FW_BCLK,
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FW_DIG_32K,
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FW_AUPLL_DIV1,
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FW_CPUPLL_400M,
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FW_DSPPLL,
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FW_MUXPLL_160M,
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FW_MUXPLL_240M,
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FW_MUXPLL_320M,
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FW_WIFIPLL_240M,
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FW_WIFIPLL_320M,
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/* Provided by HBN */
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FW_XCLK,
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FW_HBN_ROOT,
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FW_HBN_UART,
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FW_XTAL,
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/* Provided by PDS */
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FW_RC32M,
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FW_PDS_PLL,
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FW_PARENT_MAX,
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};
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static const char *const bl808_fw_parents[FW_PARENT_MAX-FW_PARENT_BASE] = {
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/* Fixed clocks */
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"ext_xtal",
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"ext_xtal32k",
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/* Provided by GLB */
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"bclk",
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"dig_32k",
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"aupll_div1",
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"cpupll_400m",
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"dsppll",
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"muxpll_160m",
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"muxpll_240m",
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"muxpll_320m",
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"wifipll_240m",
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"wifipll_320m",
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/* Provided by HBN */
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"xclk",
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"hbn_root",
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"hbn_uart",
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"xtal",
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/* Provided by PDS */
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"rc32m",
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"pds_pll",
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};
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static const struct bflb_clk_data bl808_glb_clks[] = {
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/*
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* NOTE: This list of clocks is incomplete.
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* The others in ths file are complete.
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*/
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[CLK_CPU] = {
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.name = "CPU",
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.parents = PRNTS(FW_HBN_ROOT),
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.div_reg = GLB_SYS_CFG0_OFFSET,
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.div_mask = GLB_REG_HCLK_DIV_MSK,
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},
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[CLK_HCLK] = {
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.name = "HCLK",
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.parents = PRNTS(CLK_CPU),
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.en_reg = GLB_SYS_CFG0_OFFSET,
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.en_mask = GLB_REG_HCLK_EN_MSK,
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},
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[CLK_BCLK] = {
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.name = "BCLK",
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.parents = PRNTS(CLK_CPU),
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/* Must set GLB_REG_BCLK_DIV_ACT_PULSE to update */
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.div_reg = GLB_SYS_CFG0_OFFSET,
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.div_mask = GLB_REG_BCLK_DIV_MSK,
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.en_reg = GLB_SYS_CFG0_OFFSET,
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.en_mask = GLB_REG_BCLK_EN_MSK,
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},
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[CLK_UART] = {
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.name = "UART",
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.parents = PRNTS(FW_HBN_UART),
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.div_reg = GLB_UART_CFG0_OFFSET,
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.div_mask = GLB_UART_CLK_DIV_MSK,
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.en_reg = GLB_UART_CFG0_OFFSET,
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.en_mask = GLB_UART_CLK_EN_MSK,
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},
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[CLK_DSPPLL] = {
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.name = "DSPPLL",
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},
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[CLK_MM_MUXPLL_160M] = {
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.name = "MM_MUXPLL_160M",
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.rate = 160000000,
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},
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[CLK_MM_MUXPLL_240M] = {
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.name = "MM_MUXPLL_240M",
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.rate = 240000000,
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},
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[CLK_MM_MUXPLL_320M] = {
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.name = "MM_MUXPLL_320M",
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.rate = 320000000,
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},
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[CLK_TOP_MUXPLL_160M] = {
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.name = "TOP_MUXPLL_160M",
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.rate = 160000000,
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},
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[CLK_SDH] = {
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.name = "SDH",
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.parents = PRNTS(CLK_WIFIPLL_DIV5,
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CLK_TOP_CPUPLL_100M),
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.sel_reg = GLB_SDH_CFG0_OFFSET,
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.sel_mask = GLB_REG_SDH_CLK_SEL_MSK,
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.div_reg = GLB_SDH_CFG0_OFFSET,
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.div_mask = GLB_REG_SDH_CLK_DIV_MSK,
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.en_reg = GLB_SDH_CFG0_OFFSET,
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.en_mask = GLB_REG_SDH_CLK_EN_MSK,
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},
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[CLK_TOP_CPUPLL_100M] = {
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.name = "TOP_CPUPLL_100M",
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.rate = 100000000,
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},
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[CLK_TOP_CPUPLL_400M] = {
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.name = "TOP_CPUPLL_400M",
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.rate = 400000000,
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},
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[CLK_TOP_WIFIPLL_240M] = {
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.name = "TOP_WIFIPLL_240M",
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.rate = 240000000,
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},
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[CLK_TOP_WIFIPLL_320M] = {
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.name = "TOP_WIFIPLL_320M",
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.rate = 320000000,
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},
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[CLK_WIFIPLL] = {
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.name = "WIFIPLL",
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.rate = 480000000,
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},
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[CLK_WIFIPLL_DIV5] = {
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.name = "WIFIPLL_DIV5",
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.parents = PRNTS(CLK_WIFIPLL),
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.en_reg = GLB_WIFI_PLL_CFG8_OFFSET,
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.en_mask = GLB_WIFIPLL_EN_DIV5_MSK,
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.fixed_div = 5,
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},
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[CLK_BUS_USB] = {
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.name = "BUS_USB",
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.en_reg = GLB_CGEN_CFG1_OFFSET,
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.en_mask = GLB_CGEN_S1_RSVD13_MSK,
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},
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[CLK_BUS_SDH] = {
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.name = "BUS_SDH",
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.en_reg = GLB_CGEN_CFG2_OFFSET,
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.en_mask = GLB_CGEN_S1_EXT_SDH_MSK,
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},
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[CLK_BUS_EMAC] = {
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.name = "BUS_EMAC",
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.en_reg = GLB_CGEN_CFG2_OFFSET,
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.en_mask = GLB_CGEN_S1_EXT_EMAC_MSK,
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},
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};
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const struct bflb_clk_desc bl808_glb_clk_desc = {
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.clks = bl808_glb_clks,
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.fw_parents = bl808_fw_parents,
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.num_clks = ARRAY_SIZE(bl808_glb_clks),
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.num_fw_parents = ARRAY_SIZE(bl808_fw_parents),
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};
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static const struct bflb_clk_data bl808_hbn_clks[] = {
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[CLK_XCLK] = {
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.name = "XCLK",
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.parents = PRNTS(FW_RC32M,
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CLK_XTAL),
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.sel_reg = HBN_GLB_OFFSET,
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.sel_mask = BIT(0), /* HBN_ROOT_CLK_SEL[0] */
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},
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[CLK_HBN_ROOT] = {
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.name = "HBN_ROOT",
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.parents = PRNTS(CLK_XCLK,
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FW_PDS_PLL),
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.sel_reg = HBN_GLB_OFFSET,
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.sel_mask = BIT(1), /* HBN_ROOT_CLK_SEL[1] */
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},
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[CLK_HBN_UART_SEL] = {
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.name = "HBN_UART_SEL",
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.parents = PRNTS(FW_BCLK,
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FW_MUXPLL_160M),
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.sel_reg = HBN_GLB_OFFSET,
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.sel_mask = HBN_UART_CLK_SEL_MSK,
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},
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[CLK_F32K] = {
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.name = "F32K",
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.parents = PRNTS(CLK_RC32K,
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CLK_XTAL32K,
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FW_DIG_32K,
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NO_PARENT),
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.sel_reg = HBN_GLB_OFFSET,
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.sel_mask = HBN_F32K_SEL_MSK,
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},
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[CLK_HBN_UART] = {
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.name = "HBN_UART",
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.parents = PRNTS(CLK_HBN_UART_SEL,
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CLK_XCLK),
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.sel_reg = HBN_GLB_OFFSET,
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.sel_mask = HBN_UART_CLK_SEL2_MSK,
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},
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[CLK_RC32K] = {
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.name = "RC32K",
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.rate = 32000,
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},
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[CLK_XTAL32K] = {
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.name = "XTAL32K",
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.parents = PRNTS(FW_EXT_XTAL32K),
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},
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[CLK_XTAL] = {
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.name = "XTAL",
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.parents = PRNTS(FW_EXT_XTAL),
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},
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};
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const struct bflb_clk_desc bl808_hbn_clk_desc = {
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.clks = bl808_hbn_clks,
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.fw_parents = bl808_fw_parents,
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.num_clks = ARRAY_SIZE(bl808_hbn_clks),
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.num_fw_parents = ARRAY_SIZE(bl808_fw_parents),
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};
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static const struct bflb_clk_data bl808_mm_glb_clks[] = {
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[CLK_MM_UART] = {
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.name = "MM_UART",
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.parents = PRNTS(CLK_MM_BCLK1X,
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FW_MUXPLL_160M,
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CLK_MM_XCLK,
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NO_PARENT),
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.sel_reg = MM_GLB_MM_CLK_CTRL_CPU_OFFSET,
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.sel_mask = MM_GLB_REG_UART_CLK_SEL_MSK,
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},
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[CLK_MM_I2C] = {
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.name = "MM_I2C",
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.parents = PRNTS(CLK_MM_BCLK1X,
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CLK_MM_XCLK),
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.sel_reg = MM_GLB_MM_CLK_CTRL_CPU_OFFSET,
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.sel_mask = MM_GLB_REG_I2C_CLK_SEL_MSK,
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},
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[CLK_MM_SPI] = {
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.name = "MM_SPI",
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.parents = PRNTS(FW_MUXPLL_160M,
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CLK_MM_XCLK),
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.sel_reg = MM_GLB_MM_CLK_CTRL_CPU_OFFSET,
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.sel_mask = MM_GLB_REG_SPI_CLK_SEL_MSK,
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},
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[CLK_MM_MUXPLL] = {
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.name = "MM_MUXPLL",
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.parents = PRNTS(FW_MUXPLL_240M,
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FW_MUXPLL_320M,
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FW_CPUPLL_400M,
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FW_CPUPLL_400M),
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.sel_reg = MM_GLB_MM_CLK_CTRL_CPU_OFFSET,
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.sel_mask = MM_GLB_REG_CPU_CLK_SEL_MSK,
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},
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[CLK_MM_XCLK] = {
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.name = "MM_XCLK",
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.parents = PRNTS(FW_RC32M,
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FW_XTAL),
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.sel_reg = MM_GLB_MM_CLK_CTRL_CPU_OFFSET,
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.sel_mask = MM_GLB_REG_XCLK_CLK_SEL_MSK,
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},
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[CLK_MM_CPU] = {
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.name = "MM_CPU",
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.parents = PRNTS(CLK_MM_XCLK,
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CLK_MM_MUXPLL),
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.sel_reg = MM_GLB_MM_CLK_CTRL_CPU_OFFSET,
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.sel_mask = MM_GLB_REG_CPU_ROOT_CLK_SEL_MSK,
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.div_reg = MM_GLB_MM_CLK_CPU_OFFSET,
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.div_mask = MM_GLB_REG_CPU_CLK_DIV_MSK,
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.en_reg = MM_GLB_MM_CLK_CTRL_CPU_OFFSET,
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.en_mask = MM_GLB_REG_MMCPU0_CLK_EN_MSK,
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},
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[CLK_MM_BCLK1X] = {
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.name = "MM_BCLK1X",
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.parents = PRNTS(CLK_MM_XCLK,
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CLK_MM_XCLK,
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FW_MUXPLL_160M,
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FW_MUXPLL_240M),
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.sel_reg = MM_GLB_MM_CLK_CTRL_CPU_OFFSET,
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.sel_mask = MM_GLB_REG_BCLK1X_SEL_MSK,
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.div_reg = MM_GLB_MM_CLK_CPU_OFFSET,
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.div_mask = MM_GLB_REG_BCLK1X_DIV_MSK,
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},
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[CLK_MM_BCLK2X] = {
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.name = "MM_BCLK2X",
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.parents = PRNTS(CLK_MM_CPU),
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/* Must set MM_GLB_REG_BCLK2X_DIV_ACT_PULSE to update */
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.div_reg = MM_GLB_MM_CLK_CPU_OFFSET,
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.div_mask = MM_GLB_REG_BCLK2X_DIV_MSK,
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},
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[CLK_MM_CNN] = {
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.name = "MM_CNN",
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.parents = PRNTS(FW_MUXPLL_160M,
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FW_MUXPLL_240M,
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FW_MUXPLL_320M,
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FW_MUXPLL_320M),
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.sel_reg = MM_GLB_MM_CLK_CPU_OFFSET,
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.sel_mask = MM_GLB_REG_CNN_CLK_SEL_MSK,
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.div_reg = MM_GLB_MM_CLK_CPU_OFFSET,
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.div_mask = MM_GLB_REG_CNN_CLK_DIV_MSK,
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.en_reg = MM_GLB_MM_CLK_CPU_OFFSET,
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.en_mask = MM_GLB_REG_CNN_CLK_DIV_EN_MSK,
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},
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[CLK_MM_DSP] = {
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.name = "MM_DSP",
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.parents = PRNTS(FW_MUXPLL_160M,
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FW_MUXPLL_240M,
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FW_CPUPLL_400M,
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CLK_MM_XCLK),
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.sel_reg = MM_GLB_DP_CLK_OFFSET,
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.sel_mask = MM_GLB_REG_CLK_SEL_MSK,
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.div_reg = MM_GLB_DP_CLK_OFFSET,
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.div_mask = MM_GLB_REG_CLK_DIV_MSK,
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.en_reg = MM_GLB_DP_CLK_OFFSET,
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.en_mask = MM_GLB_REG_CLK_DIV_EN_MSK,
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},
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[CLK_MM_DSP_DP] = {
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.name = "MM_DSP_DP",
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.parents = PRNTS(FW_DSPPLL,
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CLK_MM_XCLK),
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.sel_reg = MM_GLB_DP_CLK_OFFSET,
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.sel_mask = MM_GLB_REG_DP_CLK_SEL_MSK,
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.div_reg = MM_GLB_DP_CLK_OFFSET,
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.div_mask = MM_GLB_REG_DP_CLK_DIV_MSK,
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.en_reg = MM_GLB_DP_CLK_OFFSET,
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.en_mask = MM_GLB_REG_DP_CLK_DIV_EN_MSK,
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},
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[CLK_MM_H264] = {
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.name = "MM_H264",
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.parents = PRNTS(FW_MUXPLL_160M,
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FW_MUXPLL_240M,
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FW_MUXPLL_320M,
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FW_MUXPLL_320M),
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.sel_reg = MM_GLB_CODEC_CLK_OFFSET,
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.sel_mask = MM_GLB_REG_H264_CLK_SEL_MSK,
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.div_reg = MM_GLB_CODEC_CLK_OFFSET,
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.div_mask = MM_GLB_REG_H264_CLK_DIV_MSK,
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.en_reg = MM_GLB_CODEC_CLK_OFFSET,
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.en_mask = MM_GLB_REG_H264_CLK_DIV_EN_MSK,
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},
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[CLK_MM_IC20] = {
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.name = "MM_IC20",
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.parents = PRNTS(CLK_MM_I2C),
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.div_reg = MM_GLB_MM_CLK_CTRL_PERI_OFFSET,
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.div_mask = MM_GLB_REG_I2C0_CLK_DIV_MSK,
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.en_reg = MM_GLB_MM_CLK_CTRL_PERI_OFFSET,
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.en_mask = MM_GLB_REG_I2C0_CLK_DIV_EN_MSK |
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MM_GLB_REG_I2C0_CLK_EN_MSK,
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},
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[CLK_MM_UART0] = {
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.name = "MM_UART0",
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.parents = PRNTS(CLK_MM_UART),
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.div_reg = MM_GLB_MM_CLK_CTRL_PERI_OFFSET,
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.div_mask = MM_GLB_REG_UART0_CLK_DIV_MSK,
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.en_reg = MM_GLB_MM_CLK_CTRL_PERI_OFFSET,
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.en_mask = MM_GLB_REG_UART0_CLK_DIV_EN_MSK,
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},
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[CLK_MM_SPI0] = {
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.name = "MM_SPI0",
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.parents = PRNTS(CLK_MM_SPI),
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.div_reg = MM_GLB_MM_CLK_CTRL_PERI_OFFSET,
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.div_mask = MM_GLB_REG_SPI_CLK_DIV_MSK,
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.en_reg = MM_GLB_MM_CLK_CTRL_PERI_OFFSET,
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.en_mask = MM_GLB_REG_SPI_CLK_DIV_EN_MSK,
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},
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[CLK_MM_I2C1] = {
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.name = "MM_I2C1",
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.parents = PRNTS(CLK_MM_I2C),
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.div_reg = MM_GLB_MM_CLK_CTRL_PERI3_OFFSET,
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.div_mask = MM_GLB_REG_I2C1_CLK_DIV_MSK,
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.en_reg = MM_GLB_MM_CLK_CTRL_PERI3_OFFSET,
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.en_mask = MM_GLB_REG_I2C1_CLK_DIV_EN_MSK,
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},
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[CLK_MM_UART1] = {
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.name = "MM_UART1",
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.parents = PRNTS(CLK_MM_UART),
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.div_reg = MM_GLB_MM_CLK_CTRL_PERI3_OFFSET,
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.div_mask = MM_GLB_REG_UART1_CLK_DIV_MSK,
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.en_reg = MM_GLB_MM_CLK_CTRL_PERI3_OFFSET,
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.en_mask = MM_GLB_REG_UART1_CLK_DIV_EN_MSK,
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},
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};
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static const struct bflb_reset_data bl808_mm_glb_resets[] = {
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[RST_MM_CPU] = { MM_GLB_MM_SW_SYS_RESET_OFFSET,
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MM_GLB_REG_CTRL_MMCPU0_RESET_POS },
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};
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const struct bflb_clk_desc bl808_mm_glb_clk_desc = {
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.clks = bl808_mm_glb_clks,
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.resets = bl808_mm_glb_resets,
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.fw_parents = bl808_fw_parents,
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.num_clks = ARRAY_SIZE(bl808_mm_glb_clks),
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.num_resets = ARRAY_SIZE(bl808_mm_glb_resets),
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.num_fw_parents = ARRAY_SIZE(bl808_fw_parents),
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};
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static const struct bflb_clk_data bl808_pds_clks[] = {
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[CLK_PDS_PLL] = {
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.name = "PDS_PLL",
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.parents = PRNTS(FW_CPUPLL_400M,
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FW_AUPLL_DIV1,
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FW_WIFIPLL_240M,
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FW_WIFIPLL_320M),
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.sel_reg = PDS_CPU_CORE_CFG1_OFFSET,
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.sel_mask = PDS_REG_PLL_SEL_MSK,
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.en_reg = PDS_CPU_CORE_CFG1_OFFSET,
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.en_mask = PDS_REG_MCU1_CLK_EN_MSK,
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},
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[CLK_RC32M] = {
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.name = "RC32M",
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.rate = 32000000,
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},
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};
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const struct bflb_clk_desc bl808_pds_clk_desc = {
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.clks = bl808_pds_clks,
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.fw_parents = bl808_fw_parents,
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.num_clks = ARRAY_SIZE(bl808_pds_clks),
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.num_fw_parents = ARRAY_SIZE(bl808_fw_parents),
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};
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