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64ca2ff591
This driver supports the pinmux, pinconf, and GPIO functions of the Bouffalo Lab BL616 and BL808 SoCs. Signed-off-by: Samuel Holland <samuel@sholland.org>
356 lines
8.6 KiB
C
356 lines
8.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#include <dm.h>
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#include <errno.h>
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#include <bl808/glb_reg.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <dm/device-internal.h>
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#include <dm/lists.h>
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#include <dm/pinctrl.h>
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#include <linux/bitfield.h>
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#define BFLB_FUNC_GPIO 11
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struct bflb_pinctrl_desc {
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const char *const *functions;
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u8 num_functions;
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u8 num_pins;
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};
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struct bflb_pinctrl_plat {
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void __iomem *base;
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const struct bflb_pinctrl_desc *desc;
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};
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static int bflb_gpio_get_value(struct udevice *dev, unsigned offset)
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{
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const struct bflb_pinctrl_plat *plat = dev_get_plat(dev);
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u32 val;
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val = readl(plat->base + GLB_GPIO_CFG0_OFFSET + 4 * offset);
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return FIELD_GET(GLB_REG_GPIO_0_I_MSK, val);
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}
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static int bflb_gpio_get_function(struct udevice *dev, unsigned offset)
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{
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const struct bflb_pinctrl_plat *plat = dev_get_plat(dev);
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u32 val;
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val = readl(plat->base + GLB_GPIO_CFG0_OFFSET + 4 * offset);
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if (!FIELD_GET(GLB_REG_GPIO_0_IE_MSK, val) &&
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!FIELD_GET(GLB_REG_GPIO_0_OE_MSK, val))
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return GPIOF_UNUSED;
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if (FIELD_GET(GLB_REG_GPIO_0_FUNC_SEL_MSK, val) != BFLB_FUNC_GPIO)
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return GPIOF_FUNC;
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else if (FIELD_GET(GLB_REG_GPIO_0_OE_MSK, val))
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return GPIOF_OUTPUT;
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else
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return GPIOF_INPUT;
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}
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static int bflb_gpio_set_flags(struct udevice *dev, unsigned int offset,
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ulong flags)
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{
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const struct bflb_pinctrl_plat *plat = dev_get_plat(dev);
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u32 val;
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val = readl(plat->base + GLB_GPIO_CFG0_OFFSET + 4 * offset);
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val &= ~(GLB_REG_GPIO_0_IE_MSK |
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GLB_REG_GPIO_0_PU_MSK |
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GLB_REG_GPIO_0_PD_MSK |
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GLB_REG_GPIO_0_OE_MSK |
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GLB_REG_GPIO_0_FUNC_SEL_MSK |
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GLB_REG_GPIO_0_O_MSK);
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val |= FIELD_PREP(GLB_REG_GPIO_0_FUNC_SEL_MSK, BFLB_FUNC_GPIO);
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if (flags & GPIOD_IS_OUT) {
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val |= GLB_REG_GPIO_0_OE_MSK;
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if (flags & GPIOD_IS_OUT_ACTIVE)
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val |= GLB_REG_GPIO_0_O_MSK;
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} else if (flags & GPIOD_IS_IN) {
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val |= GLB_REG_GPIO_0_IE_MSK;
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if (flags & GPIOD_PULL_UP)
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val |= GLB_REG_GPIO_0_PU_MSK;
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else if (flags & GPIOD_PULL_DOWN)
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val |= GLB_REG_GPIO_0_PD_MSK;
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}
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writel(val, plat->base + GLB_GPIO_CFG0_OFFSET + 4 * offset);
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return 0;
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}
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static const struct dm_gpio_ops bflb_gpio_ops = {
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.get_value = bflb_gpio_get_value,
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.get_function = bflb_gpio_get_function,
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.set_flags = bflb_gpio_set_flags,
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};
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static int bflb_gpio_probe(struct udevice *dev)
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{
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const struct bflb_pinctrl_plat *plat = dev_get_plat(dev);
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struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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uc_priv->bank_name = "GPIO";
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uc_priv->gpio_count = plat->desc->num_pins;
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return 0;
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}
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static struct driver bflb_gpio_driver = {
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.name = "bflb_gpio",
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.id = UCLASS_GPIO,
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.probe = bflb_gpio_probe,
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.ops = &bflb_gpio_ops,
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};
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static int bflb_pinctrl_get_pins_count(struct udevice *dev)
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{
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const struct bflb_pinctrl_plat *plat = dev_get_plat(dev);
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return plat->desc->num_pins;
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}
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static const char *bflb_pinctrl_get_pin_name(struct udevice *dev,
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uint pin_selector)
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{
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static char pin_name[sizeof("GPIO??")] = "GPIO??";
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snprintf(pin_name + 4, sizeof(pin_name) - 4, "%d", pin_selector);
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return pin_name;
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}
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static int bflb_pinctrl_get_functions_count(struct udevice *dev)
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{
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const struct bflb_pinctrl_plat *plat = dev_get_plat(dev);
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return plat->desc->num_functions;
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}
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static const char *bflb_pinctrl_get_function_name(struct udevice *dev,
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uint func_selector)
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{
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const struct bflb_pinctrl_plat *plat = dev_get_plat(dev);
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return plat->desc->functions[func_selector];
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}
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static int bflb_pinctrl_pinmux_set(struct udevice *dev, uint pin_selector,
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uint func_selector)
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{
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const struct bflb_pinctrl_plat *plat = dev_get_plat(dev);
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clrsetbits_le32(plat->base + GLB_GPIO_CFG0_OFFSET + 4 * pin_selector,
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GLB_REG_GPIO_0_FUNC_SEL_MSK,
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GLB_REG_GPIO_0_IE_MSK |
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FIELD_PREP(GLB_REG_GPIO_0_FUNC_SEL_MSK, func_selector));
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return 0;
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}
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static const struct pinconf_param bflb_pinctrl_pinconf_params[] = {
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{ "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
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{ "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
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{ "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
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{ "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
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{ "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 },
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{ "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 },
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{ "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 },
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{ "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 },
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{ "output-disable", PIN_CONFIG_OUTPUT_ENABLE, 0 },
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{ "output-enable", PIN_CONFIG_OUTPUT_ENABLE, 1 },
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};
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static int bflb_pinctrl_pinconf_set(struct udevice *dev, uint pin_selector,
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uint param, uint val)
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{
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const struct bflb_pinctrl_plat *plat = dev_get_plat(dev);
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u32 mask;
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switch (param) {
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case PIN_CONFIG_BIAS_DISABLE:
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mask = GLB_REG_GPIO_0_PU_MSK |
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GLB_REG_GPIO_0_PD_MSK;
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val = 0;
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break;
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case PIN_CONFIG_BIAS_PULL_DOWN:
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mask = GLB_REG_GPIO_0_PU_MSK |
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GLB_REG_GPIO_0_PD_MSK;
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if (!val)
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return -EINVAL;
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val = GLB_REG_GPIO_0_PD_MSK;
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break;
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case PIN_CONFIG_BIAS_PULL_UP:
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mask = GLB_REG_GPIO_0_PU_MSK |
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GLB_REG_GPIO_0_PD_MSK;
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if (!val)
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return -EINVAL;
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val = GLB_REG_GPIO_0_PU_MSK;
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break;
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case PIN_CONFIG_DRIVE_STRENGTH:
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mask = GLB_REG_GPIO_0_DRV_MSK;
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val <<= GLB_REG_GPIO_0_DRV_POS;
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break;
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case PIN_CONFIG_INPUT_ENABLE:
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mask = GLB_REG_GPIO_0_IE_MSK;
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val = val ? GLB_REG_GPIO_0_IE_MSK : 0;
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break;
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case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
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mask = GLB_REG_GPIO_0_SMT_MSK;
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val = val ? GLB_REG_GPIO_0_SMT_MSK : 0;
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break;
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case PIN_CONFIG_OUTPUT_ENABLE:
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mask = GLB_REG_GPIO_0_OE_MSK;
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val = val ? GLB_REG_GPIO_0_OE_MSK : 0;
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break;
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default:
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return -EINVAL;
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}
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clrsetbits_le32(plat->base + GLB_GPIO_CFG0_OFFSET + 4 * pin_selector,
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mask, val);
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return 0;
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}
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static int bflb_pinctrl_get_pin_muxing(struct udevice *dev, uint pin_selector,
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char *buf, int size)
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{
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const struct bflb_pinctrl_plat *plat = dev_get_plat(dev);
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const char *function;
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u32 val;
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val = readl(plat->base + GLB_GPIO_CFG0_OFFSET + 4 * pin_selector);
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val = FIELD_GET(GLB_REG_GPIO_0_FUNC_SEL_MSK, val);
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function = plat->desc->functions[val];
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if (function)
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strlcpy(buf, function, size);
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else
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snprintf(buf, size, "function %d", val);
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return 0;
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}
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static const struct pinctrl_ops bflb_pinctrl_ops = {
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.get_pins_count = bflb_pinctrl_get_pins_count,
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.get_pin_name = bflb_pinctrl_get_pin_name,
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.get_functions_count = bflb_pinctrl_get_functions_count,
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.get_function_name = bflb_pinctrl_get_function_name,
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.pinmux_set = bflb_pinctrl_pinmux_set,
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.pinconf_num_params = ARRAY_SIZE(bflb_pinctrl_pinconf_params),
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.pinconf_params = bflb_pinctrl_pinconf_params,
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.pinconf_set = bflb_pinctrl_pinconf_set,
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.set_state = pinctrl_generic_set_state,
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.get_pin_muxing = bflb_pinctrl_get_pin_muxing,
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};
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static int bflb_pinctrl_bind(struct udevice *dev)
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{
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return device_bind(dev, &bflb_gpio_driver, "gpio",
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dev_get_plat(dev), dev_ofnode(dev), NULL);
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}
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static int bflb_pinctrl_of_to_plat(struct udevice *dev)
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{
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struct bflb_pinctrl_plat *plat = dev_get_plat(dev);
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plat->base = dev_remap_addr(dev);
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if (!plat->base)
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return -ENOMEM;
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plat->desc = (const struct bflb_pinctrl_desc *)dev_get_driver_data(dev);
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if (!plat->desc)
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return -EINVAL;
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return 0;
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}
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static const char *const bl616_pinctrl_functions[] = {
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[0] = "sdh",
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[1] = "spi0",
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[2] = "flash",
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[3] = "i2s",
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[4] = "pdm",
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[5] = "i2c0",
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[6] = "i2c1",
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[7] = "uart",
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[8] = "emac",
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[9] = "cam",
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[10] = "analog",
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[11] = "gpio",
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[12] = "sdu",
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[16] = "pwm0",
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[24] = "qspi",
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[25] = "aupwm",
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[26] = "jtag",
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[27] = "pec",
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[31] = "clkout",
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};
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static const struct bflb_pinctrl_desc bl616_pinctrl_desc = {
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.functions = bl616_pinctrl_functions,
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.num_functions = ARRAY_SIZE(bl616_pinctrl_functions),
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.num_pins = 35,
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};
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static const char *const bl808_pinctrl_functions[] = {
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[0] = "sdh",
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[1] = "spi0",
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[2] = "flash",
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[3] = "i2s",
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[4] = "pdm",
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[5] = "i2c0",
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[6] = "i2c1",
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[7] = "uart",
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[8] = "emac",
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[9] = "cam",
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[10] = "analog",
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[11] = "gpio",
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[12] = "sdu",
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[16] = "pwm0",
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[17] = "pwm1",
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[18] = "spi1",
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[19] = "i2c2",
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[20] = "i2c3",
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[21] = "mm_uart",
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[22] = "dbi_b",
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[23] = "dbi_c",
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[24] = "dpi",
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[25] = "jtag_lp",
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[26] = "jtag_m0",
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[27] = "jtag_d0",
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[31] = "clkout",
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};
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static const struct bflb_pinctrl_desc bl808_pinctrl_desc = {
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.functions = bl808_pinctrl_functions,
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.num_functions = ARRAY_SIZE(bl808_pinctrl_functions),
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.num_pins = 46,
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};
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static const struct udevice_id bflb_pinctrl_ids[] = {
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{ .compatible = "bflb,bl616-gpio",
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.data = (ulong)&bl616_pinctrl_desc },
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{ .compatible = "bflb,bl808-gpio",
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.data = (ulong)&bl808_pinctrl_desc },
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{ }
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};
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U_BOOT_DRIVER(bflb_pinctrl) = {
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.name = "bflb_pinctrl",
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.id = UCLASS_PINCTRL,
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.of_match = bflb_pinctrl_ids,
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.bind = bflb_pinctrl_bind,
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.of_to_plat = bflb_pinctrl_of_to_plat,
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.plat_auto = sizeof(struct bflb_pinctrl_plat),
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.ops = &bflb_pinctrl_ops,
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};
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