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This driver extends the clock driver with reset control capability. Signed-off-by: Samuel Holland <samuel@sholland.org>
70 lines
1.7 KiB
C
70 lines
1.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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#include <dm.h>
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#include <reset-uclass.h>
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#include <asm/io.h>
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#include <clk/bflb.h>
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#include <linux/bitops.h>
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static const struct bflb_reset_data *
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bflb_reset_get_data(const struct bflb_clk_plat *plat,
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const struct reset_ctl *reset_ctl)
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{
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const struct bflb_clk_desc *desc = plat->desc;
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if (reset_ctl->id >= desc->num_resets)
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return NULL;
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return &desc->resets[reset_ctl->id];
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}
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static int bflb_reset_request(struct reset_ctl *reset_ctl)
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{
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const struct bflb_clk_plat *plat = dev_get_plat(reset_ctl->dev);
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return bflb_reset_get_data(plat, reset_ctl) ? 0 : -EINVAL;
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}
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static int bflb_reset_set(struct reset_ctl *reset_ctl, bool assert)
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{
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const struct bflb_clk_plat *plat = dev_get_plat(reset_ctl->dev);
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const struct bflb_reset_data *data = bflb_reset_get_data(plat, reset_ctl);
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u32 mask = BIT(data->bit);
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clrsetbits_le32(plat->base + data->reg, mask, assert ? mask : 0);
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return 0;
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}
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static int bflb_reset_assert(struct reset_ctl *reset_ctl)
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{
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return bflb_reset_set(reset_ctl, true);
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}
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static int bflb_reset_deassert(struct reset_ctl *reset_ctl)
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{
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return bflb_reset_set(reset_ctl, false);
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}
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static int bflb_reset_status(struct reset_ctl *reset_ctl)
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{
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const struct bflb_clk_plat *plat = dev_get_plat(reset_ctl->dev);
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const struct bflb_reset_data *data = bflb_reset_get_data(plat, reset_ctl);
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u32 mask = BIT(data->bit);
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return !!(readl(plat->base + data->reg) & mask);
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}
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static const struct reset_ops bflb_reset_ops = {
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.request = bflb_reset_request,
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.rst_assert = bflb_reset_assert,
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.rst_deassert = bflb_reset_deassert,
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.rst_status = bflb_reset_status,
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};
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U_BOOT_DRIVER(bflb_reset) = {
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.name = "bflb_reset",
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.id = UCLASS_RESET,
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.ops = &bflb_reset_ops,
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};
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