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This driver extends the clock driver with reset control capability. Signed-off-by: Samuel Holland <samuel@sholland.org>
45 lines
791 B
C
45 lines
791 B
C
// SPDX-License-Identifier: GPL-2.0+
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#ifndef _CLK_BFLB_H_
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#define _CLK_BFLB_H_
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/* Boundary between internal specifier numbers and OF consumer IDs */
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#define FW_PARENT_BASE 0xc0
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/* Used for gaps in selector values */
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#define NO_PARENT 0xff
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struct bflb_clk_data {
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const char *name;
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const u8 *parents;
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ulong rate;
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u32 sel_mask;
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u32 div_mask;
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u32 en_mask;
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u16 sel_reg;
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u16 div_reg;
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u16 en_reg;
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u16 fixed_div;
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};
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struct bflb_reset_data {
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u16 reg;
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u8 bit;
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};
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struct bflb_clk_desc {
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const struct bflb_clk_data *clks;
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const struct bflb_reset_data *resets;
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const char *const *fw_parents;
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u8 num_clks;
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u8 num_resets;
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u8 num_fw_parents;
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};
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struct bflb_clk_plat {
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void __iomem *base;
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const struct bflb_clk_desc *desc;
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};
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#endif /* _CLK_BFLB_H_ */
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