Samuel Holland 5e81022e53 riscv: Weakly define invalidate_icache_range()
Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a
vendor-specific way to invalidate a portion of the instruction cache.
Allow them to override invalidate_icache_range().

Series-to: Rick Chen <rick@andestech.com>
Series-to: Leo <ycliang@andestech.com>
Series-cc: u-boot@lists.denx.de

Signed-off-by: Samuel Holland <samuel@sholland.org>
2023-10-31 00:36:42 -05:00
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