mirror of
https://github.com/smaeul/u-boot.git
synced 2025-09-14 22:16:03 +01:00
f1775996ba
Move gpio-controller up to pinctrl node and rename label to "pio" to match the label used in upstream kernel linux. Update any DTS that reference the pinctrl to follow the new naming and structure. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com> Tested-by: Weijie Gao <weijie.gao@mediatek.com>
342 lines
8.7 KiB
Plaintext
342 lines
8.7 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
|
|
/*
|
|
* Copyright (c) 2022 MediaTek Inc.
|
|
* Author: Sam Shih <sam.shih@mediatek.com>
|
|
*/
|
|
|
|
#include <dt-bindings/interrupt-controller/irq.h>
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
#include <dt-bindings/phy/phy.h>
|
|
#include <dt-bindings/clock/mt7986-clk.h>
|
|
#include <dt-bindings/reset/mt7629-reset.h>
|
|
#include <dt-bindings/pinctrl/mt65xx.h>
|
|
|
|
/ {
|
|
compatible = "mediatek,mt7986";
|
|
interrupt-parent = <&gic>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
config {
|
|
u-boot,mmc-env-partition = "u-boot-env";
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
cpu0: cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a53";
|
|
reg = <0x0>;
|
|
mediatek,hwver = <&hwver>;
|
|
};
|
|
cpu1: cpu@1 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a53";
|
|
reg = <0x1>;
|
|
mediatek,hwver = <&hwver>;
|
|
};
|
|
cpu2: cpu@2 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a53";
|
|
reg = <0x2>;
|
|
mediatek,hwver = <&hwver>;
|
|
};
|
|
cpu3: cpu@3 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a53";
|
|
reg = <0x3>;
|
|
mediatek,hwver = <&hwver>;
|
|
};
|
|
};
|
|
|
|
dummy_clk: dummy12m {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <12000000>;
|
|
#clock-cells = <0>;
|
|
/* must need this line, or uart uanable to get dummy_clk */
|
|
bootph-all;
|
|
};
|
|
|
|
hwver: hwver {
|
|
compatible = "mediatek,hwver", "syscon";
|
|
reg = <0x8000000 0x1000>;
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupt-parent = <&gic>;
|
|
clock-frequency = <13000000>;
|
|
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
|
|
arm,cpu-registers-not-fw-configured;
|
|
};
|
|
|
|
timer0: timer@10008000 {
|
|
compatible = "mediatek,mt7986-timer";
|
|
reg = <0x10008000 0x1000>;
|
|
interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&topckgen CLK_TOP_F26M_SEL>;
|
|
clock-names = "gpt-clk";
|
|
bootph-all;
|
|
};
|
|
|
|
watchdog: watchdog@1001c000 {
|
|
compatible = "mediatek,mt7986-wdt";
|
|
reg = <0x1001c000 0x1000>;
|
|
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
|
#reset-cells = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
gic: interrupt-controller@c000000 {
|
|
compatible = "arm,gic-v3";
|
|
#interrupt-cells = <3>;
|
|
interrupt-parent = <&gic>;
|
|
interrupt-controller;
|
|
reg = <0x0c000000 0x40000>, /* GICD */
|
|
<0x0c080000 0x200000>; /* GICR */
|
|
|
|
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
fixed_plls: apmixedsys@1001E000 {
|
|
compatible = "mediatek,mt7986-fixed-plls";
|
|
reg = <0x1001E000 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
topckgen: topckgen@1001B000 {
|
|
compatible = "mediatek,mt7986-topckgen";
|
|
reg = <0x1001B000 0x1000>;
|
|
clock-parent = <&fixed_plls>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
infracfg: infracfg@10001040 {
|
|
compatible = "mediatek,mt7986-infracfg";
|
|
reg = <0x10001000 0x1000>;
|
|
clock-parent = <&topckgen>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
pio: pinctrl@1001f000 {
|
|
compatible = "mediatek,mt7986-pinctrl";
|
|
reg = <0x1001f000 0x1000>,
|
|
<0x11c30000 0x1000>,
|
|
<0x11c40000 0x1000>,
|
|
<0x11e20000 0x1000>,
|
|
<0x11e30000 0x1000>,
|
|
<0x11f00000 0x1000>,
|
|
<0x11f10000 0x1000>,
|
|
<0x1000b000 0x1000>;
|
|
reg-names = "gpio", "iocfg_rt", "iocfg_rb",
|
|
"iocfg_lt", "iocfg_lb", "iocfg_tr",
|
|
"iocfg_tl", "eint";
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
};
|
|
|
|
pwm: pwm@10048000 {
|
|
compatible = "mediatek,mt7986-pwm";
|
|
reg = <0x10048000 0x1000>;
|
|
#clock-cells = <1>;
|
|
#pwm-cells = <2>;
|
|
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&topckgen CLK_TOP_PWM_SEL>,
|
|
<&infracfg CLK_INFRA_PWM_BSEL>,
|
|
<&infracfg CLK_INFRA_PWM1_CK>,
|
|
<&infracfg CLK_INFRA_PWM2_CK>;
|
|
assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>,
|
|
<&infracfg CLK_INFRA_PWM_BSEL>,
|
|
<&infracfg CLK_INFRA_PWM1_SEL>,
|
|
<&infracfg CLK_INFRA_PWM2_SEL>;
|
|
assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D4>,
|
|
<&topckgen CLK_TOP_PWM_SEL>,
|
|
<&topckgen CLK_TOP_PWM_SEL>,
|
|
<&topckgen CLK_TOP_PWM_SEL>;
|
|
clock-names = "top", "main", "pwm1", "pwm2";
|
|
status = "disabled";
|
|
bootph-all;
|
|
};
|
|
|
|
uart0: serial@11002000 {
|
|
compatible = "mediatek,hsuart";
|
|
reg = <0x11002000 0x400>;
|
|
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&infracfg CLK_INFRA_UART0_CK>;
|
|
assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
|
|
<&infracfg CLK_INFRA_UART0_SEL>;
|
|
assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
|
|
<&topckgen CLK_TOP_UART_SEL>;
|
|
mediatek,force-highspeed;
|
|
status = "disabled";
|
|
bootph-all;
|
|
};
|
|
|
|
uart1: serial@11003000 {
|
|
compatible = "mediatek,hsuart";
|
|
reg = <0x11003000 0x400>;
|
|
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&infracfg CLK_INFRA_UART1_CK>;
|
|
assigned-clocks = <&infracfg CLK_INFRA_UART1_SEL>;
|
|
assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
|
|
mediatek,force-highspeed;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@11004000 {
|
|
compatible = "mediatek,hsuart";
|
|
reg = <0x11004000 0x400>;
|
|
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&infracfg CLK_INFRA_UART2_CK>;
|
|
assigned-clocks = <&infracfg CLK_INFRA_UART2_SEL>;
|
|
assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
|
|
mediatek,force-highspeed;
|
|
status = "disabled";
|
|
};
|
|
|
|
snand: snand@11005000 {
|
|
compatible = "mediatek,mt7986-snand";
|
|
reg = <0x11005000 0x1000>,
|
|
<0x11006000 0x1000>;
|
|
reg-names = "nfi", "ecc";
|
|
clocks = <&infracfg CLK_INFRA_SPINFI1_CK>,
|
|
<&infracfg CLK_INFRA_NFI1_CK>,
|
|
<&infracfg CLK_INFRA_NFI_HCK_CK>;
|
|
clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
|
|
assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
|
|
<&topckgen CLK_TOP_NFI1X_SEL>;
|
|
assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D8>,
|
|
<&topckgen CLK_TOP_MPLL_D8>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ethsys: syscon@15000000 {
|
|
compatible = "mediatek,mt7986-ethsys", "syscon";
|
|
reg = <0x15000000 0x1000>;
|
|
clock-parent = <&topckgen>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
eth: ethernet@15100000 {
|
|
compatible = "mediatek,mt7986-eth", "syscon";
|
|
reg = <0x15100000 0x20000>;
|
|
resets = <ðsys ETHSYS_FE_RST>;
|
|
reset-names = "fe";
|
|
mediatek,ethsys = <ðsys>;
|
|
mediatek,sgmiisys = <&sgmiisys0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sgmiisys0: syscon@10060000 {
|
|
compatible = "mediatek,mt7986-sgmiisys", "syscon";
|
|
reg = <0x10060000 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
sgmiisys1: syscon@10070000 {
|
|
compatible = "mediatek,mt7986-sgmiisys", "syscon";
|
|
reg = <0x10070000 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
spi0: spi@1100a000 {
|
|
compatible = "mediatek,ipm-spi";
|
|
reg = <0x1100a000 0x100>;
|
|
clocks = <&infracfg CLK_INFRA_SPI0_CK>,
|
|
<&topckgen CLK_TOP_SPI_SEL>;
|
|
assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>,
|
|
<&infracfg CLK_INFRA_SPI0_SEL>;
|
|
assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D2>,
|
|
<&topckgen CLK_TOP_SPI_SEL>;
|
|
clock-names = "sel-clk", "spi-clk";
|
|
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi1: spi@1100b000 {
|
|
compatible = "mediatek,ipm-spi";
|
|
reg = <0x1100b000 0x100>;
|
|
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mmc0: mmc@11230000 {
|
|
compatible = "mediatek,mt7986-mmc";
|
|
reg = <0x11230000 0x1000>,
|
|
<0x11C20000 0x1000>;
|
|
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>,
|
|
<&topckgen CLK_TOP_EMMC_250M_SEL>,
|
|
<&infracfg CLK_INFRA_MSDC_CK>;
|
|
assigned-clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>,
|
|
<&topckgen CLK_TOP_EMMC_250M_SEL>;
|
|
assigned-clock-parents = <&fixed_plls CLK_APMIXED_MPLL>,
|
|
<&topckgen CLK_TOP_NET1PLL_D5_D2>;
|
|
clock-names = "source", "hclk", "source_cg";
|
|
status = "disabled";
|
|
};
|
|
|
|
xhci: xhci@11200000 {
|
|
compatible = "mediatek,mt7986-xhci",
|
|
"mediatek,mtk-xhci";
|
|
reg = <0x11200000 0x2e00>,
|
|
<0x11203e00 0x0100>;
|
|
reg-names = "mac", "ippc";
|
|
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
|
|
phys = <&u2port0 PHY_TYPE_USB2>,
|
|
<&u3port0 PHY_TYPE_USB3>,
|
|
<&u2port1 PHY_TYPE_USB2>;
|
|
clocks = <&dummy_clk>,
|
|
<&dummy_clk>,
|
|
<&dummy_clk>,
|
|
<&dummy_clk>,
|
|
<&dummy_clk>;
|
|
clock-names = "sys_ck",
|
|
"xhci_ck",
|
|
"ref_ck",
|
|
"mcu_ck",
|
|
"dma_ck";
|
|
tpl-support;
|
|
status = "okay";
|
|
};
|
|
|
|
usbtphy: usb-phy@11e10000 {
|
|
compatible = "mediatek,mt7986",
|
|
"mediatek,generic-tphy-v2";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
status = "okay";
|
|
|
|
u2port0: usb-phy@11e10000 {
|
|
reg = <0x11e10000 0x700>;
|
|
clocks = <&dummy_clk>;
|
|
clock-names = "ref";
|
|
#phy-cells = <1>;
|
|
status = "okay";
|
|
};
|
|
|
|
u3port0: usb-phy@11e10700 {
|
|
reg = <0x11e10700 0x900>;
|
|
clocks = <&dummy_clk>;
|
|
clock-names = "ref";
|
|
#phy-cells = <1>;
|
|
status = "okay";
|
|
};
|
|
|
|
u2port1: usb-phy@11e11000 {
|
|
reg = <0x11e11000 0x700>;
|
|
clocks = <&dummy_clk>;
|
|
clock-names = "ref";
|
|
#phy-cells = <1>;
|
|
status = "okay";
|
|
};
|
|
};
|
|
};
|