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140 lines
2.8 KiB
C
140 lines
2.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Samsung Electronics
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* Thomas Abraham <thomas.ab@samsung.com>
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*/
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#include <asm/armv8/mmu.h>
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#include <linux/sizes.h>
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#if IS_ENABLED(CONFIG_EXYNOS7420)
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static struct mm_region exynos7420_mem_map[] = {
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{
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.virt = 0x10000000UL,
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.phys = 0x10000000UL,
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.size = 0x10000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN,
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}, {
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.virt = 0x40000000UL,
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.phys = 0x40000000UL,
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.size = 0x80000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE,
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}, {
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/* List terminator */
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},
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};
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struct mm_region *mem_map = exynos7420_mem_map;
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#elif CONFIG_IS_ENABLED(EXYNOS7870)
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static struct mm_region exynos7870_mem_map[] = {
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{
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.virt = 0x10000000UL,
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.phys = 0x10000000UL,
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.size = 0x10000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN,
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},
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{
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.virt = 0x40000000UL,
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.phys = 0x40000000UL,
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.size = 0x3E400000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE,
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},
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{
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.virt = 0x80000000UL,
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.phys = 0x80000000UL,
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.size = 0x40000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE,
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},
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{
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/* List terminator */
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},
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};
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struct mm_region *mem_map = exynos7870_mem_map;
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#elif CONFIG_IS_ENABLED(EXYNOS7880)
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static struct mm_region exynos7880_mem_map[] = {
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{
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.virt = 0x10000000UL,
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.phys = 0x10000000UL,
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.size = 0x10000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN,
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},
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{
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.virt = 0x40000000UL,
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.phys = 0x40000000UL,
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.size = 0x3E400000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE,
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},
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{
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.virt = 0x80000000UL,
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.phys = 0x80000000UL,
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.size = 0x80000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE,
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},
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{
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/* List terminator */
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},
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};
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struct mm_region *mem_map = exynos7880_mem_map;
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#elif IS_ENABLED(CONFIG_EXYNOS850)
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static struct mm_region exynos850_mem_map[] = {
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{
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/* iRAM */
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.virt = 0x02000000UL,
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.phys = 0x02000000UL,
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.size = SZ_2M,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* Peripheral block */
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.virt = 0x10000000UL,
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.phys = 0x10000000UL,
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.size = SZ_256M,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* DDR, 32-bit area */
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.virt = 0x80000000UL,
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.phys = 0x80000000UL,
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.size = SZ_2G,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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/* DDR, 64-bit area */
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.virt = 0x880000000UL,
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.phys = 0x880000000UL,
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.size = SZ_2G,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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/* List terminator */
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}
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};
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struct mm_region *mem_map = exynos850_mem_map;
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#endif
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