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893ae07cc9
Introduce CONFIG_PHYTEC_K3_DDR_PATCH to make DDR timing patch code optional for PHYTEC K3 boards. This allows better control over which boards receive DDR timing patches, rather than compiling the code for all boards with K3_DDRSS enabled. Also enable the feature by default for PHYCORE_AM62X_R5. Signed-off-by: Garrett Giordano <ggiordano@phytec.com> Reviewed-by: Wadim Egorov <w.egorov@phytec.de>
74 lines
1.5 KiB
Plaintext
74 lines
1.5 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
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# Andrew Davis <afd@ti.com>
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if SOC_K3_AM625
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choice
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prompt "K3 AM62x based boards"
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optional
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config TARGET_AM625_A53_EVM
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bool "TI K3 based AM625 EVM running on A53"
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select ARM64
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select BINMAN
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select OF_SYSTEM_SETUP
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config TARGET_AM625_R5_EVM
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bool "TI K3 based AM625 EVM running on R5"
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select CPU_V7R
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select SYS_THUMB_BUILD
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select K3_LOAD_SYSFW
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select RAM
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select SPL_RAM
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select K3_DDRSS
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select BINMAN
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imply SYS_K3_SPL_ATF
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config TARGET_PHYCORE_AM62X_A53
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bool "PHYTEC phyCORE-AM62x running on A53"
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select ARM64
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select BINMAN
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select OF_SYSTEM_SETUP
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imply OF_UPSTREAM
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config TARGET_PHYCORE_AM62X_R5
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bool "PHYTEC phyCORE-AM62x running on R5"
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select CPU_V7R
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select SYS_THUMB_BUILD
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select K3_LOAD_SYSFW
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select RAM
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select SPL_RAM
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select K3_DDRSS
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select BINMAN
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select PHYTEC_K3_DDR_PATCH
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imply SYS_K3_SPL_ATF
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config TARGET_VERDIN_AM62_A53
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bool "Toradex Verdin AM62 running on A53"
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select ARM64
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select BINMAN
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select OF_SYSTEM_SETUP
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imply OF_UPSTREAM
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config TARGET_VERDIN_AM62_R5
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bool "Toradex Verdin AM62 running on R5"
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select CPU_V7R
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select SYS_THUMB_BUILD
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select K3_LOAD_SYSFW
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select RAM
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select SPL_RAM
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select K3_DDRSS
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select BINMAN
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imply SYS_K3_SPL_ATF
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endchoice
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source "board/beagle/beagleplay/Kconfig"
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source "board/phytec/phycore_am62x/Kconfig"
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source "board/ti/am62x/Kconfig"
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source "board/toradex/verdin-am62/Kconfig"
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endif
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