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https://github.com/smaeul/u-boot.git
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ed4b0ce247
See commit 008ba0d56d00 ("rockchip: Add common default bss and stack
addresses") for memory layout. This migrates PX30 to use the new layout,
except for TPL. Indeed, PX30 is extremely limited in SRAM, so we need to
be extra careful about what goes into the TPL and how much we can
allocate there, so let's keep the current value for
TPL_SYS_MALLOC_F_LEN (already present in the PX30-specific Kconfig, from
an earlier commit).
This will allow us to use the same memory layout on one more Rockchip
SoC, which is always a nice thing. Additionally, this will make it
easier to fix U-Boot proper pre-reloc running out of memory on PX30 in a
subsequent commit.
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
107 lines
3.1 KiB
Plaintext
107 lines
3.1 KiB
Plaintext
if ROCKCHIP_PX30
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config TARGET_EVB_PX30
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bool "EVB_PX30"
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help
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This target config option used for below listed px30 boards.
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EVB_PX30:
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* EVB_PX30 is an evaluation board for Rockchip PX30.
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config TARGET_ODROID_GO2
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bool "ODROID_GO2"
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config TARGET_PX30_CORE
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bool "Engicam PX30.Core"
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help
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PX30.Core EDIMM2.2:
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* PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.
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* EDIMM2.2 is a Form Factor Capacitive Evaluation Board from Engicam.
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* PX30.Core needs to mount on top of EDIMM2.2 for creating complete
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PX30.Core EDIMM2.2 Starter Kit.
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PX30.Core CTOUCH2:
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* PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.
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* CTOUCH2.0 is a general purpose Carrier board with capacitive
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touch interface support.
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* PX30.Core needs to mount on top of CTOUCH2.0 for creating complete
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PX30.Core C.TOUCH Carrier board.
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PX30.Core CTOUCH2-OF10:
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* PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.
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* CTOUCH2.0 is a general purpose Carrier board with capacitive
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touch interface support.
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* 10.1" OF is a capacitive touch 10.1" Open Frame panel solutions.
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* PX30.Core needs to mount on top of C.TOUCH 2.0 carrier with pluged
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10.1" OF for creating complete PX30.Core C.TOUCH 2.0 10.1" Open Frame.
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config TARGET_RINGNECK_PX30
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bool "Theobroma Systems PX30-uQ7 (Ringneck)"
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help
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The PX30-uQ7 (Ringneck) SoM is a uQseven-compatible (40mmx70mm,
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MXM-230 connector) system-on-module from Theobroma Systems[1],
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featuring the Rockchip PX30.
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It provides the following feature set:
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* up to 4GB DDR4
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* up to 128GB on-module eMMC (with 8-bit 1.8V interface)
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* SD card (on a baseboard) via edge connector
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* Fast Ethernet with on-module TI DP83825I PHY
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* MIPI-DSI/LVDS
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* MIPI-CSI
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* USB
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- 1x USB 2.0 dual-role
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- 3x USB 2.0 host
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* on-module companion controller (STM32 Cortex-M0 or ATtiny), implementing:
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- low-power RTC functionality (ISL1208 emulation)
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- fan controller (AMC6821 emulation)
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- USB<->CAN bridge controller (STM32 only)
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* on-module Espressif ESP32 for Bluetooth + 2.4GHz WiFi
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* on-module NXP SE05x Secure Element
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config ROCKCHIP_BOOT_MODE_REG
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default 0xff010200
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config ROCKCHIP_STIMER_BASE
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default 0xff220020
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config SYS_SOC
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default "px30"
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config ROCKCHIP_COMMON_STACK_ADDR
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default y
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config SYS_MALLOC_F_LEN
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default 0x400 if !SPL_SHARES_INIT_SP_ADDR
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config SPL_SERIAL
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default y
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config TPL_LDSCRIPT
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default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds"
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config TPL_TEXT_BASE
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default 0xff0e1000
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config TPL_STACK
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default 0xff0e4fff
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config TPL_SYS_MALLOC_F_LEN
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default 0x600
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config DEBUG_UART_CHANNEL
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int "Mux channel to use for debug UART2/UART3"
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depends on DEBUG_UART_BOARD_INIT
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default 0
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help
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UART2 and UART3 can use two different set of pins to route the output.
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For using the UART for early debugging the route to use needs
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to be declared (0 or 1).
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source "board/engicam/px30_core/Kconfig"
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source "board/hardkernel/odroid_go2/Kconfig"
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source "board/rockchip/evb_px30/Kconfig"
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source "board/theobroma-systems/ringneck_px30/Kconfig"
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endif
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