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https://github.com/smaeul/u-boot.git
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1c2ffcd5e6
Implement checkboard() to print current SoC model used by a board, e.g. one of: SoC: RK3582 SoC: RK3588 SoC: RK3588J SoC: RK3588S SoC: RK3588S2 when U-Boot proper is running. U-Boot 2025.01-rc1 (Nov 10 2024 - 00:31:29 +0000) Model: Generic RK3588S/RK3588 SoC: RK3588S2 DRAM: 8 GiB Information about the SoC model and variant is read from OTP. Also update rk3588s-u-boot.dtsi to include OTP in U-Boot pre-reloc phase, where checkboard() is called. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Tested-by: FUKAUMI Naoki <naoki@radxa.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
233 lines
6.6 KiB
C
233 lines
6.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2021 Rockchip Electronics Co., Ltd
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* Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
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*/
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#define LOG_CATEGORY LOGC_ARCH
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#include <dm.h>
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#include <misc.h>
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#include <spl.h>
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#include <asm/armv8/mmu.h>
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#include <asm/arch-rockchip/bootrom.h>
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#include <asm/arch-rockchip/grf_rk3588.h>
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#include <asm/arch-rockchip/hardware.h>
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#include <asm/arch-rockchip/ioc_rk3588.h>
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#define FIREWALL_DDR_BASE 0xfe030000
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#define FW_DDR_MST5_REG 0x54
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#define FW_DDR_MST13_REG 0x74
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#define FW_DDR_MST21_REG 0x94
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#define FW_DDR_MST26_REG 0xa8
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#define FW_DDR_MST27_REG 0xac
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#define FIREWALL_SYSMEM_BASE 0xfe038000
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#define FW_SYSM_MST5_REG 0x54
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#define FW_SYSM_MST13_REG 0x74
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#define FW_SYSM_MST21_REG 0x94
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#define FW_SYSM_MST26_REG 0xa8
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#define FW_SYSM_MST27_REG 0xac
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#define BUS_IOC_GPIO2A_IOMUX_SEL_L 0x40
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#define BUS_IOC_GPIO2B_IOMUX_SEL_L 0x48
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#define BUS_IOC_GPIO2D_IOMUX_SEL_L 0x58
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#define BUS_IOC_GPIO2D_IOMUX_SEL_H 0x5c
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#define BUS_IOC_GPIO3A_IOMUX_SEL_L 0x60
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#define SYS_GRF_FORCE_JTAG BIT(14)
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/**
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* Boot-device identifiers used by the BROM on RK3588 when device is booted
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* from SPI flash. IOMUX used for SPI flash affect the value used by the BROM
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* and not the type of SPI flash used.
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*/
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enum {
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BROM_BOOTSOURCE_FSPI_M0 = 3,
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BROM_BOOTSOURCE_FSPI_M1 = 4,
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BROM_BOOTSOURCE_FSPI_M2 = 6,
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};
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const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
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[BROM_BOOTSOURCE_EMMC] = "/mmc@fe2e0000",
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[BROM_BOOTSOURCE_FSPI_M0] = "/spi@fe2b0000/flash@0",
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[BROM_BOOTSOURCE_FSPI_M1] = "/spi@fe2b0000/flash@0",
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[BROM_BOOTSOURCE_FSPI_M2] = "/spi@fe2b0000/flash@0",
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[BROM_BOOTSOURCE_SD] = "/mmc@fe2c0000",
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};
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static struct mm_region rk3588_mem_map[] = {
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{
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.virt = 0x0UL,
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.phys = 0x0UL,
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.size = 0xf0000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.virt = 0xf0000000UL,
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.phys = 0xf0000000UL,
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.size = 0x10000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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.virt = 0x900000000,
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.phys = 0x900000000,
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.size = 0x150000000,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = rk3588_mem_map;
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/* GPIO0B_IOMUX_SEL_H */
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enum {
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GPIO0B5_SHIFT = 4,
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GPIO0B5_MASK = GENMASK(7, 4),
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GPIO0B5_REFER = 8,
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GPIO0B5_UART2_TX_M0 = 10,
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GPIO0B6_SHIFT = 8,
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GPIO0B6_MASK = GENMASK(11, 8),
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GPIO0B6_REFER = 8,
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GPIO0B6_UART2_RX_M0 = 10,
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};
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void board_debug_uart_init(void)
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{
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__maybe_unused static struct rk3588_bus_ioc * const bus_ioc = (void *)BUS_IOC_BASE;
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static struct rk3588_pmu2_ioc * const pmu2_ioc = (void *)PMU2_IOC_BASE;
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/* Refer to BUS_IOC */
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rk_clrsetreg(&pmu2_ioc->gpio0b_iomux_sel_h,
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GPIO0B6_MASK | GPIO0B5_MASK,
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GPIO0B6_REFER << GPIO0B6_SHIFT |
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GPIO0B5_REFER << GPIO0B5_SHIFT);
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/* UART2_M0 Switch iomux */
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rk_clrsetreg(&bus_ioc->gpio0b_iomux_sel_h,
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GPIO0B6_MASK | GPIO0B5_MASK,
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GPIO0B6_UART2_RX_M0 << GPIO0B6_SHIFT |
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GPIO0B5_UART2_TX_M0 << GPIO0B5_SHIFT);
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}
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#ifdef CONFIG_XPL_BUILD
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void rockchip_stimer_init(void)
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{
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/* If Timer already enabled, don't re-init it */
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u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x4);
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if (reg & 0x1)
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return;
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asm volatile("msr CNTFRQ_EL0, %0" : : "r" (CONFIG_COUNTER_FREQUENCY));
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writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x14);
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writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x18);
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writel(0x1, CONFIG_ROCKCHIP_STIMER_BASE + 0x4);
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}
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#endif
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#ifndef CONFIG_TPL_BUILD
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int arch_cpu_init(void)
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{
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#ifdef CONFIG_XPL_BUILD
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#ifdef CONFIG_ROCKCHIP_DISABLE_FORCE_JTAG
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static struct rk3588_sysgrf * const sys_grf = (void *)SYS_GRF_BASE;
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#endif
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int secure_reg;
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/* Set the SDMMC eMMC crypto_ns FSPI access secure area */
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secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST5_REG);
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secure_reg &= 0xffff;
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writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST5_REG);
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secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST13_REG);
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secure_reg &= 0xffff;
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writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST13_REG);
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secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST21_REG);
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secure_reg &= 0xffff;
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writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST21_REG);
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secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST26_REG);
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secure_reg &= 0xffff;
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writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST26_REG);
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secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST27_REG);
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secure_reg &= 0xffff0000;
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writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST27_REG);
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secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST5_REG);
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secure_reg &= 0xffff;
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writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST5_REG);
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secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST13_REG);
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secure_reg &= 0xffff;
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writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST13_REG);
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secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST21_REG);
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secure_reg &= 0xffff;
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writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST21_REG);
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secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST26_REG);
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secure_reg &= 0xffff;
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writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST26_REG);
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secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST27_REG);
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secure_reg &= 0xffff0000;
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writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST27_REG);
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#ifdef CONFIG_ROCKCHIP_DISABLE_FORCE_JTAG
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/* Disable JTAG exposed on SDMMC */
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rk_clrreg(&sys_grf->soc_con[6], SYS_GRF_FORCE_JTAG);
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#endif
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#endif
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return 0;
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}
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#endif
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#define RK3588_OTP_CPU_CODE_OFFSET 0x02
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#define RK3588_OTP_SPECIFICATION_OFFSET 0x06
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int checkboard(void)
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{
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u8 cpu_code[2], specification, package;
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struct udevice *dev;
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char suffix[3];
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int ret;
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if (!IS_ENABLED(CONFIG_ROCKCHIP_OTP) || !CONFIG_IS_ENABLED(MISC))
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return 0;
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ret = uclass_get_device_by_driver(UCLASS_MISC,
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DM_DRIVER_GET(rockchip_otp), &dev);
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if (ret) {
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log_debug("Could not find otp device, ret=%d\n", ret);
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return 0;
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}
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/* cpu-code: SoC model, e.g. 0x35 0x82 or 0x35 0x88 */
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ret = misc_read(dev, RK3588_OTP_CPU_CODE_OFFSET, cpu_code, 2);
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if (ret < 0) {
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log_debug("Could not read cpu-code, ret=%d\n", ret);
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return 0;
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}
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/* specification: SoC variant, e.g. 0xA for RK3588J and 0x13 for RK3588S */
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ret = misc_read(dev, RK3588_OTP_SPECIFICATION_OFFSET, &specification, 1);
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if (ret < 0) {
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log_debug("Could not read specification, ret=%d\n", ret);
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return 0;
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}
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/* package: likely SoC variant revision, 0x2 for RK3588S2 */
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package = specification >> 5;
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specification &= 0x1f;
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/* for RK3588J i.e. '@' + 0xA = 'J' */
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suffix[0] = specification > 1 ? '@' + specification : '\0';
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/* for RK3588S2 i.e. '0' + 0x2 = '2' */
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suffix[1] = package > 1 ? '0' + package : '\0';
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suffix[2] = '\0';
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printf("SoC: RK%02x%02x%s\n", cpu_code[0], cpu_code[1], suffix);
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return 0;
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}
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