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03de305ec4
As part of bringing the master branch back in to next, we need to allow for all of these changes to exist here. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
51 lines
1.8 KiB
C
51 lines
1.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* (C) Copyright 2022 - Analog Devices, Inc.
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*
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* Written and/or maintained by Timesys Corporation
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*
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* Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
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* Contact: Greg Malysa <greg.malysa@timesys.com>
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*/
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#ifndef MT41K512M16HA_H
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#define MT41K512M16HA_H
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/* Default DDR3 part assumed: MT41K512M16HA-107, 8Gb part */
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/* For DCLK= 450 MHz */
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#define DMC_DLLCALRDCNT 72
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#define DMC_DATACYC 9
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#define DMC_TRCD 7
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#define DMC_TWTR 4
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#define DMC_TRP 7
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#define DMC_TRAS 10
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#define DMC_TRC 16
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#define DMC_TMRD 4
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#define DMC_TREF 3510
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#define DMC_TRFC 158
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#define DMC_TRRD 6
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#define DMC_TFAW 16
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#define DMC_TRTP 4
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#define DMC_TWR 7
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#define DMC_TXP 3
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#define DMC_TCKE 3
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#define DMC_CL0 0
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#define DMC_CL123 3
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#define DMC_WRRECOV (DMC_TWR - 1)
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#define DMC_MR1_DLLEN 0
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#define DMC_MR1_DIC0 1
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#define DMC_MR1_RTT0 1
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#define DMC_MR1_AL 0
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#define DMC_MR1_DIC1 0
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#define DMC_MR1_RTT1 0
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#define DMC_MR1_WL 0
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#define DMC_MR1_RTT2 0
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#define DMC_MR1_TDQS 0
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#define DMC_MR1_QOFF 0
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#define DMC_WL 1
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#define DMC_RDTOWR 2
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#define DMC_CTL_AL_EN 0
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#define SDR_CHIP_SIZE ENUM_DMC_CFG_SDRSIZE8G
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#endif
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