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AST2700 SoCs integrates a Ibex 32-bits RISC-V core as the boot MCU for the first stage bootloader execution, namely SPL. This patch implements the preliminary base to successfully run SPL on this RV32-based MCU to the console banner message. Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
7 lines
119 B
Plaintext
7 lines
119 B
Plaintext
config RISCV_AST2700
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bool
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imply CPU
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imply CPU_RISCV
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help
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Run U-Boot on AST2700 with IBex RISC-V CPU integrated.
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