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AST2700 SoCs integrates a Ibex 32-bits RISC-V core as the boot MCU for the first stage bootloader execution, namely SPL. This patch implements the preliminary base to successfully run SPL on this RV32-based MCU to the console banner message. Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
77 lines
1.5 KiB
Plaintext
77 lines
1.5 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/ {
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model = "Aspeed AST2700 Ibex BootMCU";
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compatible = "aspeed,ast2700-ibex";
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "lowrisc,ibex";
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device_type = "cpu";
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reg = <0>;
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comptaible = "riscv";
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riscv,isa = "rv32imc";
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};
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};
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memory@80000000 {
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reg = <0x80000000 0x80000000>;
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};
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soc0: soc@12000000 {
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compatible = "aspeed,soc1","simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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sdrammc: sdrammc@12c00000 {
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compatible = "aspeed,ast2700-sdrammc";
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reg = <0x12c00000 0x3000>, <0x13000000 0x1000>;
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aspeed,scu0 = <&syscon0>;
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aspeed,scu1 = <&syscon1>;
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};
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syscon0: syscon@12c02000 {
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compatible = "aspeed,ast2700-scu0", "syscon", "simple-mfd";
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reg = <0x12c02000 0x1000>;
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ranges = <0 0x12c02000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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};
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soc1: soc@14000000 {
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compatible = "aspeed,soc1","simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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syscon1: syscon@14c02000 {
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compatible = "aspeed,ast2700-scu1", "syscon", "simple-mfd";
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reg = <0x14c02000 0x1000>;
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ranges = <0 0x14c02000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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uart12: serial@14c33b00 {
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compatible = "ns16550a";
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reg = <0x14c33b00 0x20>;
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reg-shift = <2>;
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no-loopback-test;
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clock-frequency = <1846153>;
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status = "disabled";
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};
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ast_ibex_timer: timer {
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compatible = "aspeed,ast2700-ibex-timer";
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clock-frequency = <200000000>;
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};
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};
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};
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