mirror of
https://github.com/smaeul/u-boot.git
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9c4d760637
Split out StarFive VisionFive2 multi-board target specific configuration into starfive-visionfive2-binman.dtsi in preparation for removal of jh7110-u-boot and jh7110-common-u-boot in part or whole as sent upstream. Signed-off-by: E Shattow <e@freeshell.de> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
101 lines
1.4 KiB
Plaintext
101 lines
1.4 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0 OR MIT
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/*
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* Copyright (C) 2023 StarFive Technology Co., Ltd.
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*/
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#include "jh7110-u-boot.dtsi"
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/ {
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aliases {
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spi0 = &qspi;
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};
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chosen {
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bootph-pre-ram;
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};
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firmware {
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spi0 = &qspi;
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bootph-pre-ram;
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};
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memory@40000000 {
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bootph-pre-ram;
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};
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};
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&uart0 {
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bootph-pre-ram;
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reg-offset = <0>;
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current-speed = <115200>;
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clock-frequency = <24000000>;
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};
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&mmc0 {
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bootph-pre-ram;
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};
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&mmc1 {
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bootph-pre-ram;
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};
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&qspi {
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bootph-pre-ram;
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flash@0 {
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bootph-pre-ram;
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cdns,read-delay = <2>;
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spi-max-frequency = <100000000>;
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};
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};
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&syscrg {
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assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,
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<&syscrg JH7110_SYSCLK_BUS_ROOT>,
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<&syscrg JH7110_SYSCLK_PERH_ROOT>,
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<&syscrg JH7110_SYSCLK_QSPI_REF>;
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assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>,
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<&pllclk JH7110_PLLCLK_PLL2_OUT>,
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<&pllclk JH7110_PLLCLK_PLL2_OUT>,
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<&syscrg JH7110_SYSCLK_QSPI_REF_SRC>;
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assigned-clock-rates = <0>, <0>, <0>, <0>;
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};
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&sysgpio {
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bootph-pre-ram;
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};
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&mmc0_pins {
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bootph-pre-ram;
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rst-pins {
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bootph-pre-ram;
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};
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};
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&mmc1_pins {
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bootph-pre-ram;
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clk-pins {
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bootph-pre-ram;
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};
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mmc-pins {
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bootph-pre-ram;
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};
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};
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&i2c5_pins {
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bootph-pre-ram;
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i2c-pins {
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bootph-pre-ram;
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};
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};
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&i2c5 {
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bootph-pre-ram;
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eeprom@50 {
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bootph-pre-ram;
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compatible = "atmel,24c04";
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reg = <0x50>;
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pagesize = <16>;
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};
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};
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