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9efcb10a09
AST2700 SoCs integrates a Ibex 32-bits RISC-V core as the boot MCU for the first stage bootloader execution, namely SPL. This patch implements the preliminary base to successfully run SPL on this RV32-based MCU to the console banner message. Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
146 lines
5.7 KiB
C
146 lines
5.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (c) Aspeed Technology Inc.
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*/
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#ifndef __ASM_AST2700_SCU_H__
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#define __ASM_AST2700_SCU_H__
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/* SCU0: CPU-die SCU */
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#define SCU0_HWSTRAP 0x010
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#define SCU0_HWSTRAP_DIS_RVAS BIT(30)
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#define SCU0_HWSTRAP_DIS_WDTFULL BIT(25)
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#define SCU0_HWSTRAP_DISARMICE_TZ BIT(22)
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#define SCU0_HWSTRAP_DISABLE_XHCI BIT(21)
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#define SCU0_HWSTRAP_BOOTEMMCSPEED BIT(20)
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#define SCU0_HWSTRAP_VGA_CC BIT(18)
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#define SCU0_HWSTRAP_EN_OPROM BIT(17)
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#define SCU0_HWSTRAP_DISARMICE BIT(16)
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#define SCU0_HWSTRAP_TSPRSNTSEL BIT(9)
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#define SCU0_HWSTRAP_DISDEBUG BIT(8)
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#define SCU0_HWSTRAP_HCLKHPLL BIT(7)
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#define SCU0_HWSTRAP_HCLKSEL GENMASK(6, 5)
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#define SCU0_HWSTRAP_CPUHPLL BIT(4)
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#define SCU0_HWSTRAP_HPLLFREQ GENMASK(3, 2)
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#define SCU0_HWSTRAP_BOOTSPI BIT(1)
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#define SCU0_HWSTRAP_HWSTRAP_DISCPU BIT(0)
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#define SCU0_DBGCTL 0x0c8
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#define SCU0_DBGCTL_MASK GENMASK(14, 0)
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#define SCU0_DBGCTL_UARTDBG BIT(1)
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#define SCU0_RSTCTL1 0x200
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#define SCU0_RSTCTL1_EMMC BIT(17)
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#define SCU0_RSTCTL1_HACE BIT(4)
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#define SCU0_RSTCTL1_CLR 0x204
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#define SCU0_RSTCTL1_CLR_EMMC BIT(17)
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#define SCU0_RSTCTL1_CLR_HACE BIT(4)
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#define SCU0_CLKGATE1 0x240
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#define SCU0_CLKGATE1_EMMC BIT(27)
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#define SCU0_CLKGATE1_HACE BIT(13)
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#define SCU0_CLKGATE1_DDRPHY BIT(11)
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#define SCU0_CLKGATE1_CLR 0x244
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#define SCU0_CLKGATE1_CLR_EMMC BIT(27)
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#define SCU0_CLKGATE1_CLR_HACE BIT(13)
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#define SCU0_CLKGATE1_CLR_DDRPHY BIT(11)
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#define SCU0_VGA0_SCRATCH 0x900
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#define SCU0_VGA0_SCRATCH_DRAM_INIT BIT(6)
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#define SCU0_PCI_MISC70 0xa70
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#define SCU0_PCI_MISC70_EN_PCIEXHCI0 BIT(3)
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#define SCU0_PCI_MISC70_EN_PCIEEHCI0 BIT(2)
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#define SCU0_PCI_MISC70_EN_PCIEVGA0 BIT(0)
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#define SCU0_PCI_MISC80 0xa80
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#define SCU0_PCI_MISC80_EN_PCIEXHCI1 BIT(3)
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#define SCU0_PCI_MISC80_EN_PCIEEHCI1 BIT(2)
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#define SCU0_PCI_MISC80_EN_PCIEVGA1 BIT(0)
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#define SCU0_PCI_MISCF0 0xaf0
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#define SCU0_PCI_MISCF0_EN_PCIEXHCI1 BIT(3)
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#define SCU0_PCI_MISCF0_EN_PCIEEHCI1 BIT(2)
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#define SCU0_PCI_MISCF0_EN_PCIEVGA1 BIT(0)
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#define SCU0_WPROT1 0xe04
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#define SCU0_WPROT1_0C8 BIT(18)
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/* SCU1: IO-die SCU */
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#define SCU1_REVISION 0x000
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#define SCU1_REVISION_HWID GENMASK(23, 16)
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#define SCU1_REVISION_CHIP_EFUSE GENMASK(15, 8)
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#define SCU1_HWSTRAP1 0x010
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#define SCU1_HWSTRAP1_DIS_CPTRA BIT(30)
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#define SCU1_HWSTRAP1_RECOVERY_USB_PORT GENMASK(29, 28)
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#define SCU1_HWSTRAP1_RECOVERY_INTERFACE GENMASK(27, 26)
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#define SCU1_HWSTRAP1_RECOVERY_I3C (BIT(26) | BIT(27))
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#define SCU1_HWSTRAP1_RECOVERY_I2C BIT(27)
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#define SCU1_HWSTRAP1_RECOVERY_USB BIT(26)
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#define SCU1_HWSTRAP1_SPI_FLASH_4_BYTE_MODE BIT(25)
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#define SCU1_HWSTRAP1_SPI_FLASH_WAIT_READY BIT(24)
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#define SCU1_HWSTRAP1_BOOT_UFS BIT(23)
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#define SCU1_HWSTRAP1_DIS_ROM BIT(22)
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#define SCU1_HWSTRAP1_DIS_CPTRAJTAG BIT(20)
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#define SCU1_HWSTRAP1_UARTDBGSEL BIT(19)
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#define SCU1_HWSTRAP1_DIS_UARTDBG BIT(18)
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#define SCU1_HWSTRAP1_DIS_WDTFULL BIT(17)
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#define SCU1_HWSTRAP1_DISDEBUG1 BIT(16)
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#define SCU1_HWSTRAP1_LTPI0_IO_DRIVING GENMASK(15, 14)
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#define SCU1_HWSTRAP1_ACPI_1 BIT(13)
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#define SCU1_HWSTRAP1_ACPI_0 BIT(12)
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#define SCU1_HWSTRAP1_BOOT_EMMC_UFS BIT(11)
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#define SCU1_HWSTRAP1_DDR4 BIT(10)
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#define SCU1_HWSTRAP1_LOW_SECURE BIT(8)
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#define SCU1_HWSTRAP1_EN_EMCS BIT(7)
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#define SCU1_HWSTRAP1_EN_GPIOPT BIT(6)
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#define SCU1_HWSTRAP1_EN_SECBOOT BIT(5)
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#define SCU1_HWSTRAP1_EN_RECOVERY_BOOT BIT(4)
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#define SCU1_HWSTRAP1_LTPI0_EN BIT(3)
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#define SCU1_HWSTRAP1_LTPI_IDX BIT(2)
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#define SCU1_HWSTRAP1_LTPI1_EN BIT(1)
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#define SCU1_HWSTRAP1_LTPI_MODE BIT(0)
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#define SCU1_HWSTRAP2 0x030
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#define SCU1_HWSTRAP2_FMC_ABR_SINGLE_FLASH BIT(29)
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#define SCU1_HWSTRAP2_FMC_ABR_CS_SWAP_DIS BIT(28)
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#define SCU1_HWSTRAP2_SPI_TPM_PCR_EXT_EN BIT(27)
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#define SCU1_HWSTRAP2_SPI_TPM_HASH_ALGO GENMASK(26, 25)
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#define SCU1_HWSTRAP2_BOOT_SPI_FREQ GENMASK(24, 23)
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#define SCU1_HWSTRAP2_RESERVED GENMASK(22, 19)
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#define SCU1_HWSTRAP2_FWSPI_CRTM GENMASK(18, 17)
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#define SCU1_HWSTRAP2_EN_FWSPIAUX BIT(16)
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#define SCU1_HWSTRAP2_FWSPISIZE GENMASK(15, 13)
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#define SCU1_HWSTRAP2_DIS_REC BIT(12)
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#define SCU1_HWSTRAP2_EN_CPTRA_DBG BIT(11)
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#define SCU1_HWSTRAP2_TPM_PCR_INDEX GENMASK(6, 2)
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#define SCU1_HWSTRAP2_ROM_CLEAR_SRAM BIT(1)
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#define SCU1_HWSTRAP2_ABR BIT(0)
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#define SCU1_RSTLOG0 0x050
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#define SCU1_RSTLOG0_BMC_CPU BIT(12)
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#define SCU1_RSTLOG0_ABR BIT(2)
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#define SCU1_RSTLOG0_EXTRSTN BIT(1)
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#define SCU1_RSTLOG0_SRST BIT(0)
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#define SCU1_MISC1 0x0c0
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#define SCU1_MISC1_UARTDBG_ROUTE GENMASK(23, 22)
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#define SCU1_MISC1_UART12_ROUTE GENMASK(21, 20)
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#define SCU1_DBGCTL 0x0c8
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#define SCU1_DBGCTL_MASK GENMASK(7, 0)
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#define SCU1_DBGCTL_UARTDBG BIT(6)
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#define SCU1_RNG_DATA 0x0f4
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#define SCU1_RSTCTL1 0x200
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#define SCU1_RSTCTL1_I3C(x) (BIT(16) << (x))
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#define SCU1_RSTCTL1_CLR 0x204
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#define SCU1_RSTCTL1_CLR_I3C(x) (BIT(16) << (x))
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#define SCU1_RSTCTL2 0x220
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#define SCU1_RSTCTL2_LTPI1 BIT(22)
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#define SCU1_RSTCTL2_LTPI0 BIT(20)
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#define SCU1_RSTCTL2_I2C BIT(15)
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#define SCU1_RSTCTL2_CPTRA BIT(9)
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#define SCU1_RSTCTL2_CLR 0x224
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#define SCU1_RSTCTL2_CLR_I2C BIT(15)
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#define SCU1_RSTCTL2_CLR_CPTRA BIT(9)
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#define SCU1_CLKGATE1 0x240
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#define SCU1_CLKGATE1_I3C(x) (BIT(16) << (x))
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#define SCU1_CLKGATE1_I2C BIT(15)
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#define SCU1_CLKGATE1_CLR 0x244
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#define SCU1_CLKGATE1_CLR_I3C(x) (BIT(16) << (x))
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#define SCU1_CLKGATE1_CLR_I2C BIT(15)
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#define SCU1_CLKGATE2 0x260
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#define SCU1_CLKGATE2_LTPI1_TX BIT(19)
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#define SCU1_CLKGATE2_LTPI_AHB BIT(10)
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#define SCU1_CLKGATE2_LTPI0_TX BIT(9)
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#define SCU1_CLKGATE2_CLR 0x264
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#endif
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